US20040241926A1 - Contactless mask progammable rom - Google Patents
Contactless mask progammable rom Download PDFInfo
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- US20040241926A1 US20040241926A1 US10/477,880 US47788003A US2004241926A1 US 20040241926 A1 US20040241926 A1 US 20040241926A1 US 47788003 A US47788003 A US 47788003A US 2004241926 A1 US2004241926 A1 US 2004241926A1
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- memory cells
- diffusions
- mask rom
- threshold voltage
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/36—Gate programmed, e.g. different gate material or no gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/383—Channel doping programmed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/34—Source electrode or drain electrode programmed
Definitions
- the present invention relates to a semiconductor device. More particularly, the present invention relates to a contactless mask programmable read-only memory (Mask ROM).
- Mosk ROM contactless mask programmable read-only memory
- Read-only memory is a type of non-volatile memory, which can retain data as disconnected from power supply and is therefore used to store permanent data, such as booting data of computer systems.
- FIG. 1 illustrates a top view of a contact ROM in the prior art.
- the contact ROM 100 comprises rows and columns of MOS-type memory cells, wherein two adjacent memory cells in the same column constitute a cell pair 102 that is isolated by field isolation 104 .
- the memory cells in the same row are controlled by a word line 106 , and the memory cells in the same column are located under a bit line 108 .
- the two memory cells in a cell pair 102 share a source 110 between the two drains 112 thereof, while the sources 110 of the cell pairs 102 in the same row are electrically connected to a ground line 114 .
- a plurality of contacts 116 are selectively formed on the drains 112 of the memory cells as data codes, wherein the contacts in the same column are connected to a bit line 108 .
- the selected word line 106 is biased to high level. If the drain 112 of the selected memory cell has a contact 116 thereon electrically connecting with the selected bit line 108 , a current can be conducted from the selected bit line 108 to the ground line 114 connecting with the source 110 of the selected memory cell. Otherwise, no current is detected. In other words, the data is stored as a contact pattern. However, since the field isolation 104 is formed between two rows of cell pairs 102 and contacts 116 are formed on the drains 112 , the area of the memory array is large and the device integration is low.
- FIG. 2 illustrates a top view of an implant programmable ROM in the prior art.
- the implant programmable ROM 200 comprises rows and columns of MOS-type memory cells 201 .
- the memory cells in the same row are controlled by a word line 202 and every two rows of memory cells 201 are coupled to a ground line 204 , while two columns of memory cells 201 are separated by isolation 203 .
- a memory cell 201 shares a source 206 with one adjacent memory cell in the same column, and shares a drain 208 with the other adjacent memory cell in the same column.
- the sources 206 of the memory cells 201 in the same row are connected to a ground line 204 , and the drains 208 of the memory cells 201 in the same column are electrically connected to a bit line 210 via contacts 212 .
- the implant programmable ROM 200 is programmed by selectively implanting ions into the channel regions under the word lines 202 to make the selected channel regions 214 have a higher threshold voltage (V T ). During the reading operation of the implant programmable ROM, the selected word line 202 is biased to high level. If the channel region of the selected memory cell 201 is not implanted, the channel can be switched on and an On-current can be detected, otherwise the channel cannot be switched on and the channel current is extremely small.
- the implant programmable ROM 200 is more compact because the isolation between rows of memory cells is omitted and a drain 208 is shared by two memory cells 201 like a source 206 .
- the fabricating process is more complex.
- the degree of area reduction of the drain region 208 is limited and the memory array cannot be further miniaturized.
- FIG. 3 illustrates a top view of a Metal ROM in the prior art.
- the Metal ROM 300 has a NAND (NOT AND) structure and comprises rows and columns of MOS-type memory cells.
- the memory cells in the same row are controlled by a word line 302 and four continuous memory cells in the same column are grouped as a memory string 304 .
- the diffusion 305 of one terminal memory cell is electrically connected to a ground line 306
- the diffusion 305 of the other terminal memory cell is coupled to a bank select transistor 308 .
- the bank select transistor 308 is coupled to a bit line 320 parallel to the memory string 304 via a contact 322 .
- the source and the drain of a memory cell, i.e., the two diffusions 305 of a memory cell are both shared by adjacent cells.
- the Metal ROM is programmed by selectively forming local interconnects 326 each connecting the two diffusions 305 of a selected memory cell. If a memory cell has a local interconnect 326 formed thereon like memory cell C 1 does, the memory cell is always electrically conductible and acts like a depletion-type MOS devices, otherwise the memory cell is in the enhanced mode like memory cell C 2 is.
- the selected bit line 320 is coupled to a certain voltage level
- the selected word line 302 is coupled to low level
- the unselected word lines 302 and the gate 340 of the bank select transistor 308 are coupled to high level.
- the bank select transistor 308 and all of the unselected memory cells in the same memory string 304 are switched on.
- the selected memory cell has a local interconnect 326 formed thereon, a current can be conducted through it and can be detected, otherwise no current is detected.
- the Metal ROM is more compact than the contact ROM, but the memory area in the Metal ROM cannot be further reduced because local interconnects must be formed on the diffusions 305 (sources and drains).
- this invention provides a contactless mask programmable ROM that has a smaller memory array for increasing device integration.
- a Mask ROM of this invention comprises a plurality of word lines extending in row direction and a plurality of MOS-type memory cells.
- a memory cell in one column shares its diffusions with two adjacent memory cells in the same column, and the two terminal memory cells in the same column are coupled to a first voltage source and a second voltage source, respectively.
- the first voltage source and the second voltage source are, for example, a bit line and ground, respectively.
- the memory cells include a plurality of first memory cells and a plurality of second memory cells.
- the first memory cells have a first channel length (word line width) and a first threshold voltage
- the second memory cells have a second channel length (word line width) that is smaller than the first one and is small enough to cause short channel effect.
- the second memory cells thus have a second threshold voltage substantially lower than the first threshold voltage.
- the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- the type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
- the first memory cells have a first channel dopant concentration to cause a first threshold voltage.
- the second memory cells have a second channel dopant concentration lower than the first one to cause a second threshold voltage substantially lower than the first threshold voltage.
- This can be done by performing a threshold voltage adjusting implantation to selected (first) memory cells with a patterned photoresist layer as a mask, which is formed with a photo-mask.
- the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- the first memory cells have a first gate dielectric thickness to cause a first threshold voltage.
- the second memory cells have a second gate dielectric thickness smaller than the first one to cause a second threshold voltage substantially lower than the first threshold voltage.
- the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- the data value stored in a memory cell corresponds to the channel length, the gate dielectric thickness or the channel dopant concentration thereof, and no contact is formed on the diffusion regions. Therefore, the Mask ROM of this invention is more compact than those in the prior art.
- FIG. 1 illustrates a top view of a contact ROM in the prior art
- FIG. 2 illustrates a top view of an implant programmable ROM in the prior art
- FIG. 3 illustrates a top view of a Metal ROM in the prior art
- FIG. 4A illustrates a contactless Mask ROM according to a first embodiment of this invention
- FIG. 4B illustrates the equivalent circuit of the contactless Mask ROM
- FIG. 5 plots the threshold voltage with respect to the channel length
- FIG. 6 illustrates a top view of a contactless Mask ROM according to a second or third embodiment of this invention
- FIG. 7 illustrates the contactless Mask ROM of the second embodiment in FIG. 6 in a cross-sectional view along line VII-VII′;
- FIG. 8 illustrates the contactless Mask ROM of the third embodiment in FIG. 6 in a cross-sectional view along line VII-VII′.
- FIG. 4A illustrates a contactless Mask ROM according to a first embodiment of this invention
- FIG. 4B illustrates the equivalent circuit of the contactless Mask ROM
- FIG. 5 plots the threshold voltage with respect to the channel length in order to explain this embodiment.
- the contactless Mask ROM 400 comprises a plurality of word lines 420 extending in row direction, and rows and columns of diffusions 440 in a substrate (not shown) like a P-type substrate.
- the word lines 420 comprise a material such as doped polysilicon, and the diffusions 440 contain N-type dopants, for example.
- two columns of diffusions 440 are separated by isolation 410 .
- Two rows of diffusions 440 are separated by a word line 420 , and the two terminal diffusions 440 in each column of diffusions 440 are coupled to a bit line (BL n ) and ground, respectively.
- two adjacent diffusions 440 in the same column, the word line 420 between the two diffusions 440 , and the substrate (not shown) between the two diffusions 440 together constitute a MOS-type memory cell C s /C n . Accordingly, two columns of memory cells C s /C n are separated by the isolation 410 .
- the word lines 420 over the memory cells C n are not narrowed, and the memory cells C n have a first channel length and a first threshold voltage.
- the word lines 420 over the memory cells C s are narrowed to create a second channel length small enough to cause short channel effect, so the memory cells C s have a second threshold voltage substantially lower than the first threshold voltage, as shown in FIG. 5.
- the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- the type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
- FIG. 6 illustrates a contactless Mask ROM according to the second embodiment of this invention
- FIG. 7 illustrates the contactless Mask ROM in a cross-sectional view along the line VII-VII′.
- the contactless Mask ROM 600 comprises a plurality of word lines 620 extending in row direction and rows and columns of diffusions 640 in a substrate 602 , wherein each word line 620 is isolated from the substrate 602 by a gate oxide layer 660 .
- the word lines 620 comprise a material such as doped polysilicon, and the diffusions 640 contain N-type dopants, for example.
- two columns of diffusions 640 are separated by isolation 610 .
- Two rows of diffusions 640 are separated by a word line 620 , and the two terminal diffusions 640 in each column of diffusions 640 are coupled to a bit line (BL n ) and ground, respectively.
- bit line BL n
- the memory cells C h have a raised channel dopant concentration, as indicated by the numeral 608 , to cause a first threshold voltage.
- the other memory cells have a lower channel dopant concentration, i.e., an original channel dopant concentration, to cause a second threshold voltage.
- the higher channel dopant concentration is made by, for example, conducting a threshold voltage adjusting implantation process, wherein a photo-mask is used to form a patterned photoresist layer exposing selected memory cells and an implantation is then performed to adjust the threshold voltages of the selected memory cells.
- the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- the type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
- FIG. 6 also illustrates a contactless Mask ROM according to the third embodiment of this invention
- FIG. 8 illustrates the contactless Mask ROM in a cross-sectional view along the line VII-VII′.
- the contactless Mask ROM 800 comprises a plurality of word lines 820 extending in row direction and rows and columns of diffusions 840 in a substrate 802 .
- the word lines 820 comprise a material such as doped polysilicon, and the diffusions 840 contain N-type dopants, for example.
- two columns of diffusions 840 are separated by isolation 810 .
- Two rows of diffusions 840 are separated by a word line 820 , and the two terminal diffusions 840 in each column of diffusions 840 are coupled to a bit line (BL n ) and ground, respectively.
- BL n bit line
- two adjacent diffusions 840 in the same column, the word line 820 between the two diffusions 840 , and the substrate 802 between the two diffusions 840 together constitute a MOS-type memory cell.
- the memory cells C h have a gate oxide layer 860 b with a first thickness to cause a first threshold voltage.
- the other memory cells have a gate oxide layer 860 a with a second thickness smaller than the first thickness to cause a second threshold voltage substantially lower than the first threshold voltage.
- the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- the type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
- the two gate oxide layers 860 a and 860 b can be formed with a method that has been used in a CMOS /Logic process supporting dual power supply product, e.g., a 3 v/5 v application.
- the substrate regions corresponding to the gate oxide layers 860 a are implanted with nitrogen ions before gate oxide formation, so as to inhibit the growth of the gate oxide layers 860 a .
- the substrate regions corresponding to the gate oxide layers 860 b are implanted with fluorine ions before gate oxide formation, so as to enhance the growth of the gate oxide layers 860 b.
- the Mask ROM in the second embodiment can be programmed by performing a selective threshold voltage adjusting implantation, while that in the third embodiment is programmed by adjusting the gate oxide thickness.
- the method using threshold voltage adjusting implantation and the method adjusting the gate oxide thickness both need an additional mask.
- the mask for forming a gate dielectric layer with different thickness is ready for a CMOS /Logic process that supports dual power supply product, e.g., a 3 v/5 v application, while the additional mask needed for adjusting the threshold voltage should be designed from the beginning.
- the reading operation of the mask ROM is described below.
- the selected word line WL 1 is coupled to low level and the unselected world lines are coupled to high level.
- the low level is between the lower (second) threshold voltage and the higher (first) threshold voltage
- the high level is higher than the first threshold voltages and therefore is capable of switching on the unselected memory cells in the same column.
- the memory cell C s corresponding to word line WL 1 and bit line BL 1 has the second (smaller) channel length and therefore has the second (lower) threshold voltage, it can be switched on by the low level voltage to allow a current from BL 1 to ground.
- the method for reading the contactless Mask ROM illustrated in FIG. 6 ⁇ 8 is similar to the aforementioned one, wherein the memory cells C h are taken as C n and the other cells are taken as C s .
- the value of the data stored in a memory cell corresponds to the channel length, the gate dielectric thickness or the channel dopant concentration, and no contact is formed on the diffusion regions. Therefore, the Mask ROM of this invention is more compact than those in the prior art.
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Abstract
Description
- 1. Field of Invention
- The present invention relates to a semiconductor device. More particularly, the present invention relates to a contactless mask programmable read-only memory (Mask ROM).
- 2. Description of Related Art
- Read-only memory (ROM) is a type of non-volatile memory, which can retain data as disconnected from power supply and is therefore used to store permanent data, such as booting data of computer systems.
- In order to simplify the fabricating processes and to increase the integration of ROM devices, various ROM structures are proposed based on shared diffusion and integration of the coding process and the contact process. Some conventional ROM devices are described below.
- FIG. 1 illustrates a top view of a contact ROM in the prior art.
- Refer to FIG. 1, the
contact ROM 100 comprises rows and columns of MOS-type memory cells, wherein two adjacent memory cells in the same column constitute acell pair 102 that is isolated byfield isolation 104. The memory cells in the same row are controlled by aword line 106, and the memory cells in the same column are located under abit line 108. The two memory cells in acell pair 102 share asource 110 between the twodrains 112 thereof, while thesources 110 of thecell pairs 102 in the same row are electrically connected to aground line 114. In thecontact ROM 100, a plurality ofcontacts 116 are selectively formed on thedrains 112 of the memory cells as data codes, wherein the contacts in the same column are connected to abit line 108. - During a reading operation of the contact ROM, the
selected word line 106 is biased to high level. If thedrain 112 of the selected memory cell has acontact 116 thereon electrically connecting with theselected bit line 108, a current can be conducted from theselected bit line 108 to theground line 114 connecting with thesource 110 of the selected memory cell. Otherwise, no current is detected. In other words, the data is stored as a contact pattern. However, since thefield isolation 104 is formed between two rows ofcell pairs 102 andcontacts 116 are formed on thedrains 112, the area of the memory array is large and the device integration is low. - FIG. 2 illustrates a top view of an implant programmable ROM in the prior art.
- Refer to FIG. 2, the implant
programmable ROM 200 comprises rows and columns of MOS-type memory cells 201. The memory cells in the same row are controlled by aword line 202 and every two rows ofmemory cells 201 are coupled to aground line 204, while two columns ofmemory cells 201 are separated byisolation 203. Amemory cell 201 shares asource 206 with one adjacent memory cell in the same column, and shares adrain 208 with the other adjacent memory cell in the same column. Thesources 206 of thememory cells 201 in the same row are connected to aground line 204, and thedrains 208 of thememory cells 201 in the same column are electrically connected to abit line 210 viacontacts 212. The implantprogrammable ROM 200 is programmed by selectively implanting ions into the channel regions under theword lines 202 to make theselected channel regions 214 have a higher threshold voltage (VT). During the reading operation of the implant programmable ROM, theselected word line 202 is biased to high level. If the channel region of theselected memory cell 201 is not implanted, the channel can be switched on and an On-current can be detected, otherwise the channel cannot be switched on and the channel current is extremely small. - As compared with the
contact ROM 100 in FIG. 1, the implantprogrammable ROM 200 is more compact because the isolation between rows of memory cells is omitted and adrain 208 is shared by twomemory cells 201 like asource 206. However, since an additional mask is needed for selectively implanting the channel regions of thememory cells 201, the fabricating process is more complex. Moreover, in consideration of the lateral area necessary for forming thecontacts 212, the degree of area reduction of thedrain region 208 is limited and the memory array cannot be further miniaturized. - FIG. 3 illustrates a top view of a Metal ROM in the prior art.
- Refer to FIG. 3, the
Metal ROM 300 has a NAND (NOT AND) structure and comprises rows and columns of MOS-type memory cells. The memory cells in the same row are controlled by aword line 302 and four continuous memory cells in the same column are grouped as amemory string 304. In amemory string 304, thediffusion 305 of one terminal memory cell is electrically connected to aground line 306, and thediffusion 305 of the other terminal memory cell is coupled to a bankselect transistor 308. Thebank select transistor 308 is coupled to abit line 320 parallel to thememory string 304 via acontact 322. The source and the drain of a memory cell, i.e., the twodiffusions 305 of a memory cell, are both shared by adjacent cells. - The Metal ROM is programmed by selectively forming
local interconnects 326 each connecting the twodiffusions 305 of a selected memory cell. If a memory cell has alocal interconnect 326 formed thereon like memory cell C1 does, the memory cell is always electrically conductible and acts like a depletion-type MOS devices, otherwise the memory cell is in the enhanced mode like memory cell C2 is. During a reading operation, theselected bit line 320 is coupled to a certain voltage level, theselected word line 302 is coupled to low level, and theunselected word lines 302 and thegate 340 of the bankselect transistor 308 are coupled to high level. Thus, the bank selecttransistor 308 and all of the unselected memory cells in thesame memory string 304 are switched on. Consequently, if the selected memory cell has alocal interconnect 326 formed thereon, a current can be conducted through it and can be detected, otherwise no current is detected. The Metal ROM is more compact than the contact ROM, but the memory area in the Metal ROM cannot be further reduced because local interconnects must be formed on the diffusions 305 (sources and drains). - Accordingly, this invention provides a contactless mask programmable ROM that has a smaller memory array for increasing device integration.
- A Mask ROM of this invention comprises a plurality of word lines extending in row direction and a plurality of MOS-type memory cells. A memory cell in one column shares its diffusions with two adjacent memory cells in the same column, and the two terminal memory cells in the same column are coupled to a first voltage source and a second voltage source, respectively. The first voltage source and the second voltage source are, for example, a bit line and ground, respectively. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel length (word line width) and a first threshold voltage, and the second memory cells have a second channel length (word line width) that is smaller than the first one and is small enough to cause short channel effect. The second memory cells thus have a second threshold voltage substantially lower than the first threshold voltage. In addition, the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
- In another Mask ROM of this invention, the first memory cells have a first channel dopant concentration to cause a first threshold voltage. The second memory cells have a second channel dopant concentration lower than the first one to cause a second threshold voltage substantially lower than the first threshold voltage. This can be done by performing a threshold voltage adjusting implantation to selected (first) memory cells with a patterned photoresist layer as a mask, which is formed with a photo-mask. In addition, the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- In still another Mask ROM of this invention, the first memory cells have a first gate dielectric thickness to cause a first threshold voltage. The second memory cells have a second gate dielectric thickness smaller than the first one to cause a second threshold voltage substantially lower than the first threshold voltage. The difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.
- As mentioned above, in the contactless Mask ROM of this invention, the data value stored in a memory cell corresponds to the channel length, the gate dielectric thickness or the channel dopant concentration thereof, and no contact is formed on the diffusion regions. Therefore, the Mask ROM of this invention is more compact than those in the prior art.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
- FIG. 1 illustrates a top view of a contact ROM in the prior art;
- FIG. 2 illustrates a top view of an implant programmable ROM in the prior art;
- FIG. 3 illustrates a top view of a Metal ROM in the prior art;
- FIG. 4A illustrates a contactless Mask ROM according to a first embodiment of this invention, and FIG. 4B illustrates the equivalent circuit of the contactless Mask ROM;
- FIG. 5 plots the threshold voltage with respect to the channel length;
- FIG. 6 illustrates a top view of a contactless Mask ROM according to a second or third embodiment of this invention;
- FIG. 7 illustrates the contactless Mask ROM of the second embodiment in FIG. 6 in a cross-sectional view along line VII-VII′; and
- FIG. 8 illustrates the contactless Mask ROM of the third embodiment in FIG. 6 in a cross-sectional view along line VII-VII′.
- First Embodiment
- FIG. 4A illustrates a contactless Mask ROM according to a first embodiment of this invention, and FIG. 4B illustrates the equivalent circuit of the contactless Mask ROM. Meanwhile, FIG. 5 plots the threshold voltage with respect to the channel length in order to explain this embodiment.
- Refer to FIGS. 4A and 4B, the
contactless Mask ROM 400 comprises a plurality ofword lines 420 extending in row direction, and rows and columns ofdiffusions 440 in a substrate (not shown) like a P-type substrate. The word lines 420 comprise a material such as doped polysilicon, and thediffusions 440 contain N-type dopants, for example. In thecontactless Mask ROM 400, two columns ofdiffusions 440 are separated byisolation 410. Two rows ofdiffusions 440 are separated by aword line 420, and the twoterminal diffusions 440 in each column ofdiffusions 440 are coupled to a bit line (BLn) and ground, respectively. In addition, twoadjacent diffusions 440 in the same column, theword line 420 between the twodiffusions 440, and the substrate (not shown) between the twodiffusions 440 together constitute a MOS-type memory cell Cs/Cn. Accordingly, two columns of memory cells Cs/Cn are separated by theisolation 410. - The word lines420 over the memory cells Cn are not narrowed, and the memory cells Cn have a first channel length and a first threshold voltage. The word lines 420 over the memory cells Cs are narrowed to create a second channel length small enough to cause short channel effect, so the memory cells Cs have a second threshold voltage substantially lower than the first threshold voltage, as shown in FIG. 5. The difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
- Second Embodiment
- FIG. 6 illustrates a contactless Mask ROM according to the second embodiment of this invention, and FIG. 7 illustrates the contactless Mask ROM in a cross-sectional view along the line VII-VII′.
- Refer to FIGS. 6 and 7, the
contactless Mask ROM 600 comprises a plurality ofword lines 620 extending in row direction and rows and columns ofdiffusions 640 in asubstrate 602, wherein eachword line 620 is isolated from thesubstrate 602 by agate oxide layer 660. The word lines 620 comprise a material such as doped polysilicon, and thediffusions 640 contain N-type dopants, for example. In thecontactless Mask ROM 600, two columns ofdiffusions 640 are separated byisolation 610. Two rows ofdiffusions 640 are separated by aword line 620, and the twoterminal diffusions 640 in each column ofdiffusions 640 are coupled to a bit line (BLn) and ground, respectively. In addition, twoadjacent diffusions 640 in the same column, theword line 620 between the twodiffusions 640, and thesubstrate 602 between the twodiffusions 640 together constitute a MOS-type memory cell. - Refer to FIGS. 6 and 7 again, the memory cells Ch have a raised channel dopant concentration, as indicated by the numeral 608, to cause a first threshold voltage. The other memory cells have a lower channel dopant concentration, i.e., an original channel dopant concentration, to cause a second threshold voltage. The higher channel dopant concentration is made by, for example, conducting a threshold voltage adjusting implantation process, wherein a photo-mask is used to form a patterned photoresist layer exposing selected memory cells and an implantation is then performed to adjust the threshold voltages of the selected memory cells. In addition, the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
- Third Embodiment
- FIG. 6 also illustrates a contactless Mask ROM according to the third embodiment of this invention, and FIG. 8 illustrates the contactless Mask ROM in a cross-sectional view along the line VII-VII′.
- Refer to FIGS. 6 and 8, the
contactless Mask ROM 800 comprises a plurality ofword lines 820 extending in row direction and rows and columns ofdiffusions 840 in asubstrate 802. The word lines 820 comprise a material such as doped polysilicon, and thediffusions 840 contain N-type dopants, for example. In thecontactless Mask ROM 800, two columns ofdiffusions 840 are separated byisolation 810. Two rows ofdiffusions 840 are separated by aword line 820, and the twoterminal diffusions 840 in each column ofdiffusions 840 are coupled to a bit line (BLn) and ground, respectively. In addition, twoadjacent diffusions 840 in the same column, theword line 820 between the twodiffusions 840, and thesubstrate 802 between the twodiffusions 840 together constitute a MOS-type memory cell. - Refer to FIG. 8, the memory cells Ch have a
gate oxide layer 860 b with a first thickness to cause a first threshold voltage. The other memory cells have agate oxide layer 860 a with a second thickness smaller than the first thickness to cause a second threshold voltage substantially lower than the first threshold voltage. The difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it. - Moreover, the two gate oxide layers860 a and 860 b can be formed with a method that has been used in a CMOS /Logic process supporting dual power supply product, e.g., a 3 v/5 v application. For example, the substrate regions corresponding to the gate oxide layers 860 a are implanted with nitrogen ions before gate oxide formation, so as to inhibit the growth of the gate oxide layers 860 a. On the other hand, the substrate regions corresponding to the gate oxide layers 860 b are implanted with fluorine ions before gate oxide formation, so as to enhance the growth of the gate oxide layers 860 b.
- As mentioned above, the Mask ROM in the second embodiment can be programmed by performing a selective threshold voltage adjusting implantation, while that in the third embodiment is programmed by adjusting the gate oxide thickness. The method using threshold voltage adjusting implantation and the method adjusting the gate oxide thickness both need an additional mask. However, the mask for forming a gate dielectric layer with different thickness is ready for a CMOS /Logic process that supports dual power supply product, e.g., a 3 v/5 v application, while the additional mask needed for adjusting the threshold voltage should be designed from the beginning.
- Reading Operation of the Mask ROM:
- The reading operation of the mask ROM according to the preferred embodiment of this invention is described below. Refer to FIG. 4B, for example, when the memory cell Cs corresponding to word line WL1 and bit line BL1 is being read, the selected word line WL1 is coupled to low level and the unselected world lines are coupled to high level. The low level is between the lower (second) threshold voltage and the higher (first) threshold voltage, and the high level is higher than the first threshold voltages and therefore is capable of switching on the unselected memory cells in the same column. Since the memory cell Cs corresponding to word line WL1 and bit line BL1 has the second (smaller) channel length and therefore has the second (lower) threshold voltage, it can be switched on by the low level voltage to allow a current from BL1 to ground.
- On the other hand, when the memory cell Cn corresponding to word line WL2 and bit line BL1 is being read, WL2 is coupled to low level, and the unselected world lines are coupled to high level to switch on the unselected memory cells in the same column. Since the memory cell Cn has the first (larger) channel length and therefore has the first (higher) threshold voltage, it cannot be switched on by the low-level voltage. Consequently, the current from BL1 to ground is extremely small. Therefore, by detecting the magnitude of the current from BL1 to ground, the type of the selected memory cell and the corresponding data value (0 or 1) can be determined.
- Moreover, the method for reading the contactless Mask ROM illustrated in FIG. 6˜8 is similar to the aforementioned one, wherein the memory cells Ch are taken as Cn and the other cells are taken as Cs.
- As mentioned above, in the contactless Mask ROM of this invention, the value of the data stored in a memory cell corresponds to the channel length, the gate dielectric thickness or the channel dopant concentration, and no contact is formed on the diffusion regions. Therefore, the Mask ROM of this invention is more compact than those in the prior art.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (20)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/IB2002/003451 WO2004019408A1 (en) | 2002-08-26 | 2002-08-26 | Contactless mask programmable rom |
Publications (1)
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US20040241926A1 true US20040241926A1 (en) | 2004-12-02 |
Family
ID=31898436
Family Applications (2)
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US10/477,880 Abandoned US20040241926A1 (en) | 2002-08-26 | 2002-08-26 | Contactless mask progammable rom |
US10/509,908 Expired - Lifetime US7227232B2 (en) | 2002-08-26 | 2003-04-28 | Contactless mask programmable ROM |
Family Applications After (1)
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US10/509,908 Expired - Lifetime US7227232B2 (en) | 2002-08-26 | 2003-04-28 | Contactless mask programmable ROM |
Country Status (3)
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US (2) | US20040241926A1 (en) |
AU (2) | AU2002328180A1 (en) |
WO (2) | WO2004019408A1 (en) |
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US20060281262A1 (en) * | 2005-05-23 | 2006-12-14 | Digh Hisamoto | Integrated semiconductor nonvolatile storage device |
US10008280B1 (en) * | 2015-03-13 | 2018-06-26 | Skan Technologies Corporation | PPA (power performance area) efficient architecture for ROM (read only memory) and a ROM bitcell without a transistor |
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KR100632953B1 (en) * | 2005-03-07 | 2006-10-12 | 삼성전자주식회사 | Memory device, memory array architecture for the memory device and operation of the memory array architecture |
US7982252B2 (en) * | 2006-01-27 | 2011-07-19 | Hynix Semiconductor Inc. | Dual-gate non-volatile ferroelectric memory |
KR100876082B1 (en) * | 2006-12-07 | 2008-12-26 | 삼성전자주식회사 | Memory device and forming method thereof |
TWI349363B (en) * | 2007-11-15 | 2011-09-21 | Nanya Technology Corp | Non-volatile memory and the manufacturing method thereof |
US7824988B2 (en) | 2009-01-21 | 2010-11-02 | Freescale Semiconductor, Inc. | Method of forming an integrated circuit |
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Also Published As
Publication number | Publication date |
---|---|
WO2004019372A3 (en) | 2004-06-03 |
US20050127454A1 (en) | 2005-06-16 |
AU2002328180A1 (en) | 2004-03-11 |
WO2004019408A1 (en) | 2004-03-04 |
AU2003226597A8 (en) | 2004-03-11 |
US7227232B2 (en) | 2007-06-05 |
WO2004019372A2 (en) | 2004-03-04 |
AU2003226597A1 (en) | 2004-03-11 |
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