US20040239412A1 - Circuit for controlling field effect device transconductance - Google Patents
Circuit for controlling field effect device transconductance Download PDFInfo
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- US20040239412A1 US20040239412A1 US10/452,089 US45208903A US2004239412A1 US 20040239412 A1 US20040239412 A1 US 20040239412A1 US 45208903 A US45208903 A US 45208903A US 2004239412 A1 US2004239412 A1 US 2004239412A1
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- transconductance
- field effect
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- control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
- H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/34—Dc amplifiers in which all stages are dc-coupled
- H03F3/343—Dc amplifiers in which all stages are dc-coupled with semiconductor devices only
- H03F3/345—Dc amplifiers in which all stages are dc-coupled with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
- H03B2200/003—Circuit elements of oscillators
- H03B2200/0058—Circuit elements of oscillators with particular transconductance characteristics, e.g. an operational transconductance amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/78—A comparator being used in a controlling circuit of an amplifier
Definitions
- the present invention relates generally to the field of electronic circuits, and more particularly to electronic circuits which include one or more metal-oxide-semiconductor (MOS) devices or other types of field effect devices.
- MOS metal-oxide-semiconductor
- One such conventional technique involves configuring the circuit so as to maintain the difference between the gate-to-source voltage V GS and the threshold voltage V T of the MOS device substantially equal to the voltage drop across a designated precision resistor. It is generally desirable, however, for the MOS device transconductance control to be implemented in a manner which is substantially independent of the threshold voltage V T .
- the circuit is configured such that relative changes in the gate-to-source voltage V GS of the MOS device and the voltage across the precision resistor track one another. This is achieved, for example, by adjusting the amount of the current flowing through the MOS device.
- the present invention provides a transconductance control circuit which in an illustrative embodiment is configured to control the transconductance of at least one MOS device such that it tracks the conductance of a resistor in the presence of circuit variations attributable to factors such as process, temperature or voltage.
- a transconductance control circuit includes a master device having first and second field effect devices coupled to respective first and second current sources, a reference device coupled to a third current source, and comparison circuitry.
- the comparison circuitry includes at least first, second and third inputs and at least one output, with the first input configured to receive a reference signal associated with the reference device, the second and third inputs coupled to respective terminals of the first and second field effect devices, and the output coupled to current control inputs of one or more of the current sources.
- the transconductance control circuit provides a feedback control arrangement in which the comparison circuitry output is utilized to adjust one or more of the current sources such that a difference signal V g between voltages at the respective terminals of the first and second field effect devices converges to a reference signal V R .
- V g difference signal between voltages at the respective terminals of the first and second field effect devices
- V R reference signal
- the transconductance g m of the first device converges to the conductance of the reference device.
- a transconductance control circuit in accordance with the invention may be implemented, for example, as a portion of an integrated circuit.
- the transconductance control circuit may be implemented as a component of an amplifier, buffer, oscillator or other type of electronic circuit which is itself implemented as a portion of an integrated circuit.
- the present invention provides a particularly efficient mechanism for controlling the transconductance of a MOS device or other field effect device in the presence of process, temperature or voltage variations, or other types of variations.
- the transconductance control circuit in the above-noted illustrative embodiment provides significantly improved precision and flexibility relative to the conventional techniques previously described, in that the MOS transconductance g m is implemented so as to converge to the reciprocal of the resistor value R. Moreover, this transconductance control circuit does not require that any assumptions be made regarding relative resistance and transconductance values, nor does it require different size transistors.
- FIG. 1 is a schematic diagram of an N-type MOS (NMOS) implementation of an example current mode circuit for maintaining MOS device transconductance in accordance with an illustrative embodiment of the invention.
- NMOS N-type MOS
- FIG. 2 is a schematic diagram showing a P-type (PMOS) implementation of the example current mode circuit of FIG. 1.
- the present invention will be illustrated below in conjunction with exemplary embodiments of transconductance control circuits in which MOS device transconductance is controlled so as to track the conductance of a resistor. It should be understood, however, that the invention is not limited to use with the particular circuitry arrangements of the illustrative embodiments, and other embodiments may include, for example, different types and arrangements of controlled devices, reference devices, control circuitry, etc. For example, although illustrated in the context of MOS device transconductance control, the invention is more generally applicable to transconductance control for any type of field effect transistor (FET) or other field effect device.
- FET field effect transistor
- FIG. 1 shows a transconductance control circuit 100 configured in accordance with an illustrative embodiment of the invention.
- This embodiment is an example of an N-type MOS (NMOS) implementation of the invention, and includes NMOS devices M 1 , M 2 and M 3 as shown.
- the circuit 100 further includes comparison circuitry 102 and current sources 110 , 112 , 114 , 116 and 118 arranged as shown.
- the devices M 1 and M 2 collectively comprise an example of what is referred to herein as a master NMOS device, while the device M 3 is an example of an associated slave NMOS device.
- a given master device may include more than two MOS devices or a single MOS device, or a slave device may include two or more MOS devices, in alternative embodiments.
- the devices M 1 and M 2 of the master NMOS device are coupled to the current sources 112 and 114 , respectively.
- Each of the devices M 1 and M 2 has a gate terminal, a source terminal and a drain terminal, with the gate terminal coupled to the drain terminal, the source terminal coupled to a ground potential of the circuit 100 , and the associated current source 112 or 114 coupled between the drain terminal and an upper voltage potential associated with a VDD supply line 120 of the circuit 100 .
- Ground potential in this embodiment represents an example of a lower voltage potential of the circuit 100 , although other embodiments may use other types of lower voltage potentials, including a negative voltage supply.
- the device M 3 of the slave NMOS device is coupled to the current source 118 .
- the device M 3 has a gate terminal, a source terminal and a drain terminal, with the gate terminal coupled to the drain terminal, the source terminal coupled to ground potential of the circuit 100 , and the current source 118 coupled between the drain terminal and the upper voltage potential of the circuit 100 .
- the devices M 1 , M 2 and M 3 have substantially the same channel width W and substantially the same channel length L in this embodiment.
- the devices M 1 and M 3 each have a transconductance denoted herein as g m
- the device M 2 has a transconductance denoted herein as g m ′.
- the circuit 100 also includes a reference device which in this embodiment comprises a resistor R.
- a resistor as used herein is intended to include a single-element precision resistor or any other type of resistor, including a transistor or other type of circuitry which is configured to operate as a resistor.
- the notation R is also used herein to refer to the particular resistance value associated with the resistor. The conductance of the resistor is therefore given by 1/R.
- the resistor R is coupled to the current source 110 . More specifically, the resistor R and the current source 110 are connected in series between the upper voltage potential of the circuit 100 and ground potential of the circuit 100 .
- the current source 116 is coupled between the upper voltage potential of the circuit 100 and a point in the circuit 100 between the device M 2 and the current source 114 .
- Each of the current sources 112 and 114 has a current I associated therewith.
- the current source 118 is configured to mirror the current I associated with the current sources 112 and 114 .
- the current source 116 has a current al associated therewith, where a is a selectable operating parameter of the circuit 100 , to be described in greater detail below.
- the current associated with the current source 110 is also a function of the parameter a, and in this embodiment is given by: I ⁇ ( ⁇ ( ⁇ + 2 ) ) .
- Each of the current sources 110 also includes a current control input which is driven via signal line 122 by an output of the comparison circuitry 102 .
- the comparison circuitry 102 in this embodiment comprises a multi-input comparator having at least first, second and third inputs and at least one output, although it is to be appreciated that the invention does not require this particular arrangement of comparison circuitry.
- a first non-inverting input of the comparator is configured to receive a reference signal associated with the resistor R.
- the reference signal in this embodiment more specifically comprises a voltage V R across the resistor R.
- Second and third inputs of the comparator are coupled to respective terminals of the devices M 1 and M 2 . More specifically, a second non-inverting input of the comparator is coupled to a gate terminal of the device M 2 , and an inverting input of the comparator is coupled to a gate terminal of the device M 1 . As indicated previously, the gate terminals of the devices M 1 and M 2 are coupled to their respective drain terminals. The voltage difference between the gate terminals M 2 and M 1 is denoted in the figure as V g .
- the output of the comparator is coupled via line 122 to current control inputs of each of the current sources 110 , 112 , 114 , 116 and 118 .
- the comparison circuitry output may drive only a subset of the current source control inputs.
- the transconductance control circuit 100 controls the transconductance g m such that it tracks a conductance of the resistor R, thereby maintaining desired levels for dimensionless parameters such as gain in the presence of variations attributable to process, temperature, voltage, etc.
- the circuit 100 is configured to compare the transconductance g m of device M 1 with the value of the resistor R, and to provide the necessary current adjustments such that g m is substantially equal to the resistor conductance 1/R.
- the value of ⁇ utilized in circuit 100 is typically selected such that ⁇ 1. This can be easily achieved by configuring the current sources 112 , 114 and 116 such that the transconductance values g m and g m ′ of the respective devices M 1 and M 2 are close to one another.
- suitable values for a may be on the order of about 0.05 to 0.10.
- Other values of ⁇ can be used in alternative embodiments.
- the transconductance control circuit 100 configured in the manner shown in FIG. 1 provides a feedback control arrangement which adjusts the current sources such that V g will converge to V R , and therefore g m will converge to the conductance 1/R of the resistor R. As indicated previously, the current I is mirrored and controls the slave device M 3 .
- FIG. 2 shows a transconductance control circuit 200 representing a P-type MOS (PMOS) implementation of the FIG. 1 embodiment.
- the circuit 200 includes a master PMOS device comprising PMOS devices M 4 and M 5 , a slave PMOS device comprising PMOS device M 6 , comparison circuitry 202 , current sources 210 , 212 , 214 , 216 and 218 , and reference device comprising resistor R.
- FIG. 2 PMOS implementation is analogous to that of the NMOS implementation previously described in conjunction with FIG. 1, as will be appreciated by those skilled in the art.
- the transconductance control circuits of the illustrative embodiments of the invention each provide significantly improved precision and flexibility relative to the conventional techniques previously described.
- the illustrative embodiments implement the MOS transconductance value g m such that it converges to the reciprocal of the resistor value R.
- these circuits do not require that any assumptions be made regarding relative resistance and transconductance values, nor do they require different size transistors.
- the transconductance control circuits of FIGS. 1 and 2 may each be implemented, by way of example, as a component of an integrated circuit, and a given integrated circuit may include a plurality of such transconductance control circuits.
- the transconductance control circuit may be implemented as a component of an amplifier, buffer, oscillator or other type of electronic circuit which is itself implemented as a portion of an integrated circuit.
- circuit parameters such as channel widths W, channel lengths L, and resistance R will generally depend on factors such as the particular process and other variations that are present in a given implementation, and can be readily determined in a straightforward manner given the teachings contained herein.
- FIGS. 1 and 2 are intended to illustrate the operation of the invention, and therefore should not be construed as limiting the invention to any particular embodiment or group of embodiments.
- the particular circuitry shown herein for purposes of illustrating the invention may be implemented in many different ways, and may include additional or alternative elements.
- the transconductance of one or more MOS devices may be made to track a parameter of a reference device comprising another circuit element or set of circuit elements, rather than to track the conductance of a resistor as in the illustrative embodiments.
Abstract
Description
- The present invention relates generally to the field of electronic circuits, and more particularly to electronic circuits which include one or more metal-oxide-semiconductor (MOS) devices or other types of field effect devices.
- It is important in many electronic circuit applications to provide a mechanism for controlling the transconductance of one or more field effect devices. For example, in amplifiers, buffers, oscillators and other similar circuits, failure to provide proper control of the transconductance of certain MOS devices within the circuits can allow undesirable variations in one or more dimensionless parameters, such as gain, in the presence of variations attributable to factors such as process, temperature, voltage, etc.
- Conventional techniques have been unable to provide an adequate solution to the problem of controlling MOS device transconductance, as will be described below.
- One such conventional technique involves configuring the circuit so as to maintain the difference between the gate-to-source voltage VGS and the threshold voltage VT of the MOS device substantially equal to the voltage drop across a designated precision resistor. It is generally desirable, however, for the MOS device transconductance control to be implemented in a manner which is substantially independent of the threshold voltage VT.
- The issue of independence of VT is addressed in another conventional technique. In accordance with this technique, the circuit is configured such that relative changes in the gate-to-source voltage VGS of the MOS device and the voltage across the precision resistor track one another. This is achieved, for example, by adjusting the amount of the current flowing through the MOS device.
- Nonetheless, these and other conventional techniques still suffer from a number of significant drawbacks. For example, the conventional techniques fail to implement the MOS transconductance value gm as the reciprocal of the precision resistor value R. In addition, certain conventional techniques require that particular assumptions be made regarding the relative values of R and gm, such as an assumption that R is much less than 1/gm. Such assumptions are undesirable in that they can unduly limit the level of achievable precision, while also reducing circuit configuration flexibility. Furthermore, certain conventional techniques may require different transistor sizes in order to implement the MOS transconductance control, which further limits achievable precision and configuration flexibility.
- As is apparent from the foregoing, a need exists for improved techniques for controlling the transconductance of a MOS device or other field effect device, which address one or more of the drawbacks of the conventional techniques described above.
- The present invention provides a transconductance control circuit which in an illustrative embodiment is configured to control the transconductance of at least one MOS device such that it tracks the conductance of a resistor in the presence of circuit variations attributable to factors such as process, temperature or voltage.
- In accordance with one aspect of the invention, a transconductance control circuit includes a master device having first and second field effect devices coupled to respective first and second current sources, a reference device coupled to a third current source, and comparison circuitry. The comparison circuitry includes at least first, second and third inputs and at least one output, with the first input configured to receive a reference signal associated with the reference device, the second and third inputs coupled to respective terminals of the first and second field effect devices, and the output coupled to current control inputs of one or more of the current sources.
- In an illustrative embodiment, the transconductance control circuit provides a feedback control arrangement in which the comparison circuitry output is utilized to adjust one or more of the current sources such that a difference signal Vg between voltages at the respective terminals of the first and second field effect devices converges to a reference signal VR. As a result, the transconductance gm of the first device converges to the conductance of the reference device.
-
- where αis selected such that α<<1.
- A transconductance control circuit in accordance with the invention may be implemented, for example, as a portion of an integrated circuit. As a more particular example, the transconductance control circuit may be implemented as a component of an amplifier, buffer, oscillator or other type of electronic circuit which is itself implemented as a portion of an integrated circuit.
- Advantageously, the present invention provides a particularly efficient mechanism for controlling the transconductance of a MOS device or other field effect device in the presence of process, temperature or voltage variations, or other types of variations.
- The transconductance control circuit in the above-noted illustrative embodiment provides significantly improved precision and flexibility relative to the conventional techniques previously described, in that the MOS transconductance gm is implemented so as to converge to the reciprocal of the resistor value R. Moreover, this transconductance control circuit does not require that any assumptions be made regarding relative resistance and transconductance values, nor does it require different size transistors.
- FIG. 1 is a schematic diagram of an N-type MOS (NMOS) implementation of an example current mode circuit for maintaining MOS device transconductance in accordance with an illustrative embodiment of the invention.
- FIG. 2 is a schematic diagram showing a P-type (PMOS) implementation of the example current mode circuit of FIG. 1.
- The present invention will be illustrated below in conjunction with exemplary embodiments of transconductance control circuits in which MOS device transconductance is controlled so as to track the conductance of a resistor. It should be understood, however, that the invention is not limited to use with the particular circuitry arrangements of the illustrative embodiments, and other embodiments may include, for example, different types and arrangements of controlled devices, reference devices, control circuitry, etc. For example, although illustrated in the context of MOS device transconductance control, the invention is more generally applicable to transconductance control for any type of field effect transistor (FET) or other field effect device.
- FIG. 1 shows a
transconductance control circuit 100 configured in accordance with an illustrative embodiment of the invention. This embodiment is an example of an N-type MOS (NMOS) implementation of the invention, and includes NMOS devices M1, M2 and M3 as shown. Thecircuit 100 further includescomparison circuitry 102 andcurrent sources - The devices M1 and M2 collectively comprise an example of what is referred to herein as a master NMOS device, while the device M3 is an example of an associated slave NMOS device. Other arrangements of devices are possible. For example, a given master device may include more than two MOS devices or a single MOS device, or a slave device may include two or more MOS devices, in alternative embodiments.
- The devices M1 and M2 of the master NMOS device are coupled to the
current sources circuit 100, and the associatedcurrent source VDD supply line 120 of thecircuit 100. Ground potential in this embodiment represents an example of a lower voltage potential of thecircuit 100, although other embodiments may use other types of lower voltage potentials, including a negative voltage supply. - The device M3 of the slave NMOS device is coupled to the
current source 118. The device M3 has a gate terminal, a source terminal and a drain terminal, with the gate terminal coupled to the drain terminal, the source terminal coupled to ground potential of thecircuit 100, and thecurrent source 118 coupled between the drain terminal and the upper voltage potential of thecircuit 100. - The devices M1, M2 and M3 have substantially the same channel width W and substantially the same channel length L in this embodiment.
- The devices M1 and M3 each have a transconductance denoted herein as gm, and the device M2 has a transconductance denoted herein as gm′.
- The
circuit 100 also includes a reference device which in this embodiment comprises a resistor R. The term “resistor” as used herein is intended to include a single-element precision resistor or any other type of resistor, including a transistor or other type of circuitry which is configured to operate as a resistor. The notation R is also used herein to refer to the particular resistance value associated with the resistor. The conductance of the resistor is therefore given by 1/R. - The resistor R is coupled to the
current source 110. More specifically, the resistor R and thecurrent source 110 are connected in series between the upper voltage potential of thecircuit 100 and ground potential of thecircuit 100. - The
current source 116 is coupled between the upper voltage potential of thecircuit 100 and a point in thecircuit 100 between the device M2 and thecurrent source 114. - Each of the
current sources current source 118 is configured to mirror the current I associated with thecurrent sources - The
current source 116 has a current al associated therewith, where a is a selectable operating parameter of thecircuit 100, to be described in greater detail below. -
- Each of the
current sources 110 also includes a current control input which is driven viasignal line 122 by an output of thecomparison circuitry 102. - Current mirroring, current control and other conventional techniques associated with the operation of the
current sources - The
comparison circuitry 102 in this embodiment comprises a multi-input comparator having at least first, second and third inputs and at least one output, although it is to be appreciated that the invention does not require this particular arrangement of comparison circuitry. - A first non-inverting input of the comparator is configured to receive a reference signal associated with the resistor R. The reference signal in this embodiment more specifically comprises a voltage VR across the resistor R.
- Second and third inputs of the comparator are coupled to respective terminals of the devices M1 and M2. More specifically, a second non-inverting input of the comparator is coupled to a gate terminal of the device M2, and an inverting input of the comparator is coupled to a gate terminal of the device M1. As indicated previously, the gate terminals of the devices M1 and M2 are coupled to their respective drain terminals. The voltage difference between the gate terminals M2 and M1 is denoted in the figure as Vg.
- As mentioned above, the output of the comparator is coupled via
line 122 to current control inputs of each of thecurrent sources - In operation, the
transconductance control circuit 100 as described above controls the transconductance gm such that it tracks a conductance of the resistor R, thereby maintaining desired levels for dimensionless parameters such as gain in the presence of variations attributable to process, temperature, voltage, etc. - More specifically, the
circuit 100 is configured to compare the transconductance gm of device M1 with the value of the resistor R, and to provide the necessary current adjustments such that gm is substantially equal to theresistor conductance 1/R. - The value of α utilized in
circuit 100 is typically selected such that α<<1. This can be easily achieved by configuring thecurrent sources -
-
- The
transconductance control circuit 100 configured in the manner shown in FIG. 1 provides a feedback control arrangement which adjusts the current sources such that Vg will converge to VR, and therefore gm will converge to theconductance 1/R of the resistor R. As indicated previously, the current I is mirrored and controls the slave device M3. - FIG. 2 shows a
transconductance control circuit 200 representing a P-type MOS (PMOS) implementation of the FIG. 1 embodiment. Thecircuit 200 includes a master PMOS device comprising PMOS devices M4 and M5, a slave PMOS device comprising PMOS device M6,comparison circuitry 202,current sources - The operation of the FIG. 2 PMOS implementation is analogous to that of the NMOS implementation previously described in conjunction with FIG. 1, as will be appreciated by those skilled in the art.
- Advantageously, the transconductance control circuits of the illustrative embodiments of the invention each provide significantly improved precision and flexibility relative to the conventional techniques previously described. The illustrative embodiments implement the MOS transconductance value gm such that it converges to the reciprocal of the resistor value R. Moreover, these circuits do not require that any assumptions be made regarding relative resistance and transconductance values, nor do they require different size transistors.
- The transconductance control circuits of FIGS. 1 and 2 may each be implemented, by way of example, as a component of an integrated circuit, and a given integrated circuit may include a plurality of such transconductance control circuits. As a more particular example, the transconductance control circuit may be implemented as a component of an amplifier, buffer, oscillator or other type of electronic circuit which is itself implemented as a portion of an integrated circuit.
- Suitable values for circuit parameters such as channel widths W, channel lengths L, and resistance R will generally depend on factors such as the particular process and other variations that are present in a given implementation, and can be readily determined in a straightforward manner given the teachings contained herein.
- It should again be emphasized that the exemplary transconductance control circuits described in conjunction with FIGS. 1 and 2 are intended to illustrate the operation of the invention, and therefore should not be construed as limiting the invention to any particular embodiment or group of embodiments. Furthermore, it will be apparent to those skilled in the art that the particular circuitry shown herein for purposes of illustrating the invention may be implemented in many different ways, and may include additional or alternative elements. For example, other types and arrangements of field effect devices, current sources, and comparison circuitry can be used. Also, the transconductance of one or more MOS devices may be made to track a parameter of a reference device comprising another circuit element or set of circuit elements, rather than to track the conductance of a resistor as in the illustrative embodiments.
- These and numerous other alternative embodiments within the scope of the following claims will therefore be apparent to those skilled in the art.
Claims (20)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104485891A (en) * | 2014-11-18 | 2015-04-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | Low-temperature-drift CMOS (complementary metal oxide semiconductor) oscillator circuit |
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US6166592A (en) * | 1998-07-31 | 2000-12-26 | Lucent Technologies Inc. | Linear CMOS transconductor with rail-to-rail compliance |
US6292034B1 (en) * | 2000-02-24 | 2001-09-18 | Motorola Inc. | Low noise transconductance device |
US6313684B1 (en) * | 1998-12-17 | 2001-11-06 | Stmicroelectronics S.R.L. | Current pulse generator with process- and temperature-independent symmetric switching times |
US6483383B2 (en) * | 2001-01-05 | 2002-11-19 | Elan Microelectronics Corporation | Current controlled CMOS transconductive amplifier arrangement |
US6639457B1 (en) * | 2002-05-15 | 2003-10-28 | Industrial Technology Research Institute | CMOS transconductor circuit with high linearity |
-
2003
- 2003-05-30 US US10/452,089 patent/US6828831B1/en not_active Expired - Fee Related
Patent Citations (5)
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US6166592A (en) * | 1998-07-31 | 2000-12-26 | Lucent Technologies Inc. | Linear CMOS transconductor with rail-to-rail compliance |
US6313684B1 (en) * | 1998-12-17 | 2001-11-06 | Stmicroelectronics S.R.L. | Current pulse generator with process- and temperature-independent symmetric switching times |
US6292034B1 (en) * | 2000-02-24 | 2001-09-18 | Motorola Inc. | Low noise transconductance device |
US6483383B2 (en) * | 2001-01-05 | 2002-11-19 | Elan Microelectronics Corporation | Current controlled CMOS transconductive amplifier arrangement |
US6639457B1 (en) * | 2002-05-15 | 2003-10-28 | Industrial Technology Research Institute | CMOS transconductor circuit with high linearity |
Cited By (1)
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CN104485891A (en) * | 2014-11-18 | 2015-04-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | Low-temperature-drift CMOS (complementary metal oxide semiconductor) oscillator circuit |
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