US20040218420A1 - Flash memory with pre-detection for data loss - Google Patents
Flash memory with pre-detection for data loss Download PDFInfo
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- US20040218420A1 US20040218420A1 US10/438,682 US43868203A US2004218420A1 US 20040218420 A1 US20040218420 A1 US 20040218420A1 US 43868203 A US43868203 A US 43868203A US 2004218420 A1 US2004218420 A1 US 2004218420A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- the invention relates to a nonvolatile memory device, and, more particularly, to a method and a circuit to prevent data retention errors in a nonvolatile memory device.
- Nonvolatile memory is a critical component in microprocessor-based systems. Maximum system flexibility is achieved through the use of nonvolatile, re-programmable memories such as flash memory. By storing operating programs or key system parameters in flash memories, system performance can be rapidly, and permanently, changed in the field.
- the flash cell 10 is a form of a MOS transistor having a source 16 and drain 14 formed in a substrate region 12 .
- a complex gate is formed comprising a control gate (CG) 20 and a floating gate (FG) 18 .
- the transistor may be operated by biasing the control gate 20 , drain 14 and source 16 as is well known in the art.
- the floating gate 18 comprises a conductive region electrically isolated from the substrate 12 by a first dielectric region 17 and electrically isolated from the control gate 20 by a second dielectric region 19 .
- the device is turned ON when a sufficient bias is applied to the control gate 20 to create a channel region of to carry charge from the drain 14 to the source 16 .
- the necessary control gate bias is defined as a threshold voltage (V TH ).
- V TH threshold voltage
- charge in the form of electrons, may be injected into or out from the floating gate 18 .
- the presence of charge on the floating gate 18 will alter the V TH of the device 10 . This fact may be used to create a digital memory cell where a first state is defined by a large presence of charge and a second state is defined by an absence of charge.
- control gate 20 may be biased to a voltage whereby the device should be ON or should be OFF, depending on the charged state of the floating gate.
- a voltage bias from drain 14 to source 16 will cause a current to flow if the device is ON. This current flow, or the absence or this current flow, may be detected to determine to state of the cell 10 as is well known in the art.
- FIG. 2 an exemplary diagram of a circuit for the reading a flash cell is illustrated.
- a section 30 of an integrated circuit device is illustrated showing an array 32 of nonvolatile cells.
- a particular cell 34 of the memory array is selected by asserting its wordline WL 42 and bit line BL by methods well known in the art.
- the WL voltage is connected to the control gate of the cell 34 and the BL voltage V BL is connected to the drain.
- the cell current I CELL is the drain-to-source current (I DS ) of the cell 34 . If the cell threshold voltage (V TH ) exceeds the WL voltage, then the cell 34 will be OFF and I CELL will be very small. If the cell V TH is less than the WL voltage, then the cell 34 will be ON and I CELL will be much larger.
- a reference cell 36 is used.
- the reference cell 36 comprises a comparable flash device having a fixed V TH .
- the reference cell 36 control gate is biased to a reference voltage V REF and the drain is biased to a bit line voltage V BL .
- a reference current I REF is generated.
- a comparitor 40 is used to compare the reference current I REF with the cell current I CELL .
- the comparitor output 46 is the decoded CELL STATE, which is either high or low.
- each cell in a flash memory array is typically tested at the factory following programming. Theoretically, the isolated floating gate and the solid state character of the device should create very long data retention times. However, it is known in the art there is a statistical distribution to the retention capabilities of cells and that some data cells will exhibit substantially shorter data retention times than the average. It is further found that these leaky cells, have a non-constant amount of floating gate charge over time. If, for example, a cell is fully charged during programming, then the cell will initially read the correct cell state of ‘X’ but later will read an incorrect cell state of ‘Y’ when the floating gate has become sufficiently discharged.
- this shortened data retention cell may create a single bit failure, as opposed to a grouped or burst failure.
- a product malfunction due to such a memory error is a serious matter. Therefore, it is of great advantage to prevent such memory errors.
- U. S. Pat. No. 6,483,745 B2 to Sacki teaches a method and a circuit to detect and to correct soft errors in a nonvolatile cell.
- the cell is read three times using three different reference transistors.
- One reference is the standard reading reference, one reference is for a programmed state threshold, and one reference is for an erase state threshold. By comparing the results of each of the three reads, the cell state and margin can be determined.
- U.S. Pat. No. 6,049,899 to Auclair et al describes a method and a circuit to detect soft errors in a nonvolatile memory array.
- U.S. Pat. No. 6,525,960 B2 to Yoshida et al discloses a method and a circuit to write a multiple value, nonvolatile memory array. A method to correct erratic cells is disclosed.
- a principal object of the present invention is to provide an effective and very manufacturable integrated circuit device.
- a further object of the present invention is to provide a method to detect and to correct weak cell states in a nonvolatile memory device.
- a yet further object of the present invention is to prevent bit errors in a nonvolatile memory device.
- a yet further object of the present invention is to selectively refresh memory cells in a nonvolatile memory device in an efficient method.
- a yet further object of the present invention is to provide a method to continuously detect weak cell states.
- a yet further object of the present invention is to provide a method for multiple level nonvolatile memory as well as for binary nonvolatile memory.
- Another further object of the present invention is to provide a nonvolatile memory device capable of detecting weak cell states.
- a method to detect and to correct a weakly programmed cell in a nonvolatile memory device comprises providing a plurality of nonvolatile memory cells.
- a means to read a selected cell compares the performance of the selected cell with the performance of a reference cell.
- a read state of the selected cell is high if the selected cell exceeds the reference cell.
- the read state of the selected cell is low if the selected cell exceeds the reference cell.
- a first read state is obtained by reading the selected cell with the reference cell biased to a first value.
- a second read state is obtained by reading the selected cell with the reference cell biased to a second value that is greater than the first value.
- the selected cell is flagged as weakly programmed, high if the first and second read states do not match.
- a third read state is obtained by reading the selected cell with the reference cell biased to a third value that is less than the first value.
- the selected cell is flagged as weakly programmed, low if the first and third read states do not match.
- the selected cell is refreshed if the selected cell is weakly programmed.
- a nonvolatile memory device comprises a plurality of nonvolatile memory cells and a means to determine a read state of a selected cell by comparing performances of the selected cell and of a reference cell.
- the reference cell has a gate biased to a read value.
- the read state is an upper value or a lower value based on the comparison.
- the means to determine a read state further comprises a first reference cell with a gate set to a first value.
- a first comparitor is coupled to the reference cell and to the selected cell.
- the first read state is the output of the first comparitor.
- a second reference cell has a gate set to a second value.
- a second comparitor is coupled to the reference cell and to the selected cell.
- the second read state is the output of the second comparitor.
- a third reference cell has a gate set to a third value.
- a third comparitor is coupled to the reference cell and to the selected cell.
- the third read state is the output of the third comparitor.
- FIG. 1 illustrates a prior art, nonvolatile memory cell.
- FIG. 2 illustrates a prior art method to read a selected cell in a nonvolatile memory.
- FIG. 3 illustrates the preferred embodiment of the method of the present invention.
- FIG. 4 illustrates a first preferred embodiment of the device of the present invention.
- FIG. 5 illustrates a second preferred embodiment of the device of the present invention.
- FIG. 6 illustrates a third preferred embodiment of the device of the present invention.
- FIG. 7 illustrates a fourth preferred embodiment of the device of the present invention.
- the preferred embodiments of the present invention disclose methods to detect and to correct weakly programmed flash memory cells. Architectures to read flash memory cells are illustrated. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention.
- FIG. 3 the preferred embodiment of the method 60 of the present invention is illustrated. Several important features of the present invention are shown and discussed below. This method 60 is further illustrated by a first embodiment device shown in FIG. 4 that is referenced during this description.
- a first preferred embodiment of an integrated circuit device 100 is illustrated.
- This device 100 comprises an array 104 of nonvolatile devices.
- the nonvolatile cells may comprise flash cells formed using any of the well-known configurations and methods. Stacked gate or split-gate devices may be used. Further, various addressing architectures could be used as are well-known in the art.
- a particular cell 106 is illustrated as a “selected” cell within the array.
- means of addressing and biasing allow a fixed reading bias to be forced onto the WL 122 for the cell 106 and a fixed BL bias V BL to be forced onto the drain of the cell 106 such that a cell current I CELL is generated.
- the relative cell current I CELL will depend on the threshold voltage V TH of the selected cell 106 .
- the V TH will further depend on the stored charge on the floating gate of the cell 106 .
- a means 108 to determine a read state of a selected cell 106 by comparing the performance of the selected cell 108 and the performance of several reference cells 110 , 114 , and 118 is included.
- the means 108 to determine the read state comprises a first reference cell 110 and first comparitor 138 , a second reference cell 114 and second comparitor 146 , and a third reference cell 118 and third comparitor 154 .
- the drain current I CELL of the selected cell 106 can be independently compared with three different, reference cell drain currents I NORM , I UPPER , and I LOWER .
- the first reference cell control gate is biased to a first read value (V NORM ).
- This first read value V NORM 126 preferably equals a mid point between an upper state value and a lower state value.
- the first reference cell 110 drain current I NORM is compared to the selected cell 106 using the first comparitor 138 .
- the output 142 of the first comparitor 138 is the first read state (CELL STATE 1 ). For example, if I CELL exceeds I NORM , then CELL STATE 1 is “upper state” (which may be further defined as a “1” or a ‘0”). If I CELL is less than I NORM , then CELL STATE 1 is “lower state”.
- the first comparitor 138 is therefore configured to perform a typical reading function as in the prior art.
- a second reference cell 114 and second comparitor 138 provide a means to test the selected cell 106 against a second threshold level V UPPER 130 that is higher than the normal, first reading threshold V NORM 126 .
- the control gate of the second reference cell 114 is set to the second read value V UPPER 130 during a read operation.
- the drain current I UPPER generated by the second reference cell 114 may be compared to the selected cell 106 drain current I CELL using the second comparitor 146 .
- the second read state CELL STATE 2 is the output 150 of the second comparitor 146 .
- CELL STATE 2 is “upper state” if I CELL exceeds I UPPER and CELL STATE 2 is “lower state” if I CELL is less than I UPPER .
- the third reference cell 118 and third comparitor 154 provide an means to test the selected cell against a third threshold level, V LOWER 134 , that is below the standard reading value of V NORM 126 .
- the control gate of the third reference cell 118 is set to the third read value V LOWER 134 during a read operation.
- the drain current I LOWER generated by the third reference cell 118 may be compared to the selected cell 106 drain current I CELL using the third comparitor 154 .
- the third read state CELL STATE 3 is the output 158 of the third comparitor 154 .
- CELL STATE 3 is “upper state” if I CELL exceeds I LOWER and CELL STATE 3 is “lower state” if I CELL is less than I LOWER .
- the method 60 comprises, first, reading selected cells using a first read value to determine a first read state in step 65 .
- the selected cells may comprise a group of cells, such as a byte (8 bits) or a word (16 bits). However, each cell, or bit, is read individually using a first reference cell 110 and comparitor 138 as shown in FIG. 4.
- the selected cells are read at a second read value where that second read value is greater than the first read value in step 70 .
- this second read corresponds to reading using the second reference cell 114 biased at the second reference value V UPPER and compared using the second comparitor 146 .
- any cells wherein the second read state does not match the first read state are flagged as weak, upper state cells in step 75 .
- the selected cells are read at a third read value of less than the first read value in step 80 .
- this third read corresponds to reading using the third reference cell 118 biased at the third reference value V LOWER and compared using the third comparitor 154 .
- any cells wherein the third read state does not match the first read state are flagged as weak, lower state cells in step 85 .
- any weak, “upper” state or weak, “lower” state cells are refreshed in step 90 . That is, by comparing the first, second, and third reads as described above, the method of the present invention can detect specific, weakly-programmed bit cells in the nonvolatile array. These weakly-programmed cells represent potential bit errors to the memory system. The memory system responds by reprogramming these cells to their existing state, whether “upper” or “lower” such that these cells are returned to a strongly programmed condition.
- FIGS. 5 and 6 second and third preferred embodiments of devices of the present invention are illustrated. Each of these embodiments shows a flash memory device incorporating three reading comparitors, as described above, along with a microprocessor device.
- the second embodiment shows a flash memory 200 and a microprocessor 232 .
- the flash memory 200 comprises a nonvolatile memory array 204 , and a reading section further comprising a normal comparitor 212 , an upper comparitor 208 , and a low comparitor 216 .
- a means 220 to select and to present a particular reading channel to the flash memory output 224 is shown.
- a signal 228 from the microprocessor is used to select any one of the normal, upper, and lower thresholds data reads as the data read value 224 , on a byte (8 bits) or a word (16 bits) basis, to be input into the microprocessor 232 .
- the microprocessor device 232 normally reads out the data value, through the data read channel 224 , using the normal threshold comparitor 212 .
- An entire section, or block, of the memory array 204 may thus be transferred into the microprocessor device 232 and then stored in a secondary memory structure, such as a RAM.
- the microprocessor device 232 may enter a test mode in which the comparitor control signal 228 selects either the upper reference comparitor or the lower reference comparitor for data reading.
- the section of the memory array 204 may be read out using the upper threshold reference comparitor 208 .
- the microprocessor device can then compare the upper threshold data reads to the normal threshold data reads stored in the RAM.
- the microprocessor device 232 can then flag any bit where the normal and upper threshold reads do not agree as a “weak” bit that should be refreshed. The microprocessor device 232 can then refresh these bit locations by writing these locations through the DATA WRITE line 226 .
- the microprocessor device 232 may enter a test mode in which the comparitor control signal 228 selects the lower reference comparitor LOWER REF 216 .
- the microprocessor device can then compare the lower threshold data reads to the normal threshold data reads stored in the RAM.
- the microprocessor device 232 can flag any bit where the normal and lower threshold reads do not agree as a “weak” bit that should be refreshed.
- the microprocessor device 232 can then refresh these bit locations by writing these locations through the DATA WRITE line 226 .
- the flash memory device 300 comprises a memory array 304 and a means of reading further comprising a NORMAL threshold comparitor 312 , a UPPER threshold comparitor 308 , and a LOWER threshold comparitor 316 .
- each of the threshold comparitors 308 , 312 , and 316 is output from the flash memory device 300 on every read operation through the UPPER READ 320 , NORM READ 324 , and LOWER READ 328 buses. It is possible, therefore, for the microprocessor device 332 to continuously monitor incoming read data for “weak” data bits.
- every bit of the incoming data bytes/words on the UPPER READ 320 , NORM READ 324 , and LOWER READ 328 lines is filtered by the microprocessor device 332 using a voting scheme to detect and correct weak bits as shown in TABLE 1 below. Where data bits are detected as “weak”, then these bits are refreshed by the microprocessor device 332 using the DATA WRITE bus 326 .
- the nonvolatile memory cells are programmed to binary levels of ‘0’ or ‘1’.
- the present invention is extendible to nonvolatile memories that are programmable to multiple levels.
- the cell may be programmed to any of three levels. In that case, the cell can take on the values 0 , 1 , or 2 .
- FIG. 7 A further extension of the idea is shown in FIG. 7.
- the selected cell 404 is programmable to any of 4 levels ( 0 , 1 , 2 , or 3 ).
- three comparitors CN 1 467 , CN 2 464 , and CN 3 461 are needed.
- six additional comparitors CL 1 468 , CU 1 466 , CL 2 465 , CU 2 463 , CL 3 462 , and CU 3 460 are needed.
- the selected cell 404 is biased by the wordline signal WL 408 to generate a cell current I CELL .
- Reference currents are generated in the nine reference cells REF 1 -REF 9 450 - 458 .
- Each reference cell is biased to a specific gate bias as shown.
- a level 1 bias V LEVEL1 440 is used to generated the I LEVEL1 current.
- the I LEVEL1 is compared to I CELL by the normal level comparitor for level 1 CN 1 467 .
- the CELL STATE LEVEL 1 signal corresponds to the level 1 state and also corresponds to the first reading described in the first embodiment.
- the upper margin of the level 1 state is measured using the upper comparitor for level 1 CU 1 466 .
- An upper reference for level 1 V UPPER1 436 biases the REF 7 cell to generate I UPPER1 .
- I UPPER1 is used to measure the level 1 upper margin corresponding to the signal CELL STATE LEVEL 1 UPPER MARGIN 476 and also corresponding to the second reading of the first embodiment.
- the third reading of the first embodiment corresponds to the CELL STATE LEVEL 1 LOWER MARGIN 478 .
- the V LOWER1 signal 446 is used to generate the I LOWER1 current in REF 9 458 .
- Levels 1 , 2 , and 3 each require three comparitors to perform the state detection and the weak programming state detection.
- Level 1 uses CL 1 468 , CN 1 467 , and CU 1 466 .
- Level 2 uses CL 2 465 , CN 2 464 , and CU 2 463 to generate the CELL STATE LEVEL 2 LOWER MARGIN 475 , CELL STATE LEVEL 2 474 , and CELL STATE LEVEL 2 UPPER MARGIN 473 .
- Level 3 uses CL 3 462 , CN 3 461 , and CU 3 460 to generate the CELL STATE LEVEL 3 LOWER MARGIN 472 , CELL STATE LEVEL 3 471 , and CELL STATE LEVEL 3 UPPER MARGIN 470 .
- Level 0 does not require additional comparitors.
- a programmable cell requires 3 comparitors for each programming level excepting the ‘0’ level. More generally, for an n-level cell, 3>(n ⁇ 1) comparitors are required.
- An effective and very manufacturable integrated circuit device is achieved.
- a method to detect and to correct weak cell states in a nonvolatile memory device is achieved. Bit errors are prevented in a nonvolatile memory device.
- An efficient method to selectively refresh memory cells in a nonvolatile memory device is achieved.
- a method to continuously detect weak cell states in a nonvolatile memory device is achieved.
- the present invention is extendible to multiple level memory devices.
- a nonvolatile memory device capable of detecting weak cell states is achieved.
- novel method and devices of the present invention provide an effective and manufacturable alternative to the prior art.
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Abstract
Description
- (1) Field of the Invention
- The invention relates to a nonvolatile memory device, and, more particularly, to a method and a circuit to prevent data retention errors in a nonvolatile memory device.
- (2) Description of the Prior Art
- Nonvolatile memory is a critical component in microprocessor-based systems. Maximum system flexibility is achieved through the use of nonvolatile, re-programmable memories such as flash memory. By storing operating programs or key system parameters in flash memories, system performance can be rapidly, and permanently, changed in the field.
- Referring now to FIG. 1, an exemplary flash memory cell is illustrated in schematic22 and cross sectional 10 forms. The
flash cell 10 is a form of a MOS transistor having asource 16 anddrain 14 formed in asubstrate region 12. A complex gate is formed comprising a control gate (CG) 20 and a floating gate (FG) 18. The transistor may be operated by biasing thecontrol gate 20,drain 14 andsource 16 as is well known in the art. Thefloating gate 18 comprises a conductive region electrically isolated from thesubstrate 12 by a firstdielectric region 17 and electrically isolated from thecontrol gate 20 by a seconddielectric region 19. As in any MOS transistor, the device is turned ON when a sufficient bias is applied to thecontrol gate 20 to create a channel region of to carry charge from thedrain 14 to thesource 16. The necessary control gate bias is defined as a threshold voltage (VTH). As is well known in the art, charge, in the form of electrons, may be injected into or out from thefloating gate 18. The presence of charge on thefloating gate 18 will alter the VTH of thedevice 10. This fact may be used to create a digital memory cell where a first state is defined by a large presence of charge and a second state is defined by an absence of charge. To program or erase the state of thecell 10, relatively large voltage biases may be applied to a combination ofcontrol gate 20,drain 14, andsource 16 to cause the injection of charge into thefloating gate 18 or to cause the removal of charge from thefloating gate 18. To read the state of thecell 10, thecontrol gate 20 may be biased to a voltage whereby the device should be ON or should be OFF, depending on the charged state of the floating gate. A voltage bias fromdrain 14 tosource 16 will cause a current to flow if the device is ON. This current flow, or the absence or this current flow, may be detected to determine to state of thecell 10 as is well known in the art. - Referring now to FIG. 2, an exemplary diagram of a circuit for the reading a flash cell is illustrated. A
section 30 of an integrated circuit device is illustrated showing anarray 32 of nonvolatile cells. Aparticular cell 34 of the memory array is selected by asserting itswordline WL 42 and bit line BL by methods well known in the art. The WL voltage is connected to the control gate of thecell 34 and the BL voltage VBL is connected to the drain. The cell current ICELL is the drain-to-source current (IDS) of thecell 34. If the cell threshold voltage (VTH) exceeds the WL voltage, then thecell 34 will be OFF and ICELL will be very small. If the cell VTH is less than the WL voltage, then thecell 34 will be ON and ICELL will be much larger. - To determine the relative VTH, and therefore the
cell 34 logic state, areference cell 36 is used. Thereference cell 36 comprises a comparable flash device having a fixed VTH. Thereference cell 36 control gate is biased to a reference voltage VREF and the drain is biased to a bit line voltage VBL. A reference current IREF is generated. Acomparitor 40 is used to compare the reference current IREF with the cell current ICELL. Thecomparitor output 46 is the decoded CELL STATE, which is either high or low. - The logic state of each cell in a flash memory array is typically tested at the factory following programming. Theoretically, the isolated floating gate and the solid state character of the device should create very long data retention times. However, it is known in the art there is a statistical distribution to the retention capabilities of cells and that some data cells will exhibit substantially shorter data retention times than the average. It is further found that these leaky cells, have a non-constant amount of floating gate charge over time. If, for example, a cell is fully charged during programming, then the cell will initially read the correct cell state of ‘X’ but later will read an incorrect cell state of ‘Y’ when the floating gate has become sufficiently discharged. In the field, this shortened data retention cell may create a single bit failure, as opposed to a grouped or burst failure. In certain applications, especially automotive or industrial control systems, a product malfunction due to such a memory error is a serious matter. Therefore, it is of great advantage to prevent such memory errors.
- Several prior art inventions relate to methods to detect bit errors in nonvolatile memories. U. S. Pat. No. 6,483,745 B2 to Sacki teaches a method and a circuit to detect and to correct soft errors in a nonvolatile cell. The cell is read three times using three different reference transistors. One reference is the standard reading reference, one reference is for a programmed state threshold, and one reference is for an erase state threshold. By comparing the results of each of the three reads, the cell state and margin can be determined. U.S. Pat. No. 6,049,899 to Auclair et al describes a method and a circuit to detect soft errors in a nonvolatile memory array. Cells are read using variable control gate voltages or using variable reference currents to thereby assess the state and margin of the cell. Cells with inadequate margin are refreshed. U.S. Pat. No. 6,525,960 B2 to Yoshida et al discloses a method and a circuit to write a multiple value, nonvolatile memory array. A method to correct erratic cells is disclosed.
- A principal object of the present invention is to provide an effective and very manufacturable integrated circuit device.
- A further object of the present invention is to provide a method to detect and to correct weak cell states in a nonvolatile memory device.
- A yet further object of the present invention is to prevent bit errors in a nonvolatile memory device.
- A yet further object of the present invention is to selectively refresh memory cells in a nonvolatile memory device in an efficient method.
- A yet further object of the present invention is to provide a method to continuously detect weak cell states.
- A yet further object of the present invention is to provide a method for multiple level nonvolatile memory as well as for binary nonvolatile memory.
- Another further object of the present invention is to provide a nonvolatile memory device capable of detecting weak cell states.
- In accordance with the objects of this invention, a method to detect and to correct a weakly programmed cell in a nonvolatile memory device is achieved. The method comprises providing a plurality of nonvolatile memory cells. A means to read a selected cell compares the performance of the selected cell with the performance of a reference cell. A read state of the selected cell is high if the selected cell exceeds the reference cell. The read state of the selected cell is low if the selected cell exceeds the reference cell. A first read state is obtained by reading the selected cell with the reference cell biased to a first value. A second read state is obtained by reading the selected cell with the reference cell biased to a second value that is greater than the first value. The selected cell is flagged as weakly programmed, high if the first and second read states do not match. A third read state is obtained by reading the selected cell with the reference cell biased to a third value that is less than the first value. The selected cell is flagged as weakly programmed, low if the first and third read states do not match. The selected cell is refreshed if the selected cell is weakly programmed.
- Also in accordance with the objects of this invention, a nonvolatile memory device is achieved. The device comprises a plurality of nonvolatile memory cells and a means to determine a read state of a selected cell by comparing performances of the selected cell and of a reference cell. The reference cell has a gate biased to a read value. The read state is an upper value or a lower value based on the comparison. The means to determine a read state further comprises a first reference cell with a gate set to a first value. A first comparitor is coupled to the reference cell and to the selected cell. The first read state is the output of the first comparitor. A second reference cell has a gate set to a second value. A second comparitor is coupled to the reference cell and to the selected cell. The second read state is the output of the second comparitor. A third reference cell has a gate set to a third value. A third comparitor is coupled to the reference cell and to the selected cell. The third read state is the output of the third comparitor.
- In the accompanying drawings forming a material part of this description, there is shown:
- FIG. 1 illustrates a prior art, nonvolatile memory cell.
- FIG. 2 illustrates a prior art method to read a selected cell in a nonvolatile memory.
- FIG. 3 illustrates the preferred embodiment of the method of the present invention.
- FIG. 4 illustrates a first preferred embodiment of the device of the present invention.
- FIG. 5 illustrates a second preferred embodiment of the device of the present invention.
- FIG. 6 illustrates a third preferred embodiment of the device of the present invention.
- FIG. 7 illustrates a fourth preferred embodiment of the device of the present invention.
- The preferred embodiments of the present invention disclose methods to detect and to correct weakly programmed flash memory cells. Architectures to read flash memory cells are illustrated. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention.
- Referring now to FIG. 3, the preferred embodiment of the
method 60 of the present invention is illustrated. Several important features of the present invention are shown and discussed below. Thismethod 60 is further illustrated by a first embodiment device shown in FIG. 4 that is referenced during this description. Referring again to FIG. 4, a first preferred embodiment of anintegrated circuit device 100 is illustrated. Thisdevice 100 comprises anarray 104 of nonvolatile devices. The nonvolatile cells may comprise flash cells formed using any of the well-known configurations and methods. Stacked gate or split-gate devices may be used. Further, various addressing architectures could be used as are well-known in the art. Aparticular cell 106 is illustrated as a “selected” cell within the array. As key features, means of addressing and biasing allow a fixed reading bias to be forced onto theWL 122 for thecell 106 and a fixed BL bias VBL to be forced onto the drain of thecell 106 such that a cell current ICELL is generated. As in the prior art device described above, it is assumed that the relative cell current ICELL will depend on the threshold voltage VTH of the selectedcell 106. Finally, the VTH will further depend on the stored charge on the floating gate of thecell 106. - A means108 to determine a read state of a selected
cell 106 by comparing the performance of the selectedcell 108 and the performance ofseveral reference cells means 108 to determine the read state comprises afirst reference cell 110 andfirst comparitor 138, asecond reference cell 114 andsecond comparitor 146, and a third reference cell 118 andthird comparitor 154. With this novel arrangement, the drain current ICELL of the selectedcell 106 can be independently compared with three different, reference cell drain currents INORM, IUPPER, and ILOWER. The first reference cell control gate is biased to a first read value (VNORM).This firstread value V NORM 126 preferably equals a mid point between an upper state value and a lower state value. Thefirst reference cell 110 drain current INORM is compared to the selectedcell 106 using thefirst comparitor 138. Theoutput 142 of thefirst comparitor 138 is the first read state (CELL STATE1). For example, if ICELL exceeds INORM, then CELL STATE1 is “upper state” (which may be further defined as a “1” or a ‘0”). If ICELL is less than INORM, then CELL STATE1 is “lower state”. Thefirst comparitor 138 is therefore configured to perform a typical reading function as in the prior art. - As an important feature, a
second reference cell 114 andsecond comparitor 138 provide a means to test the selectedcell 106 against a secondthreshold level V UPPER 130 that is higher than the normal, firstreading threshold V NORM 126. The control gate of thesecond reference cell 114 is set to the secondread value V UPPER 130 during a read operation. The drain current IUPPER generated by thesecond reference cell 114 may be compared to the selectedcell 106 drain current ICELL using thesecond comparitor 146. The second read state CELL STATE2 is theoutput 150 of thesecond comparitor 146. In the preferred configuration, CELL STATE2 is “upper state” if ICELL exceeds IUPPER and CELL STATE2 is “lower state” if ICELL is less than IUPPER. In similar fashion, the third reference cell 118 andthird comparitor 154 provide an means to test the selected cell against a third threshold level,V LOWER 134, that is below the standard reading value ofV NORM 126. The control gate of the third reference cell 118 is set to the thirdread value V LOWER 134 during a read operation. The drain current ILOWER generated by the third reference cell 118 may be compared to the selectedcell 106 drain current ICELL using thethird comparitor 154. The third read state CELL STATE3 is theoutput 158 of thethird comparitor 154. In the preferred configuration, CELL STATE3 is “upper state” if ICELL exceeds ILOWER and CELL STATE3 is “lower state” if ICELL is less than ILOWER. - Referring again to FIG. 3, the
preferred method 60 to detect and to correct weak cells states in the above-described nonvolatile memory device is now described. Themethod 60 comprises, first, reading selected cells using a first read value to determine a first read state instep 65. The selected cells may comprise a group of cells, such as a byte (8 bits) or a word (16 bits). However, each cell, or bit, is read individually using afirst reference cell 110 andcomparitor 138 as shown in FIG. 4. - Referring again to FIG. 3, the selected cells are read at a second read value where that second read value is greater than the first read value in
step 70. Referring again to FIG. 4, this second read corresponds to reading using thesecond reference cell 114 biased at the second reference value VUPPER and compared using thesecond comparitor 146. Referring again to FIG. 3, as an important step, any cells wherein the second read state does not match the first read state are flagged as weak, upper state cells instep 75. Referring again to the embodiment of FIG. 4, a comparison is made of theCELL STATE2 150 reading and theCELL STATE1 142 reading, If CELL STATE2 does not equal CELL STATE1 for a selectedcell 106, then it can be concluded that thecell 106 is programmed to the “upper” state. In addition, it can also be concluded that the cell is only weakly programmed to the “upper” state. In other words, while thefirst reading comparitor 142 indicates that the cell is in the “upper” state, thecell 106 has experienced discharging to an extent that it no longer passes the more stringent VUPPER threshold. According to the teachings of this invention, thecell 106 is in danger of failing. Alternatively, if CELL STATE2 equals CELL STATE1, then either thecell 106 is in the “lower” state or thecell 106 is strongly in the “upper” state and, therefore, not in danger of failing. - Referring again to FIG. 3, the selected cells are read at a third read value of less than the first read value in
step 80. Referring again to FIG. 4, this third read corresponds to reading using the third reference cell 118 biased at the third reference value VLOWER and compared using thethird comparitor 154. Referring again to FIG. 3, as an important step, any cells wherein the third read state does not match the first read state are flagged as weak, lower state cells instep 85. Referring again to the embodiment of FIG. 4, a comparison is made of theCELL STATE3 158 reading and theCELL STATE1 142 reading, If CELL STATE3 does not equal CELL STATE1 for a selectedcell 106, then it can be concluded that thecell 106 is programmed to the “lower” state. In addition, in can be concluded that thecell 106 is only weakly programmed to the “lower” state. In other words, while thefirst reading comparitor 142 indicates that the cell is in the “upper” state, thecell 106 has experienced discharging to an extent that it no longer passes the more stringent VLOWER threshold. According to the teachings of this invention, thecell 106 is in danger of failing. Alternatively, if CELL STATE3 equals CELL STATE1, then either thecell 106 is in the “upper” state or thecell 106 is strongly in the “lower” state and, therefore, not in danger of failing. - Referring again to FIG. 3, any weak, “upper” state or weak, “lower” state cells are refreshed in
step 90. That is, by comparing the first, second, and third reads as described above, the method of the present invention can detect specific, weakly-programmed bit cells in the nonvolatile array. These weakly-programmed cells represent potential bit errors to the memory system. The memory system responds by reprogramming these cells to their existing state, whether “upper” or “lower” such that these cells are returned to a strongly programmed condition. - Referring now to FIGS. 5 and 6, second and third preferred embodiments of devices of the present invention are illustrated. Each of these embodiments shows a flash memory device incorporating three reading comparitors, as described above, along with a microprocessor device. Referring specifically to FIG. 5, the second embodiment shows a
flash memory 200 and a microprocessor 232. Theflash memory 200 comprises anonvolatile memory array 204, and a reading section further comprising anormal comparitor 212, anupper comparitor 208, and alow comparitor 216. As an additional important feature, ameans 220 to select and to present a particular reading channel to the flash memory output 224 is shown. A signal 228 from the microprocessor is used to select any one of the normal, upper, and lower thresholds data reads as the data read value 224, on a byte (8 bits) or a word (16 bits) basis, to be input into the microprocessor 232. - The microprocessor device232 normally reads out the data value, through the data read channel 224, using the
normal threshold comparitor 212. An entire section, or block, of thememory array 204 may thus be transferred into the microprocessor device 232 and then stored in a secondary memory structure, such as a RAM. Next, the microprocessor device 232 may enter a test mode in which the comparitor control signal 228 selects either the upper reference comparitor or the lower reference comparitor for data reading. For example, the section of thememory array 204 may be read out using the upperthreshold reference comparitor 208. The microprocessor device can then compare the upper threshold data reads to the normal threshold data reads stored in the RAM. The microprocessor device 232 can then flag any bit where the normal and upper threshold reads do not agree as a “weak” bit that should be refreshed. The microprocessor device 232 can then refresh these bit locations by writing these locations through the DATA WRITE line 226. - Similarly, the microprocessor device232 may enter a test mode in which the comparitor control signal 228 selects the lower reference
comparitor LOWER REF 216. The microprocessor device can then compare the lower threshold data reads to the normal threshold data reads stored in the RAM. The microprocessor device 232 can flag any bit where the normal and lower threshold reads do not agree as a “weak” bit that should be refreshed. The microprocessor device 232 can then refresh these bit locations by writing these locations through the DATA WRITE line 226. - Referring again to FIG. 6, the third preferred embodiment of the device of the present invention is illustrated. In this embodiment, the
flash memory device 300 comprises amemory array 304 and a means of reading further comprising aNORMAL threshold comparitor 312, aUPPER threshold comparitor 308, and aLOWER threshold comparitor 316. In this embodiment, each of thethreshold comparitors flash memory device 300 on every read operation through the UPPER READ 320, NORM READ 324, andLOWER READ 328 buses. It is possible, therefore, for themicroprocessor device 332 to continuously monitor incoming read data for “weak” data bits. As a preferred approach, every bit of the incoming data bytes/words on the UPPER READ 320, NORM READ 324, andLOWER READ 328 lines is filtered by themicroprocessor device 332 using a voting scheme to detect and correct weak bits as shown in TABLE 1 below. Where data bits are detected as “weak”, then these bits are refreshed by themicroprocessor device 332 using the DATA WRITE bus 326.TABLE 1 Voting Scheme for Detection and Correction of Weak Bits UPPER NORMAL LOWER THRESHOLD THRESHOLD THRESHOLD VOTING VALUE LOW LOW LOW LOW LOW LOW HIGH LOW, NEEDS REFRESH LOW HIGH HIGH HIGH, NEEDS REFRESH HIGH HIGH HIGH HIGH - Referring now to FIG. 7, a fourth embodiment of the present invention is illustrated. In the previous embodiments, the nonvolatile memory cells are programmed to binary levels of ‘0’ or ‘1’. The present invention is extendible to nonvolatile memories that are programmable to multiple levels. For example, the cell may be programmed to any of three levels. In that case, the cell can take on the
values cell 404 is programmable to any of 4 levels (0, 1, 2, or 3). To read such acell 404, threecomparitors CN1 467, CN2 464, andCN3 461 are needed. To perform the novel detection and correction of a weakly programmed cell, sixadditional comparitors CL1 468,CU1 466,CL2 465,CU2 463,CL3 462, andCU3 460 are needed. - The selected
cell 404 is biased by thewordline signal WL 408 to generate a cell current ICELL. Reference currents are generated in the nine reference cells REF1-REF9 450-458. Each reference cell is biased to a specific gate bias as shown. In particular, alevel 1 bias VLEVEL1 440 is used to generated the ILEVEL1 current. The ILEVEL1 is compared to ICELL by the normal level comparitor forlevel 1CN1 467. TheCELL STATE LEVEL 1 signal corresponds to thelevel 1 state and also corresponds to the first reading described in the first embodiment. The upper margin of thelevel 1 state is measured using the upper comparitor forlevel 1CU1 466. An upper reference for level 1V UPPER1 436 biases the REF7 cell to generate IUPPER1. IUPPER1 is used to measure thelevel 1 upper margin corresponding to the signalCELL STATE LEVEL 1 UPPER MARGIN 476 and also corresponding to the second reading of the first embodiment. The third reading of the first embodiment corresponds to theCELL STATE LEVEL 1 LOWER MARGIN 478. The VLOWER1 signal 446 is used to generate the ILOWER1 current inREF9 458. -
Levels Level 1 usesCL1 468,CN1 467, andCU1 466.Level 2 usesCL2 465, CN2 464, andCU2 463 to generate theCELL STATE LEVEL 2LOWER MARGIN 475,CELL STATE LEVEL 2 474, andCELL STATE LEVEL 2UPPER MARGIN 473.Level 3 usesCL3 462,CN3 461, andCU3 460 to generate theCELL STATE LEVEL 3 LOWER MARGIN 472,CELL STATE LEVEL 3 471, andCELL STATE LEVEL 3 UPPER MARGIN 470. Level 0 does not require additional comparitors. In general, a programmable cell requires 3 comparitors for each programming level excepting the ‘0’ level. More generally, for an n-level cell, 3>(n−1) comparitors are required. - The advantages of the present invention may now be summarized. An effective and very manufacturable integrated circuit device is achieved. A method to detect and to correct weak cell states in a nonvolatile memory device is achieved. Bit errors are prevented in a nonvolatile memory device. An efficient method to selectively refresh memory cells in a nonvolatile memory device is achieved. A method to continuously detect weak cell states in a nonvolatile memory device is achieved. The present invention is extendible to multiple level memory devices. A nonvolatile memory device capable of detecting weak cell states is achieved.
- As shown in the preferred embodiments, the novel method and devices of the present invention provide an effective and manufacturable alternative to the prior art.
- While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
Claims (30)
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CNA2004100550563A CN1591693A (en) | 2003-04-29 | 2004-04-29 | Flash memory with pre-detection for data loss |
KR1020040029839A KR100710608B1 (en) | 2003-04-29 | 2004-04-29 | Flash memory with pre-detection for data loss |
JP2004135212A JP2004355793A (en) | 2003-04-29 | 2004-04-30 | Flash memory with pre-detection for data loss |
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EP03392005A EP1473739A1 (en) | 2003-04-29 | 2003-04-29 | Flash memory with pre-detection for data loss |
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EP03392005 | 2003-04-29 |
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US7116602B2 (en) | 2004-07-15 | 2006-10-03 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
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