US20040173159A1

US20040173159A1 - Semiconductor process chamber electrode

Info

Publication number: US20040173159A1
Application number: US10/796,836
Authority: US
Inventors: Andras Kuthi; Lumin Li
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 1998-06-19
Filing date: 2004-03-08
Publication date: 2004-09-09
Also published as: PL195681B1; MY124608A; IL140277A; TW414971B; HUP0101824A2; EP1090407A1; KR100557444B1; KR20010071535A; RU2212077C2; WO1999066533A1; JP2002518842A; AU4568099A; IL140277A0; EP1090407B1; JP4565743B2; US6106663A; HUP0101824A3; WO1999066533A9; ATE460743T1; CN1258805C

Abstract

Disclosed is an electrode used for processing a semiconductor wafer through plasma etching operations. The electrode is disposed within a process chamber that includes a support chuck for holding the semiconductor wafer and a pair of RF power sources. The electrode has a center region, a first surface and a second surface. The first surface is configured to receive processing gases from a source and to flow the processing gases into the center region. The second surface has a plurality of gas feed holes that are continuously coupled to a corresponding plurality of electrode openings. Electrode opening diameters are greater than gas feed hole diameters. The plurality of electrode openings define an electrode surface that is over a wafer surface. The electrode surface assists in defining an electrode plasma sheath surface area which causes an increase in bias voltage onto the wafer surface, thereby increasing the ion bombardment energy over the wafer without increasing the plasma density.

Description

This application is a Continuation Application of U.S. patent application Ser. No. 09/611,037, filed Jul. 6, 2000, and entitled “METHOD FOR MAKING A SEMICONDUCTOR PROCESS CHAMBER ELECTRODE,” which is a Divisional Application of U.S. patent application Ser. No. 09/100,268, filed on Jun. 19, 1998, entitled “SEMICONDUCTOR PROCESS CHAMBER ELECTRODE AND METHOD FOR MAKING THE SAME,” now U.S. Pat. No. 6,106,663.[0001]

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor fabrication equipment, and more particularly, the present invention relates to improved semiconductor processing chamber electrodes and methods for making and implementing the improved electrodes.

2. Description of the Related Art

In semiconductor fabrication, integrated circuit devices are fabricated from semiconductor wafers that are placed through numerous processing operations. Many of the numerous processing operations are commonly carried out in processing chambers in which layers, such as, dielectric and metallization materials are successively applied and patterned to form multi-layered structures. For example, some of these layers (e.g., SiO ₂) are commonly deposited in chemical vapor deposition (CVD) chambers, and then photoresist materials are spin-coated and placed through photolithography patterning. When a photoresist mask is defined over a particular surface, the semiconductor wafer is placed into a plasma etching chamber in order to remove (i.e., etch) portions of the underlying materials that are not covered by the photoresist mask.

FIG. 1A shows a

semiconductor processing system

100 including a chamber 102 that is used for processing semiconductor wafers through etching operations. In this example, the chamber 102 includes a chuck 104 which is configured to support a semiconductor wafer 106. The chuck 104 also supports a plurality of quartz rings 108. Over a topmost quartz ring 108, sits a ceramic ring holder 110, which is configured to hold a top electrode 114. The top electrode 114 is configured to receive processing gases which will be distributed into the plasma region 112 during processing.

The top electrode is also shown coupled to a match box and

diplexer

116 a and an RF power source 118 a. The chuck 104 is also coupled to a match box and diplexer 116 b and an RF power source 118 b. The chamber 102 is provided with outlets 120 which are configured to pump out excess gases from within the chamber during processing. In operation, the RF power supply 118 a is configured to bias the top electrode 114 and operate at frequencies of about 27 MHz. The RF power source 118 a is primarily responsible for generating most of the plasma density within the plasma region 112, while the RF power source 118 b is primarily responsible for generating a bias voltage within the plasma region 112. The RF power source 118 b generally operates at lower frequencies in the range of about 2 MHz.

FIG. 1B provides a more detailed view of the

top electrode

114 of the semiconductor processing system 100. The top electrode 114 generally includes a number of gas buffer plates 122 which have a plurality of holes defined throughout their surface region, and are configured to evenly distribute the processing gases throughout the top electrode 114. In this manner, the gas buffer plates 112 will ensure that an about equal amount of gas is allowed to flow out of each of the gas feed holes 128 of a silicon plate 126. The top electrode 114 also has a graphite ring 124 which is configured to mount onto the ceramic holders 110 of FIG. 1A. Once the process gases are allowed to flow out of the gas feed holes 128, a plasma may be generated in the plasma region 112 that is defined between the surface of the silicon plate 126 and a surface of the wafer 106.

During operation, the

RF power

118 a and the RF power 118 b is applied to the top electrode 114 and the chuck 104, respectively. Once the process gases are channeled into the top electrode 114 and allowed to flow out of the gas feed holes 128 into the plasma region 112, a

plasma sheath

131 and 132 will be defined within the plasma region 112 as shown in FIG. 1C.

As pictorially shown, the

silicon plate

126 will have an electrode surface 134 which is directly opposite a wafer surface 136 of the semiconductor wafer 106. As is well understood in plasma physics, the electrode surface 134 and the wafer surface 136 are partially responsible for producing the

plasma sheaths

131 and 132 within the plasma region 112.

Specifically, as shown in FIG. 1D, plasma sheaths edges are defined at

points

133 a and 133 b along a plasma density profile 133. The plasma density profile illustrates that the plasma concentration falls to about zero near the wafer surface 136 and the top electrode surface 134. As such, the plasma concentration gradually increases from zero up to a constant concentration between

points

133 a and 133 b. The electrode surface 134 and the wafer surface 136 will therefore ensure that the bulk of the plasma is contained between the

plasma sheaths

131 and 132 as shown in FIG. 1C.

As the demand to etch smaller and smaller integrated circuit device patterns continues to increase, more difficult high aspect ratio etching will be needed. As shown in FIG. 1E, a cross

sectional view

140 of a wafer substrate 106′ is shown. The wafer substrate 106′ has a dielectric layer 140 deposited thereon and a patterned photoresist layer 142. The photoresist layer 142 has a patterned window 144 defining a window down to the dielectric layer 140. As the aspect ratios continue to increase (i.e., deeper and narrower etching geometries), a process window that defines a set of controllable process parameters will also rapidly shrink. When the process window shrinks, adjustment of process parameters will no longer improve etch rates, etch selectivities, or etch profiles.

Typically, the process parameters include pressure settings, flow rates, electrode biasing powers, types of processing chemistries, and so on. However, as aspect ratios continue to increase, varying the process window parameters no longer assist a processing chamber's ability to control a desired etching operation. For example, when a geometry such as that defined by the patterned window 144 (i.e., for a contact via or the like) in the photoresist layer 142 is desired, the best etching chemistries may no longer be able to etch all the way down through the dielectric layer 140. When that happens, a premature etch stop 146 will develop because the processing chemistries will also be depositing polymers on the sidewalls and the bottom during the etching operation. As is well known, this polymer deposition can seriously retard the etching of dielectric layers 140 when high aspect ratio patterns are the subject of etching.

In efforts to combat this problem, process engineers have in the past, attempted to increase the level of oxygen within the processing chamber during an etch operation. Unfortunately, when the oxygen level is increased within the processing chamber, the etching operation will produce a bow-

shaped etch

148 within the dielectric layer 140. As can be appreciated, when such a bow-shaped etch 148 occur within the dielectric layer 140, subsequent filling of the via hole defined by the bow-shaped etch 148 will be problematic. That is, conventional conductive fill techniques used to deposit metallization within a via hole may not work because of the bow-shaped etch via 148. As a result, a fabricated device having the bow-shaped etch via holes 148 may fail to function within its intended design.

Another solution attempted in the prior art has been to increase the bias power of the

RF power source

118 b that is coupled to the chuck 104 in an attempt to increase the ion bombardment energy over the surface of the wafer 106. However, when the bias voltage of the RF power source 118 b is increased, more plasma is also generated within the plasma region 114, which counteracts the increase in ion bombardment energy. In addition, the processing molecules channeled into the plasma region 112 may change their chemical composition when the bias power is increased, and therefore, may fail to perform the desired etching. Consequently, it has been observed that merely increasing the RF power that is applied to the chuck 104 does not help in improving the etching of high aspect ratio geometries.

In view of the foregoing, what is needed is a processing apparatus and method for making and implementing the apparatus which will assist in increasing the ion bombardment energy at the surface of a wafer without also increasing the plasma density or changing the chemical composition of the processing molecules.

SUMMARY OF THE INVENTION

The present invention fills these needs by providing a semiconductor processing chamber electrode that assists in shifting an increased ion bombardment energy toward the surface of the semiconductor wafer. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, and a method. Several inventive embodiments of the present invention are described below.

In one embodiment, an apparatus is provided. The apparatus includes an electrode capable of being positioned over a substrate location. The electrode has a center region, a first surface and a second surface. The first surface is configured to receive processing gases and to enable flow of the processing gases through the center region. The second surface has a plurality of gas feed holes that are coupled to a corresponding plurality of electrode openings having electrode opening diameters that are greater than gas feed hole diameters of the plurality of gas feed holes. The plurality of electrode openings are configured to define the second surface which is located over the substrate location. The second surface has a surface area that is larger than a surface area of the substrate location. The larger surface area is capable of inducing an increased bias voltage at a point closer to the substrate location and a decreased bias voltage at a point closer to the second surface of the electrode when a plasma is struck in a space defined by the second surface and the substrate location.

In another embodiment, a electrode is provided. The electrode includes an electrode body having a first surface and a second surface. The second surface has a plurality of gas feed holes that are coupled to a corresponding plurality of electrode openings. Each electrode opening has an electrode opening diameter that is greater than a gas feed hole diameter of each of the plurality of gas feed holes. The second surface is defined by inner surfaces of the plurality of electrode openings so that a surface area of the second surface is larger than a surface area of the electrode body without the plurality of electrode openings. The larger second surface area is capable of inducing an increased bias voltage at a substrate processing surface.

In yet another embodiment, an electrode is provided. The electrode includes an electrode body which includes a first surface and a second surface. The second surface has a plurality of gas feed holes. Each one of the plurality of gas feed holes is integrally coupled to a corresponding electrode opening to comprise a plurality of electrode openings. Each one of the plurality of electrode openings is larger than each one of the plurality of gas feed holes. The second surface defines a boundary of a plasma sheath. The plasma sheath has a first plasma sheath surface and a second plasma sheath surface. The second plasma sheath surface is at least partially within the plurality of electrode openings.

In still a further embodiment, an electrode is provided. The electrode includes an electrode body with a process surface. The process surface has a plurality of gas feed holes. Each gas feed hole is integrally coupled to a corresponding electrode opening. The electrode opening is larger than the gas feed hole, and the process surface defines a plasma sheath which has a surface that is at least partially within each electrode opening.

Advantageously, it is now possible to increase the bias voltage over the surface of the wafer without also causing an increase in plasma density. Because an increased bias voltage is essentially an increase in ion bombardment energy, higher aspect ratio geometries can now be etched without causing premature etch stops or bow etch profiles. These and other advantages of the present invention will become apparent upon reading the following detailed descriptions and studying the various figures of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings. [0023]
FIG. 1A shows a semiconductor processing system including a chamber that is used for processing semiconductor wafers through etching operations. [0024]
FIG. 1B provides a more detailed view of a top electrode of a semiconductor processing system. [0025]
FIG. 1C shows a plasma and plasma sheaths formed next to an electrode surface and a wafer surface. [0026]
FIG. 1D shows a plasma concentration profile and the plasma sheath locations relative to an electrode surface and a wafer surface. [0027]
FIG. 1E shows a cross sectional view of a semiconductor substrate undergoing an etch operation. [0028]
FIG. 2A shows a cross sectional view of a top electrode in accordance with one embodiment of the present invention. [0029]
FIG. 2B shows a plan view of a surface of the electrode body in accordance with one embodiment of the present invention. [0030]
FIG. 2C shows a more detailed view of the electrode opening of FIG. 2A in accordance with one embodiment of the present invention. [0031]
FIG. 2D shows an alternative detailed view of an electrode opening in accordance with one embodiment of the present invention. [0032]
FIG. 2E shows a more detailed view of the electrode opening surfaces, a wafer surface, and a corresponding plasma having plasma sheaths in accordance with one embodiment of the present invention. [0033]
FIG. 3 shows a more detailed view of a contoured plasma sheath that is defined into the electrode openings and a substantially planar plasma sheath that is defined over the wafer surface in accordance with one embodiment of the present invention. [0034]
FIG. 4A shows voltage waveforms plotted over time, including a shifted voltage waveform that causes a shift in bias voltage in accordance with one embodiment of the present invention. [0035]
FIG. 4B shows a graph illustrating the resulting current magnitudes over a cycle of a shifted voltage waveform of FIG. 4A in accordance with one embodiment of the present invention. [0036]
FIG. 5 is a graph illustrating bias vs. area ratio for the plasma sheaths of a top electrode and a wafer in accordance with one embodiment of the present invention. [0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An invention is described for a semiconductor processing chamber electrode that assists in shifting an increased plasma ion bombardment energy toward the surface of the semiconductor wafer to improve etching of high aspect ratio geometries. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention. [0038]
As described above, the present invention discloses a unique top electrode that enables processing chambers to retain control of processing windows during high aspect ratio etching operations. Although the top electrodes of the present invention can be implemented into many different types of processing chambers, one exemplary chamber that will benefit from the inventive design features of the disclosed top electrodes is a Lam Research Rainbow 4520XL processing chamber, which is available from Lam Research Corporation of Fremont, Calif. In some chamber orientations, the top electrode may be grounded and both frequencies are fed to the bottom electrode (i.e., wafer support chuck). In either case, the top electrode configuration of the present invention will assist in increasing the ion bombardment energy on the surface of the wafer without the side effects of the prior art. [0039]
FIG. 2A shows a cross sectional view of a [0040] top electrode 200 in accordance with one embodiment of the present invention. In this embodiment, the top electrode 200 includes an electrode body 202 that has a plurality of electrode regions 202 c that define respective electrode openings 202 b. The electrode openings 202 b form a channel that leads to a plurality of gas feed holes 228. In general, the gas feed holes 228 channel the processing gases to a plasma region 112, as described with respect to FIG. 1A. Accordingly, when the top electrode 200 is inserted into a semiconductor processing system chamber, a surface 234 of the electrode body 202 will define the surface that is in close proximity to a generated plasma sheath.
In a preferred embodiment of the present invention, the inter-portion of the [0041] electrode body 202 will preferably have an opening 250 which is about the same diameter of a wafer being processed. For example, when an 8-inch wafer is being processed, the diameter 250 is preferably sized to be about 8 inches. Although not shown, gas buffer plates are typically positioned within the electrode body 202. The electrode body 202 has a preferred thickness 252 of about 1 inch, while the electrode regions 202 c have a thickness 256 that is about ¼ inch. Of course, these exemplary dimensions may be modified depending on the size of the semiconductor wafer being processed.
FIG. 2B shows a plan view of the [0042] surface 234 of the electrode body 202 in accordance with one embodiment of the present invention. As shown, the electrode openings 202 b are preferably arranged throughout the surface 234 in a hexagonal pattern arrangement. In this hexagonal pattern arrangement, the separation 203 between the electrode openings 202 b is preferably set to about 0.375 inches. Also, in a preferred embodiment, the diameter of each of the electrode openings 202 b is set to be about 0.25 inches.
FIG. 2C shows a more detailed view of the [0043] electrode opening 202 b of FIG. 2A in accordance with one embodiment of the present invention. The electrode opening 202 b has a diameter D ₃ 242 that is selected to be at least equal to or greater than about 5 Λ_Debye(i.e., ≧0.5 mm). The depth D ₄ 244 of the electrode opening 202 b is preferably set to be between about {fraction (1/32)} inch and about ¼ inch, and more preferably between about {fraction (1/16)} inch and about ¼ inch, and most preferably about ⅛ inch. Preferably, the diameter D ₂ 240 is about 0.1 mm. In this embodiment, the electrode opening 202 b has an angled (about 30 degrees) surface 246, which is caused by the profile of a machining drill bit. However, it should be understood that other angles will work as well. For example, FIG. 2D shows a case in which the angled surface 246 is replaced with a right angle 248. Of course, when the angled surface 246 is removed, the electrode opening 202 b may extend to a distance D ₅ 249, which may be greater than distance D ₄ 244.
FIG. 2E shows a cross sectional view of three [0044] electrode regions 202 c and a cross section of the wafer 206 in accordance with one embodiment of the present invention. In a preferred embodiment, the distance between the surface 234 and the wafer surface 236 is preferably set to be between about 0.75 cm and about 4 cm, and more preferably between about 1 cm and about 3 cm, and most preferably about 2 cm. Once the semiconductor processing system is placed into its operational state (i.e., processing gases have been flown into the chamber, biasing powers have been set, pressures and temperatures adjusted, etc.), a plasma is generated within a plasma region 212. Because the electrode openings 202 b have been increased to be at least equal to or greater than about 5 mm, a plasma sheath 231 is caused to shift into the electrode openings 202 b.
As pictorially shown, the shifted [0045] plasma sheath 231 follows the profile of the electrode opening 202 b walls. That is, the plasma sheath 231 is separated from the surface 234 and electrode opening surfaces 204 by a distance D ₁ 233. In one embodiment, the distance D ₁ 233 may be between about 0.5 mm, and about 5 mm, and most preferably about 2 mm. Because the plasma sheath next to the top electrode in prior art designs is not shifted as shown in FIG. 1C, the surface area of both plasma sheaths will be about equal. However, because the plasma sheath 231 is shifted into the electrode openings 202 b throughout the top electrode 200, the surface area of the plasma sheath 231 will be greater than the surface area of the plasma sheath 232.

FIG. 3 shows a cross sectional view of the

plasma sheath

231 that conforms to the surfaces of the electrode regions 202 c as shown in FIG. 2E, and the plasma sheath 232 that is defined above the wafer 206. Although only a cross sectional view of the

sheaths

231 and 232 are shown, it should be understood that the sheaths are actually three-dimensional (3D) blankets that are defined over each of the surfaces of the top electrode 200 and the wafer 206. As such, a substantial increase in sheath area, is produced when the sheath 231 shifts into the electrode openings 202 b. Table A below shows an exemplary calculation of the increase in sheath 231 surface area, compared to the sheath 232 surface area₂. Of course, other area increases may be obtained depending on the specific electrode opening geometries.

TABLE A


TOP ELECTRODE AREA INCREASE

Electrode Opening 202b	diameter (d = 1/4 in)	depth (h = 1/8 in)
Distance Between	D = 3/8 in
Electrode Openings
Transparency	T = (d²π/D²{square root over (3)})	T = 0.806
Added Area	A = (dπh) +	A = 0.682 cm²
	((1/cos(30 deg)) − 1)d²π/4
Base Area	B = ((D²{square root over (3)})/4)	B = 0.393 cm²
Area Increase	I = (B + A)/B	I = 2.7

As shown from the calculations of Table A, the surface area[0047] ₁of the plasma sheath 231 has increased to about 2.7 times the surface area₂of the sheath 232 that is defined over the wafer 206. In other preferred embodiments, the increase in area can be between about 1.5 and 3.5, and most preferably between about 2 and about 3.
FIG. 4A shows a [0048] graph 300 depicting sinusoidal RF voltage waveforms over time in accordance with one embodiment of the present invention. In this example, a sinusoidal voltage wave 302 of a prior art design having equal area sheaths (i.e., area₁=area₂) is shown. When the area sheaths are equal, the sinusoidal voltage wave 302 will be positive for an equal amount of time as it is negative. However, once the electrode 200 is placed into the processing chamber, the area₁of the sheath 231 will increase as shown in FIG. 3. At this point, the magnitude of current (ion and electron current) flowing through the plasma will be different during the time that a current I₁flows away from the wafer 206 in the direction of the top electrode 200 and during the time that a current I₂flows away from the top electrode 200 in the direction of the wafer 206. In fact, because there is a greater sheath surface area, close to the top electrode surface 234/204, the current I₁will have a greater magnitude than the current 12 as depicted in FIG. 3.
Because of this current magnitude difference, the [0049] sinusoidal voltage wave 302 will shift downward to form a shifted sinusoidal voltage wave 302′. At this point, it should be evident that the shifted sinusoidal voltage wave 302′ will be positive for a shorter amount of time T₁than it is negative T₂. However, over a full cycle, the current flowing in one direction (i.e., I₁) across the plasma has to be the same as the current flowing in the other direction (i.e., I₂). FIG. 4B illustrates how a total current during time T₁for the larger magnitude current I₁will actually equal a total current during a time T₂for a smaller magnitude current I₂. Specifically, the area under 320 a defines the net current for I₁and the area under 320 b defines the net current for I₂. For reference purposes only, the net current under area 310 a and 310 b are also equal to each other in a non-shifted system.
Referring back to FIG. 4A, a [0050] wave portion 306 is the result of a half-wave rectification that is induced by the generated plasma. When a time average is taken over one cycle of the wave portion 306, a bias voltage on the surface of the top electrode is produced. In a like manner, a wave portion 308 is the result of another half-wave rectification that was induced by the generated plasma. Upon taking a time average over one cycle of the wave portion 308, a bias voltage on the surface of the wafer is produced. It is important to note that the bias voltage produced on the surface of the wafer 206 has substantially increased over the standard bias voltage. That is, in prior art systems, the applied bias voltage is generally equally applied to both the surface of the top electrode and the surface of the wafer. Thus, by increasing the surface area of the sheath 231 that is proximate to the top electrode 200 surface, it is possible to increase the bias voltage over the surface of wafer 206, while slightly decreasing the bias voltage over the surface of the top electrode 200.
FIG. 5 shows a graph illustrating bias vs. area ratio for the plasma sheaths of the [0051] top electrode 200 and the wafer 206, assuming that a sinusoidal RF potential is used and proper current balancing is in effect, in accordance with one embodiment of the present invention. When the sheath areas of the top electrode 200 and wafer 206 are about the same, the bias voltage (i.e., Electrode Potential/V_peak) on both the top electrode 200 and wafer 206 will be about −0.3. However, the bias voltage of the top electrode 200 is shown to decrease as the area ratio increases. Conversely, the bias of the wafer 206 is shown to increase as the area ratio increases.
In a preferred embodiment, when the [0052] plasma sheath 231 has an area, that is about 2.7 times greater than the area₂of the plasma sheath 232, the bias voltage on the wafer 206 will increase to about −0.75, while the bias voltage on the top electrode 200 will decrease to about −0.05. Because the bias voltage is now greater on the surface of the wafer 206, a larger ion bombardment energy will be present on the surface of the wafer 206 to assist in high aspect ratio semiconductor etching operations.
As an advantage, it is now possible to increase the bias voltage over the surface of the [0053] wafer 206 without causing an increase in plasma density. As mentioned above, when the plasma density is caused to increase beyond an acceptable level, the processing gases may fail to perform their desired etching functions. Further yet, because an increased bias voltage is essentially an increase in ion bombardment energy, higher aspect ratio geometries can now be etched without causing premature etch stops, bow etch effects, or process window shifts.
In addition, although the above described parameters are associated with chambers configured to process “8 inch wafers,” the parameters may be modified for application to substrates of varying sizes and shapes, such as those employed in the manufacture of semiconductor devices and flat panel displays. While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.[0054]

Claims

What is claimed is:

1. An apparatus, comprising:

an electrode capable of being positioned over a substrate location, the electrode having a center region, a first surface and a second surface, the first surface being configured to receive processing gases and to enable flow of the processing gases through the center region, the second surface having a plurality of gas feed holes that are coupled to a corresponding plurality of electrode openings having electrode opening diameters that are greater than gas feed hole diameters of the plurality of gas feed holes, the plurality of electrode openings being configured to define the second surface which is located over the substrate location, the second surface having a surface area that is larger than a surface area of the substrate location, the larger surface area being capable of inducing an increased bias voltage at a point closer to the substrate location and a decreased bias voltage at a point closer to the second surface of the electrode when a plasma is struck in a space defined between the second surface and the substrate location.

2. The apparatus of claim 1, wherein a first plasma sheath surface is defined next to the substrate location and a second plasma sheath surface is defined next to the second surface, and the second plasma sheath surface follows an outline defined by the plurality of electrode openings of the second surface of the electrode.

3. The apparatus of claim 2, wherein the first plasma sheath surface has a first sheath surface area and the second plasma sheath surface has a second sheath surface area, and the second sheath surface area is larger than the first sheath surface area.

4. The apparatus of claim 1, wherein each one of the plurality of electrode openings is at least about 0.5 mm or greater in diameter and each one of the plurality of gas feed holes has a diameter of about 0.1 mm.

5. An electrode, comprising:

an electrode body having a first surface and a second surface, the second surface having a plurality of gas feed holes that are coupled to a corresponding plurality of electrode openings, each electrode opening having an electrode opening diameter that is greater than a gas feed hole diameter of each of the plurality of gas feed holes, the second surface being defined by inner surfaces of the plurality of electrode openings so that a surface area of the second surface is larger than a surface area of the electrode body without the plurality of electrode openings, the larger second surface area being capable of inducing an increased bias voltage at a substrate processing surface.

6. The electrode of claim 5, wherein a plasma is defined between the second surface of the electrode and a substrate surface, the substrate surface being disposed adjacent to the second surface of the electrode, and with the second surface of the electrode, defining a processing space in which the plasma is defined.

7. The electrode of claim 6, wherein a plasma sheath having a first sheath surface and a second sheath surface is defined in the processing space, the first sheath surface being defined next to the substrate surface and the second sheath surface being defined next to the second surface of the electrode, the second sheath surface following an outline defined by the plurality of electrode openings of the second surface of the electrode.

8. The electrode of claim 5, wherein each of the plurality of electrode openings is at least about 0.5 mm or greater in diameter and each of the plurality of gas feed holes has a diameter of about 0.1 mm.

9. An electrode, comprising:

an electrode body including,

a first surface; and

a second surface, the second surface having a plurality of gas feed holes, each one of the plurality of gas feed holes being integrally coupled to a corresponding electrode opening to comprise a plurality of electrode openings, each one of the plurality of electrode openings being larger than each one of the plurality of gas feed holes, the second surface defining a boundary of a plasma sheath, the plasma sheath having a first plasma sheath surface and a second plasma sheath surface, the second plasma sheath surface being at least partially within the plurality of electrode openings.

10. The electrode of claim 9, wherein the first plasma sheath surface is adjacent to a processing surface of a substrate, the first plasma sheath surface having a first plasma sheath surface area which is smaller than a second plasma sheath surface area of the second plasma sheath surface.

11. The electrode of claim 9, wherein when the second plasma sheath surface that is at least partially within the plurality of electrode openings causes an increase in bias voltage to be directed at an active surface of a substrate.

12. The electrode of claim 10, wherein the second plasma sheath surface area is about 2.7 times greater than the first plasma sheath surface area.

13. An electrode, comprising:

an electrode body having a process surface, the process surface having a plurality of gas feed holes, each gas feed hole being integrally coupled to a corresponding electrode opening, the electrode opening being larger than the gas feed hole, the process surface defining a plasma sheath having a surface that is at least partially within each electrode opening.

14. The electrode of claim 13, wherein each electrode opening is at least about 0.5 mm or greater in diameter and each gas feed hole has a diameter of about 0.1 mm, and wherein when a plasma is struck adjacent to the electrode, the plasma sheath shifts to be at least partially within each electrode opening.