US20040170142A1 - Method and apparatus for long code generation in synchronous, multi-chip rate systems - Google Patents
Method and apparatus for long code generation in synchronous, multi-chip rate systems Download PDFInfo
- Publication number
- US20040170142A1 US20040170142A1 US10/794,891 US79489104A US2004170142A1 US 20040170142 A1 US20040170142 A1 US 20040170142A1 US 79489104 A US79489104 A US 79489104A US 2004170142 A1 US2004170142 A1 US 2004170142A1
- Authority
- US
- United States
- Prior art keywords
- code sequence
- code
- long
- long code
- modulo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
- H04J13/10—Code generation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
- H04J13/0007—Code type
- H04J13/0022—PN, e.g. Kronecker
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70703—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation using multiple or variable rates
Definitions
- the present invention is related in general to cellular communication systems, and, more particularly, to an improved method and system for long code generation in synchronous, multi-chip rate systems.
- CDMA 2000 has a Spreading Rate 1, also known as 1 ⁇ , having a chip rate of 1.2288 Mcps, and a Spreading Rate 3, also known as 3 ⁇ , having a chip rate of 3.6864 Mcps.
- the long code generator in the 3 ⁇ system runs three times as fast as the long code generator in the 1 ⁇ system. This causes a problem when handing off from a 3 ⁇ system to a 1 ⁇ system, and vice versa. Due to the synchronous nature of the two systems, it is difficult to download the long code generator state of the new system to the user during handoff.
- FIG. 1 illustrates a block diagram of an exemplary apparatus in accordance with the present invention illustrating the extension of a 1 ⁇ chip rate to an Nx chip rate;
- FIG. 2 illustrates a block diagram of an alternate embodiment of an exemplary apparatus in accordance with the present invention illustrating the extension of a 1 ⁇ chip rate to an Nx chip rate;
- FIG. 3 illustrates a block diagram of an exemplary apparatus in accordance with the present invention illustrating an example of a long code generator for spreading rate 3;
- FIG. 4 illustrates a logical flowchart of the method for long code generation according to the method and system of the present invention.
- FIG. 1 illustrates a block diagram of an exemplary apparatus 100 in accordance with the present invention illustrating the extension of a 1 ⁇ chip rate to an Nx chip rate.
- encoder 102 is concatenated to the output 104 of code generator 106 .
- code generator 106 includes a long code generator comprising a PN sequence generator.
- PN sequence generator a sequence generator capable of generating a sequence of random bits may be used without departing from the spirit and scope of the present invention.
- both the long code generator 106 and the encoder 102 are operated at the same bit or chip rate, which in the preferred embodiment is the 1 ⁇ or reference chip rate (i.e. 1.2288 Mcps).
- Encoder 102 encodes code generator output 104 , and produces a plurality of component or code sequences 110 - 114 , which are received by multiplexor 108 .
- Multiplexor 108 multiplexes code sequences 110 - 114 and produces an output code sequence 116 .
- the architecture depicted in FIG. 1 provides the flexibility of extending the long code sequence from the 1 ⁇ chip rate to any future higher multiple and related chip rate.
- Multiplexer 108 has clock input 118 operating at Nx chip rate so that the output sequence 116 has the desired chip rate.
- FIG. 2 a block diagram of an alternate embodiment of an exemplary apparatus 200 in accordance with the present invention illustrating an example of a long code generator for spreading rate N is shown.
- An encoder 202 is concatenated with the output 204 of the long code generator 206 , which preferably is running at the 1 ⁇ chip rate.
- Encoder 202 encodes code generator output 204 , and produces a plurality of component or code sequences 205 , 215 , 225 , which are received by multiplexor 208 .
- first component sequence 205 is substantially similar to code generator output 204 , and is input to multiplexor 208 .
- first component sequence 205 may be a delayed version of code generator output 204 .
- Second component sequence 215 is a delayed version of code generator output 204 , wherein code generator output 204 is delayed by a predetermined amount at delay block 210 .
- Third component sequence 225 is also a delayed version of code generator output 204 , wherein code generator output 204 is delayed by a second predetermined amount at delay block 212 , wherein the first and second predetermined delays may or may not be the same.
- the long code for spreading rate N comprises N multiplexed component sequences 205 , 215 , 225 , etc., each having a chip rate of 1 ⁇ .
- Multiplexor 208 has clock input 218 operating at the Nx chip rate so that the output sequence 216 has the desired chip rate.
- FIG. 3 a block diagram of an exemplary apparatus 300 in accordance with the present invention illustrating an example of a long code generator for spreading rate 3 is shown.
- a code mask 305 which in the preferred embodiment is a long code mask, is input to code generator 306 .
- code generator 306 is preferably a long code generator.
- Long code mask 305 is applied over long code generator 306 to generate a specific mobile station's long code sequence.
- a systematic rate 1 ⁇ 3 convulational encoder 302 is concatenated with the output 304 of the long code generator 306 , which is running at the 1 ⁇ chip rate.
- Encoder 302 encodes code generator output 304 , and produces a plurality of component or code sequences 305 , 315 , 325 , which are received by multiplexor 308 .
- the long code for spreading rate 1 has a chip rate of 1 ⁇ or 1.2288 Mcps.
- the long code for spreading rate 3 comprises three multiplexed component sequences 305 , 315 , 325 , each having a chip rate of 1.2288 Mcps.
- the first component sequence 305 comprises the long code for spreading rate 1.
- the second component sequence 315 comprises the modulo-2 addition of the long code for spreading rate 1 and the long code for spreading rate 1 delayed by a predetermined amount, which in the preferred embodiment is ⁇ fraction (1/1.2288) ⁇ microseconds.
- the third component sequence 325 comprises the modulo-2 addition of the long code for spreading rate 1 and the long code for spreading rate 1 delayed by another predetermined amount, which in the preferred embodiment is ⁇ fraction (2/1.2288) ⁇ microseconds.
- code generator output 304 is a maximum length pseudo-noise sequence
- the second and third component sequences 315 , 325 are delayed or time-shifted versions of the first component sequence 305 .
- the delay may be produced via a shift register, a multiplier, etc. However, it should be noted that the length of the shift register may be prohibitive.
- the three component sequences 305 , 315 , and 325 are multiplexed by multiplexer 308 .
- Multiplexor 308 multiplexes code sequences 305 , 315 , 325 and produces an output code sequence 316 .
- multiplexer 308 runs at a chip rate three times that of spreading rate 1 (i.e. spreading rate 3) via clock input 318 . Therefore, the long code for spreading rate 3 will have a chip rate of 3.6864 Mcps.
- the three component sequences 305 , 315 , and 325 are multiplexed such that the long code value at the beginning of every ⁇ fraction (1/1.2288) ⁇ microsecond interval, starting from the beginning of the System Time, corresponds to the first component sequence.
- a 4 ⁇ long code sequence may be generated by multiplexing four 1 ⁇ sequences: the three sequences above and a fourth sequence generated by delaying the long code for spreading rate 1 by yet another predetermined amount, which in the preferred embodiment is three chips or ⁇ fraction (3/1.2288) ⁇ microseconds, and exclusive or'ing or performing a modulo-2 addition with spreading rate 1.
- the process begins at block 402 , wherein the step of synchronizing to the system long code is performed. Thereafter, as shown at block 404 , the step of performing the modulo-2 addition of the long code sequence for the 1 ⁇ system and the long code sequence for the 1 ⁇ system delayed by a predetermined amount is performed. Thereafter, as shown at block 406 , the step of performing the modulo-2 addition of the long code sequence for the 1 ⁇ system and the long code sequence for the 1 ⁇ system delayed by another predetermined amount is performed. Thereafter, as shown at block 408 , the step of multiplexing together the three long code sequences is performed, producing the 3 ⁇ long code sequence.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mobile Radio Communication Systems (AREA)
- Error Detection And Correction (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
A method and apparatus for long code generation in synchronous, multi-chip rate systems, wherein a first code sequence having a first bit rate, and a second code sequence having the first bit rate, the second code sequence being a time delay of the first code sequence, are multiplexed together, producing a desired long code.
Description
- The present invention is related in general to cellular communication systems, and, more particularly, to an improved method and system for long code generation in synchronous, multi-chip rate systems.
- In synchronous code division multiple access (CDMA) telecommunication systems, a long code generator is initialized by use of the forward link synchronization channel. The long code generator is used to separate users. For example, in the IS-95 system, each user gets a different time shift of the same pseudo noise (PN) sequence, which is the long code. When two synchronized systems are running at multiple and related chip rates, handoffs from one system to the other may be complicated because the state of the long code generator of the new system is not known. For example, CDMA 2000 has a
Spreading Rate 1, also known as 1×, having a chip rate of 1.2288 Mcps, and a Spreading Rate 3, also known as 3×, having a chip rate of 3.6864 Mcps. If the same long code generator is used in each system, the long code generator in the 3× system runs three times as fast as the long code generator in the 1× system. This causes a problem when handing off from a 3× system to a 1× system, and vice versa. Due to the synchronous nature of the two systems, it is difficult to download the long code generator state of the new system to the user during handoff. - In the example discussed above, it is optimum to have a 3× long code generator that is derived from the 1× long code generator. In this way, once the mobile station is accessing either system, it knows the long code generator state of the other system, and handoffs are simplified. Therefore, a need exists for an improved method and apparatus for long code generation in a synchronous, multi-chip rate system.
- The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
- FIG. 1 illustrates a block diagram of an exemplary apparatus in accordance with the present invention illustrating the extension of a 1× chip rate to an Nx chip rate;
- FIG. 2 illustrates a block diagram of an alternate embodiment of an exemplary apparatus in accordance with the present invention illustrating the extension of a 1× chip rate to an Nx chip rate;
- FIG. 3 illustrates a block diagram of an exemplary apparatus in accordance with the present invention illustrating an example of a long code generator for spreading rate 3; and
- FIG. 4 illustrates a logical flowchart of the method for long code generation according to the method and system of the present invention.
- Referring now to the figures, wherein like referenced numerals designate like components, FIG. 1 illustrates a block diagram of an
exemplary apparatus 100 in accordance with the present invention illustrating the extension of a 1× chip rate to an Nx chip rate. In accordance with FIG. 1,encoder 102 is concatenated to theoutput 104 ofcode generator 106. In the preferred embodiment,code generator 106 includes a long code generator comprising a PN sequence generator. However, it will be appreciated by those skilled in the art that any sequence generator capable of generating a sequence of random bits may be used without departing from the spirit and scope of the present invention. In the preferred embodiment, both thelong code generator 106 and theencoder 102 are operated at the same bit or chip rate, which in the preferred embodiment is the 1× or reference chip rate (i.e. 1.2288 Mcps).Encoder 102 encodescode generator output 104, and produces a plurality of component or code sequences 110-114, which are received bymultiplexor 108.Multiplexor 108 multiplexes code sequences 110-114 and produces anoutput code sequence 116. As will be appreciated by those skilled in art, the architecture depicted in FIG. 1 provides the flexibility of extending the long code sequence from the 1× chip rate to any future higher multiple and related chip rate.Multiplexer 108 hasclock input 118 operating at Nx chip rate so that theoutput sequence 116 has the desired chip rate. - Referring now to FIG. 2, a block diagram of an alternate embodiment of an
exemplary apparatus 200 in accordance with the present invention illustrating an example of a long code generator for spreading rate N is shown. Anencoder 202 is concatenated with theoutput 204 of thelong code generator 206, which preferably is running at the 1× chip rate.Encoder 202 encodescode generator output 204, and produces a plurality of component orcode sequences multiplexor 208. Preferably,first component sequence 205 is substantially similar tocode generator output 204, and is input tomultiplexor 208. However, those skilled in the art will appreciate thatfirst component sequence 205 may be a delayed version ofcode generator output 204.Second component sequence 215 is a delayed version ofcode generator output 204, whereincode generator output 204 is delayed by a predetermined amount atdelay block 210.Third component sequence 225 is also a delayed version ofcode generator output 204, whereincode generator output 204 is delayed by a second predetermined amount atdelay block 212, wherein the first and second predetermined delays may or may not be the same. As shown in FIG. 2, the long code for spreading rate N comprises N multiplexedcomponent sequences Multiplexor 208 hasclock input 218 operating at the Nx chip rate so that theoutput sequence 216 has the desired chip rate. - Referring now to FIG. 3, a block diagram of an
exemplary apparatus 300 in accordance with the present invention illustrating an example of a long code generator for spreading rate 3 is shown. Acode mask 305, which in the preferred embodiment is a long code mask, is input tocode generator 306. As described above,code generator 306 is preferably a long code generator.Long code mask 305 is applied overlong code generator 306 to generate a specific mobile station's long code sequence. A systematic rate ⅓convulational encoder 302 is concatenated with theoutput 304 of thelong code generator 306, which is running at the 1× chip rate.Encoder 302 encodescode generator output 304, and produces a plurality of component orcode sequences multiplexor 308. In cdma2000 or TIA IS-2000.2 Physical layer Standard for cdma2000 Spread Spectrum Systems, the long code for spreadingrate 1 has a chip rate of 1× or 1.2288 Mcps. As shown in FIG. 3, the long code for spreading rate 3 comprises three multiplexedcomponent sequences first component sequence 305 comprises the long code forspreading rate 1. Thesecond component sequence 315 comprises the modulo-2 addition of the long code for spreadingrate 1 and the long code for spreadingrate 1 delayed by a predetermined amount, which in the preferred embodiment is {fraction (1/1.2288)} microseconds. Thethird component sequence 325 comprises the modulo-2 addition of the long code for spreadingrate 1 and the long code for spreadingrate 1 delayed by another predetermined amount, which in the preferred embodiment is {fraction (2/1.2288)} microseconds. However, other predetermined amounts may be used and still fall within the scope of the present invention. Ifcode generator output 304 is a maximum length pseudo-noise sequence, the second andthird component sequences first component sequence 305. As will be appreciated by those skilled in the art, the delay may be produced via a shift register, a multiplier, etc. However, it should be noted that the length of the shift register may be prohibitive. The threecomponent sequences multiplexer 308.Multiplexor 308multiplexes code sequences output code sequence 316. In this example,multiplexer 308 runs at a chip rate three times that of spreading rate 1 (i.e. spreading rate 3) viaclock input 318. Therefore, the long code for spreading rate 3 will have a chip rate of 3.6864 Mcps. In the preferred embodiment, the threecomponent sequences - As will be appreciated by those skilled in the art, the procedure described above for spreading rate 3 can be extended to generate a long code sequence of any multiple length. For example, a 4× long code sequence may be generated by multiplexing four 1× sequences: the three sequences above and a fourth sequence generated by delaying the long code for spreading
rate 1 by yet another predetermined amount, which in the preferred embodiment is three chips or {fraction (3/1.2288)} microseconds, and exclusive or'ing or performing a modulo-2 addition withspreading rate 1. - With reference now to FIG. 4, there is depicted a logical flowchart of the
process 400 of long code generation according to the method and system of the present invention. As shown, the process begins atblock 402, wherein the step of synchronizing to the system long code is performed. Thereafter, as shown atblock 404, the step of performing the modulo-2 addition of the long code sequence for the 1× system and the long code sequence for the 1× system delayed by a predetermined amount is performed. Thereafter, as shown atblock 406, the step of performing the modulo-2 addition of the long code sequence for the 1× system and the long code sequence for the 1× system delayed by another predetermined amount is performed. Thereafter, as shown atblock 408, the step of multiplexing together the three long code sequences is performed, producing the 3× long code sequence. - The foregoing description of a preferred embodiment of the invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiment was chosen and described to provide the best illustration of the principles of the invention and its practical application, and to enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
Claims (13)
1. A method for code generation in synchronous, multi-chip rate communication systems, comprising the steps of:
producing a first code sequence having a first bit rate;
producing a second code sequence having the first bit rate, the second code sequence being a time delay of the first code sequence; and
multiplexing the first code sequence and the second code sequence and producing an output code sequence having a desired bit rate.
2. A method for code generation as recited in claim 1 , wherein the step of producing the second code sequence comprises the step of performing modulo-2 addition of the first code sequence and a delayed version of the first code sequence.
3. A method for code generation as recited in claim 1 , including the step of producing a third code sequence having the first bit rate, the third code sequence being a time delay of the first code sequence, wherein the step of multiplexing includes multiplexing the third code sequence.
4. A method for code generation as recited in claim 3 , wherein the step of producing the second code sequence comprises the step of performing modulo-2 addition of the first code sequence and a delayed version of the first code sequence, and wherein the step of producing the third code sequence comprises the step of performing modulo-2 addition of the first code sequence and a second delayed version of the first code sequence.
5. A method for long code generation in synchronous, multi-chip rate communication systems, comprising the steps of:
producing a first long code sequence having a first bit rate;
producing a second long code sequence having the first bit rate, the second long code sequence being a time delay of the first code sequence;
producing a third long code sequence having the first bit rate, the third long code sequence being a time delay of the first long code sequence; and
multiplexing the first long code sequence, the second long code sequence, and the third long code sequence, and producing an output code sequence having a desired bit rate.
6. A method for long code generation as recited in claim 5 , wherein the step of producing the second long code sequence comprises the step of performing modulo-2 addition of the first code sequence and a delayed version of the first code sequence, and wherein the step of producing the third code sequence comprises the step of performing modulo-2 addition of the first code sequence and a second delayed version of the first code sequence.
7. An apparatus for code generation in synchronous, multichip rate systems, comprising:
a code generator adapted to produce a first code sequence having a first bit rate;
an encoder coupled to the code generator and adapted to receive the first code sequence, the encoder adapted to produce a second code sequence having the first bit rate, and
a multiplexor coupled to the encoder, the multiplexer adapted to receive the first code sequence and the second code sequence, the multiplexor further adapted to produce an output code sequence having a desired bit rate.
8. An apparatus for code generation as recited in claim 7 , wherein the encoder comprises
a delay block coupled to the first code sequence, the delay block adapted to produce a delayed first code sequence having a predetermined delay time; and
a modulo-2 addition block coupled to the delay block and to the multiplexor, the modulo-2 addition block adapted to perform modulo-2 addition of the first code sequence and the time delayed first code sequence.
9. An apparatus for code generation as recited in claim 7 , wherein the encoder is further adapted to produce a third code sequence having the first bit rate, the third code sequence being a time delay of the first code sequence, wherein the multiplexor is adapted to receive the third code sequence.
10. An apparatus for code generation as recited in claim 8 , wherein the encoder comprises
a second delay block coupled to the first code sequence, the second delay block adapted to produce a second delayed first code sequence having a second predetermined delay time; and
a second modulo-2 addition block coupled to the second delay block and to the multiplexor, the second modulo-2 addition block adapted to perform modulo-2 addition of the first code sequence and the second delayed first code sequence.
11. An apparatus for long code generation in synchronous, multi-chip rate communication systems, comprising:
a long code generator adapted to produce a first long code sequence having a first bit rate;
a convolutional encoder coupled to the long code generator and adapted to receive the first long code sequence, the convolutional encoder adapted to produce a second long code sequence having the first bit rate, the convolutional encoder further adapted to produce a third long code sequence having the first bit rate; and
a multiplexor coupled to the convolutional encoder, the multiplexor adapted to receive the first long code sequence, the second long code sequence, and the third long code sequence, the multiplexor further adapted to produce an output long code sequence having a desired bit rate.
12. An apparatus for long code generation as recited in claim 11 , wherein the convolutional encoder comprises
a first delay block coupled to the first code sequence, the first delay block adapted to produce a delayed first code sequence having a predetermined delay time; and
a first modulo-2 addition block coupled to the first delay block, the first modulo-2 addition block adapted to perform modulo-2 addition of the first code sequence and the delayed first code sequence.
13. An apparatus for long code generation as recited in claim 12 , wherein the convolutional encoder further comprises
a second delay block coupled to the first code sequence, the second delay block adapted to produce a second delayed first code sequence having a second predetermined delay time; and
a second modulo-2 addition block coupled to the second delay block and to the multiplexor, the second modulo-2 addition block adapted to perform modulo-2 addition of the first code sequence and the second delayed first code sequence;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/794,891 US20040170142A1 (en) | 2000-03-16 | 2004-03-04 | Method and apparatus for long code generation in synchronous, multi-chip rate systems |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/526,643 US6724778B1 (en) | 2000-03-16 | 2000-03-16 | Method and apparatus for long code generation in synchronous, multi-chip rate systems |
US10/794,891 US20040170142A1 (en) | 2000-03-16 | 2004-03-04 | Method and apparatus for long code generation in synchronous, multi-chip rate systems |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/526,643 Division US6724778B1 (en) | 2000-03-16 | 2000-03-16 | Method and apparatus for long code generation in synchronous, multi-chip rate systems |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040170142A1 true US20040170142A1 (en) | 2004-09-02 |
Family
ID=24098156
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/526,643 Expired - Fee Related US6724778B1 (en) | 2000-03-16 | 2000-03-16 | Method and apparatus for long code generation in synchronous, multi-chip rate systems |
US10/794,891 Abandoned US20040170142A1 (en) | 2000-03-16 | 2004-03-04 | Method and apparatus for long code generation in synchronous, multi-chip rate systems |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/526,643 Expired - Fee Related US6724778B1 (en) | 2000-03-16 | 2000-03-16 | Method and apparatus for long code generation in synchronous, multi-chip rate systems |
Country Status (8)
Country | Link |
---|---|
US (2) | US6724778B1 (en) |
EP (1) | EP1183807A4 (en) |
JP (1) | JP2003528537A (en) |
KR (1) | KR20020031101A (en) |
CN (1) | CN1364359A (en) |
AU (1) | AU2001249159A1 (en) |
CA (1) | CA2373469A1 (en) |
WO (1) | WO2001071956A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030078611A1 (en) * | 2001-05-17 | 2003-04-24 | Kiyoshi Hashiba | Intragastric device for treating obesity |
US20050113082A1 (en) * | 2003-11-24 | 2005-05-26 | Bender Paul E. | Access terminal identification management |
US20070237116A1 (en) * | 2006-04-07 | 2007-10-11 | Mark Kent | Method and apparatus for efficient gold code generation and management in WCDMA systems |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100424538B1 (en) * | 2001-05-29 | 2004-03-27 | 엘지전자 주식회사 | Method for producing scrambling code and apparatus thereof in mobile system |
US7099299B2 (en) * | 2002-03-04 | 2006-08-29 | Agency For Science, Technology And Research | CDMA system with frequency domain equalization |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216693A (en) * | 1990-11-13 | 1993-06-01 | Ricoh Company, Ltd. | Spread spectrum communications system |
US5790891A (en) * | 1996-01-11 | 1998-08-04 | Galileo Technology Ltd. | Synchronizing unit having two registers serially connected to one clocked elements and a latch unit for alternately activating the registers in accordance to clock signals |
US5796776A (en) * | 1995-06-30 | 1998-08-18 | Interdigital Technology Corporation | Code sequence generator in a CDMA modem |
US5878075A (en) * | 1996-07-26 | 1999-03-02 | Motorola, Inc. | Method of and apparatus for generating a pseudorandom noise sequence |
US6055264A (en) * | 1997-08-01 | 2000-04-25 | Nokia Mobile Phones Limited | Method and apparatus for fast acquisition and multipath search in a spread spectrum system |
US6324205B1 (en) * | 1999-05-10 | 2001-11-27 | Sony Corporation | Scalable method for generating long codes using gold sequences |
US6389138B1 (en) * | 1998-11-12 | 2002-05-14 | Lucent Technologies Inc. | Method and apparatus for generating a complex scrambling code sequence |
US6512753B1 (en) * | 1998-12-29 | 2003-01-28 | Samsung Electronics, Co., Ltd. | Device and method for spreading channels in mobile communication system |
US6643280B1 (en) * | 1999-10-27 | 2003-11-04 | Lucent Technologies Inc. | Method and apparatus for generation of CDMA long codes |
US6980539B2 (en) * | 2000-11-06 | 2005-12-27 | Ntt Docomo, Inc. | Mobile communication system in multi-carrier CDMA scheme using short code and long code |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5727064A (en) * | 1995-07-03 | 1998-03-10 | Lucent Technologies Inc. | Cryptographic system for wireless communications |
-
2000
- 2000-03-16 US US09/526,643 patent/US6724778B1/en not_active Expired - Fee Related
-
2001
- 2001-03-12 JP JP2001570006A patent/JP2003528537A/en active Pending
- 2001-03-12 KR KR1020017014573A patent/KR20020031101A/en not_active Application Discontinuation
- 2001-03-12 AU AU2001249159A patent/AU2001249159A1/en not_active Abandoned
- 2001-03-12 CN CN01800547A patent/CN1364359A/en active Pending
- 2001-03-12 EP EP01922344A patent/EP1183807A4/en not_active Withdrawn
- 2001-03-12 CA CA002373469A patent/CA2373469A1/en not_active Abandoned
- 2001-03-12 WO PCT/US2001/007856 patent/WO2001071956A1/en not_active Application Discontinuation
-
2004
- 2004-03-04 US US10/794,891 patent/US20040170142A1/en not_active Abandoned
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216693A (en) * | 1990-11-13 | 1993-06-01 | Ricoh Company, Ltd. | Spread spectrum communications system |
US5796776A (en) * | 1995-06-30 | 1998-08-18 | Interdigital Technology Corporation | Code sequence generator in a CDMA modem |
US5790891A (en) * | 1996-01-11 | 1998-08-04 | Galileo Technology Ltd. | Synchronizing unit having two registers serially connected to one clocked elements and a latch unit for alternately activating the registers in accordance to clock signals |
US5878075A (en) * | 1996-07-26 | 1999-03-02 | Motorola, Inc. | Method of and apparatus for generating a pseudorandom noise sequence |
US6055264A (en) * | 1997-08-01 | 2000-04-25 | Nokia Mobile Phones Limited | Method and apparatus for fast acquisition and multipath search in a spread spectrum system |
US6389138B1 (en) * | 1998-11-12 | 2002-05-14 | Lucent Technologies Inc. | Method and apparatus for generating a complex scrambling code sequence |
US6512753B1 (en) * | 1998-12-29 | 2003-01-28 | Samsung Electronics, Co., Ltd. | Device and method for spreading channels in mobile communication system |
US6324205B1 (en) * | 1999-05-10 | 2001-11-27 | Sony Corporation | Scalable method for generating long codes using gold sequences |
US6643280B1 (en) * | 1999-10-27 | 2003-11-04 | Lucent Technologies Inc. | Method and apparatus for generation of CDMA long codes |
US6980539B2 (en) * | 2000-11-06 | 2005-12-27 | Ntt Docomo, Inc. | Mobile communication system in multi-carrier CDMA scheme using short code and long code |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030078611A1 (en) * | 2001-05-17 | 2003-04-24 | Kiyoshi Hashiba | Intragastric device for treating obesity |
US20050113082A1 (en) * | 2003-11-24 | 2005-05-26 | Bender Paul E. | Access terminal identification management |
US7130626B2 (en) * | 2003-11-24 | 2006-10-31 | Qualcomm, Inc. | Access terminal identification management |
US20070237116A1 (en) * | 2006-04-07 | 2007-10-11 | Mark Kent | Method and apparatus for efficient gold code generation and management in WCDMA systems |
Also Published As
Publication number | Publication date |
---|---|
US6724778B1 (en) | 2004-04-20 |
KR20020031101A (en) | 2002-04-26 |
CN1364359A (en) | 2002-08-14 |
AU2001249159A1 (en) | 2001-10-03 |
EP1183807A4 (en) | 2004-09-29 |
CA2373469A1 (en) | 2001-09-27 |
WO2001071956A1 (en) | 2001-09-27 |
JP2003528537A (en) | 2003-09-24 |
EP1183807A1 (en) | 2002-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100420404B1 (en) | Spreading code generator for code division multiple access communication and code division multiple access communication system using the same | |
JP3616014B2 (en) | Apparatus and method for generating and verifying frame synchronization word in asynchronous code division multiple access communication system | |
KR100827140B1 (en) | Apparatus for generating reception/transmission reference timing in mobile communication terminal and method thereof | |
JP2004502324A (en) | Apparatus and method for synchronization of uplink synchronous transmission scheme in code division multiple access communication system | |
WO2001043315A1 (en) | Method and apparatus for implementing pn masks for a truncated m-sequence | |
JPH11150523A (en) | Spectrum diffusion transmission device/spectrum diffusion reception device and spectrum diffusion communication system | |
JP3029819B2 (en) | Code division multiple access (CDMA) band spreading apparatus and method | |
AU767511B2 (en) | Apparatus and method for spreading channel data in CDMA communication system using orthogonal transmit diversity | |
US6766337B1 (en) | Apparatus and method for generating spreading code in CDMA communication system | |
US6724778B1 (en) | Method and apparatus for long code generation in synchronous, multi-chip rate systems | |
KR100768979B1 (en) | A method and apparatus for generating multiple bits of a pseudonoise sequence with each clock pulse by computing the bits in parallel | |
US6643280B1 (en) | Method and apparatus for generation of CDMA long codes | |
CA2551565C (en) | Cdma integrated circuit demodulator with build-in test pattern generation | |
JPH10190524A (en) | Code generator and spread communication system | |
JPH07107006A (en) | Method and device for generating spreading code | |
JP2688686B2 (en) | CDMA random access communication method and mobile station apparatus using the same | |
KR100257808B1 (en) | Method for asynchronizing base station of wide band cdma system using short period extended gold code | |
KR100629680B1 (en) | Apparatus and method for off-line cell search in asynchronous CDMA communication system | |
JPH11313008A (en) | Diffusion code generating device | |
Galluzzo et al. | CODE GENERATION FOR WIDEBAND CDMA | |
KR19990017716A (en) | Broadband data transmission method and device | |
KR20000077063A (en) | Apparatus and method for generating spreading code in cdma communication system | |
JP2001053647A (en) | Synchronism acquisition device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MOTOROLA, INC., ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LAIRD, KEVIN MICHAEL;CHEN, JIANGNAN;ZHOU, FRANK FEI;REEL/FRAME:021767/0482;SIGNING DATES FROM 20000622 TO 20000714 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GOOGLE TECHNOLOGY HOLDINGS LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA MOBILITY LLC;REEL/FRAME:035464/0012 Effective date: 20141028 |