US20040159908A1 - Silicon-on-insulator wafer for RF integrated circuit - Google Patents
Silicon-on-insulator wafer for RF integrated circuit Download PDFInfo
- Publication number
- US20040159908A1 US20040159908A1 US10/764,938 US76493804A US2004159908A1 US 20040159908 A1 US20040159908 A1 US 20040159908A1 US 76493804 A US76493804 A US 76493804A US 2004159908 A1 US2004159908 A1 US 2004159908A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- silicon
- layer
- oxide layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/012—Bonding, e.g. electrostatic for strain gauges
Definitions
- the present invention relates to silicon-on-insulator (SOI) wafers for RF integrated circuits.
- SOI silicon-on-insulator
- Losses and coupling (cross-talk) in RF applications may be reduced by using high resistivity silicon (HRS) substrates.
- HRS high resistivity silicon
- Such substrates have maximum resistivities ⁇ of 10 4 ⁇ -cm as compared to a resistivity ⁇ of about 10 ⁇ -cm for the silicon substrate typically used.
- the resistivity of HRS is 3-4 orders of magnitude lower than a GaAs substrate commonly used for RF applications.
- there is a problem with using high resistivity silicon substrates in RF applications that is, during post-processing, thermally generated donors degrade the resistivity both at the SiO 2 /Si interface and at the back of the wafer, as shown by the graphs in FIGS. 1 and 2.
- FIG. 1 is a resistance profile at the interface between the buried oxide and the substrate (i.e., the SiO 2 /Si interface) where the substrate is assumed to be an n-type substrate.
- FIG. 2 is a resistance profile across a p-type wafer.
- the y-axis of FIG. 2 represents resistivity, and the x-axis represents depth into the wafer.
- the back of the wafer under certain conditions, may actually undergo a conversion in type (in this case, from p type to n type). It has also been observed that, under other conditions, the region of the wafer just below the buried oxide may also undergo a conversion in type.
- the degradation at the back of the wafer may be removed by grinding.
- the degradation at the interface produces higher losses, increases coupling (cross-talk), lowers inductor Q, and is not so easily remedied.
- the present invention solves one or more of these problems
- an RF semiconductor device comprises a high resistivity polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the buried oxide layer.
- an RF semiconductor device comprises a high resistivity polycrystalline layer, a buried oxide layer over the polycrystalline layer, and a silicon layer over the buried oxide layer.
- a method of fabricating an RF semiconductor device comprises the following: forming an oxide layer on a surface of a first wafer, wherein the first wafer comprises low resistivity silicon; and, bonding the oxide layer of the first wafer to a second wafer, wherein the second wafer comprises a high resistivity polysilicon wafer, whereby the RF semiconductor device is produced.
- a method of fabricating an RF semiconductor device comprises the following: forming a first oxide layer on a surface of a first wafer, wherein the first wafer comprises a high resistivity polycrystalline material; forming a second oxide layer on a surface of a second wafer, wherein the second wafer comprises low resistivity silicon; and, bonding the first and second oxide layers against one another so as to produce the RF semiconductor device.
- a method is provided to fabricate an RF semiconductor device starting with a SOI wafer having a top silicon layer, a buried oxide layer, and a bottom silicon layer.
- the method comprises the following: forming a new oxide layer on a surface of the top silicon layer; forming a high resistivity polysilicon layer over the new oxide layer; removing the bottom silicon layer of the SOI wafer; and, removing the buried oxide layer of the SOI wafer so as to produce the RF semiconductor device.
- FIG. 1 illustrates is a resistance profile at the interface between the buried oxide and the substrate of a conventional Silicon-on-Insulator wafer
- FIG. 2 illustrates a resistance profile across a conventional p-type wafer following standard CMOS processing
- FIG. 3 illustrates an RF device that advantageously uses the present invention
- FIG. 4 shows a wafer according to the present invention which may be used in the RF device of FIG. 3;
- FIGS. 5 a , 5 b , and 5 c illustrate a process of preparing the RF substrate 20 illustrated in FIG. 4;
- FIGS. 6 a , 6 b , and 6 c illustrate an alternative process of preparing the RF substrate 20 illustrated in FIG. 4;
- FIGS. 7 a , 7 b , 7 c , 7 d , and 7 e illustrate a further alternative process of preparing the RF substrate 20 illustrated in FIG. 4.
- an RF device 10 incorporates an integrated circuit 12 and has an RF input 14 and an output 16 .
- An RF substrate 20 that may be used during the fabrication of the integrated circuit 12 is shown in FIG. 4.
- the RF substrate 20 includes a high resistivity polysilicon handle wafer 22 , a buried oxide layer 24 formed over the polysilicon handle wafer 22 , and a silicon layer 26 formed over the buried oxide layer 24 .
- the silicon layer 26 of the RF substrate 20 may be then processed to form RF components, such as transistors, capacitors, diodes, varactors, and inductors, incorporated to form the RF device 10 .
- the buried oxide layer 24 may be SiO 2 or Al 2 O 3 . Alternatively, a layer of AlN or Si 3 N 4 may be substituted for the buried oxide layer 24 .
- An additional layer 28 may be provided to control stress and also to reduce any warping of the RF substrate 20 and to act as a barrier layer against contamination impurities. The additional layer 28 may be provided, for example, by oxidizing the polysilicon of the polysilicon handle wafer 22 or by depositing Si 3 N 4 on the polysilicon handle wafer 22 .
- the polysilicon of the polysilicon handle wafer 22 has a high resistivity ⁇ such as a resistivity ⁇ greater than 10 6 ⁇ -cm. Also, polysilicon is less susceptible to the degradation, such as type conversion, that occurs with the single crystal materials heretofore used. Moreover, high resistivity polysilicon suffers less loss of resistivity during processing.
- FIGS. 5 a , 5 b , and 5 c A process of preparing the RF substrate 20 is illustrated in FIGS. 5 a , 5 b , and 5 c .
- an oxide layer 30 is formed on a surface of a first wafer 32 of single crystal silicon. This oxide layer should have the desired thickness of the buried oxide layer 24 .
- low atomic weight atoms 34 such as hydrogen or helium atoms, may be implanted in a surface of a polycrystalline wafer 36 , where the material of the polysilicon wafer 36 .
- FIG. 5 a an oxide layer 30 is formed on a surface of a first wafer 32 of single crystal silicon. This oxide layer should have the desired thickness of the buried oxide layer 24 .
- low atomic weight atoms 34 such as hydrogen or helium atoms, may be implanted in a surface of a polycrystalline wafer 36 , where the material of the polysilicon wafer 36 .
- FIG. 1 A process of preparing the
- the oxidized layer 30 of the first wafer 32 and the implanted surface of the second wafer 36 are bonded against one another, such as by use of a heat treatment.
- the implanted atoms form macrobubbles, and the silicon film above the implanted region is typically released.
- the resulting structure is the RF substrate 20 which may be polished as needed.
- the additional layer 28 can be added as desired.
- the RF substrate 20 may be prepared by oxidizing a surface of a first wafer 40 of a polycrystalline material, such as polysilicon, to form an oxide layer 42 (FIG. 6 a ).
- a surface of a second wafer 44 comprising single crystal silicon is oxidized to form an oxide layer 46 .
- the oxidized layers 42 and 46 of the first and second wafers 40 and 44 are bonded together such as by use of a heat treatment. The combined depth of the oxide layers 42 and 46 should result in the desired thickness of the buried oxide layer 24 .
- a portion of the exposed silicon surface of the second wafer 44 is removed such as by grinding and/or etching to produce the desired RF substrate 20 having a top silicon layer of a desired depth. If etching is used, a doped layer may be used in the single crystal wafer before bonding to stop the etching at a desired point. The additional layer 28 can be added as desired.
- the RF substrate 20 can be fabricated by starting with a standard SOI wafer 50 having a top silicon layer 52 , a buried oxide layer 54 , and a thick bottom silicon layer 56 (FIG. 7 a ).
- a standard SOI wafer 50 having a top silicon layer 52 , a buried oxide layer 54 , and a thick bottom silicon layer 56 (FIG. 7 a ).
- the top silicon layer 52 of the SOI wafer 50 is oxidized to form an oxide layer 58 .
- a polysilicon layer 60 is formed over the oxide layer 58 such as by deposition.
- the resulting polysilicon layer may have a thickness, for example, of 500 ⁇ m for a wafer of 4 inches.
- the thick bottom silicon layer 56 of the original SOI wafer 50 is removed, such as by etching and/or grinding.
- the oxide layer 54 of the original SOI wafer 50 is removed, such as by etching and/or grinding, leaving the RF substrate 20 .
- the additional layer 28 can be added as desired.
- the buried oxide layers 24 and 54 described herein may be comprised of one or a combination of such dielectrics as SiO 2 , Si 3 N 4 , Al 2 O 3 , AlN, titanates, etc.
- the buried oxide can be deposited using such deposition techniques as CVD, LPCVD, sputtering, MBE, PECVD, high density plasma and thermal growth.
- the other oxide layers can be selected from one or a combination of such dielectrics as SiO 2 , Si 3 N 4 , Al 2 O 3 , AlN, titanates, etc. These other oxide layers can be deposited using such deposition techniques as CVD, LPCVD, sputtering, MBE, PECVD, high density plasma and thermal growth.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
An RF semiconductor device is fabricated from a starting substrate comprising a polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the oxide layer.
Description
- The present invention relates to silicon-on-insulator (SOI) wafers for RF integrated circuits.
- The material requirements for the initial processing of the silicon used in a particular application are driven by that application. For RF applications, these material requirements are very stringent. Standard bulk silicon wafers or silicon-on-insulator wafers use low resistivity substrates that result in high losses and cross-talk at high frequencies. For example, the Q's of inductors fabricated using silicon wafers or silicon-on-insulator wafers having low resistivity substrates are low. Therefore, multi-level metals with a ground plane are used in order to achieve higher Q's. However, these coupling techniques result in cross-talk. In addition, losses increase at higher frequencies due to the low resistivity of the substrates.
- Losses and coupling (cross-talk) in RF applications may be reduced by using high resistivity silicon (HRS) substrates. Such substrates have maximum resistivities ρ of 104 Ω-cm as compared to a resistivity ρ of about 10 Ω-cm for the silicon substrate typically used. However, the resistivity of HRS is 3-4 orders of magnitude lower than a GaAs substrate commonly used for RF applications. In addition, there is a problem with using high resistivity silicon substrates in RF applications. That is, during post-processing, thermally generated donors degrade the resistivity both at the SiO2/Si interface and at the back of the wafer, as shown by the graphs in FIGS. 1 and 2.
- FIG. 1 is a resistance profile at the interface between the buried oxide and the substrate (i.e., the SiO2/Si interface) where the substrate is assumed to be an n-type substrate. The y-axis of FIG. 1 represents resistivity, and the x-axis represents depth into the substrate. The point at which x=0 is at the interface. As shown in FIG. 1, the resistivity of the substrate is lowest just below the interface.
- FIG. 2 is a resistance profile across a p-type wafer. The y-axis of FIG. 2 represents resistivity, and the x-axis represents depth into the wafer. The point at which x=0 is at the front surface of the wafer. As shown in FIG. 2, the back of the wafer, under certain conditions, may actually undergo a conversion in type (in this case, from p type to n type). It has also been observed that, under other conditions, the region of the wafer just below the buried oxide may also undergo a conversion in type.
- The degradation at the back of the wafer may be removed by grinding. However, the degradation at the interface produces higher losses, increases coupling (cross-talk), lowers inductor Q, and is not so easily remedied. The present invention solves one or more of these problems
- In accordance with one aspect of the present invention, an RF semiconductor device comprises a high resistivity polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the buried oxide layer.
- In accordance with another aspect of the present invention, an RF semiconductor device comprises a high resistivity polycrystalline layer, a buried oxide layer over the polycrystalline layer, and a silicon layer over the buried oxide layer.
- In accordance with still another aspect of the present invention, a method of fabricating an RF semiconductor device comprises the following: forming an oxide layer on a surface of a first wafer, wherein the first wafer comprises low resistivity silicon; and, bonding the oxide layer of the first wafer to a second wafer, wherein the second wafer comprises a high resistivity polysilicon wafer, whereby the RF semiconductor device is produced.
- In accordance with yet another aspect of the present invention, a method of fabricating an RF semiconductor device comprises the following: forming a first oxide layer on a surface of a first wafer, wherein the first wafer comprises a high resistivity polycrystalline material; forming a second oxide layer on a surface of a second wafer, wherein the second wafer comprises low resistivity silicon; and, bonding the first and second oxide layers against one another so as to produce the RF semiconductor device.
- In accordance with a further aspect of the present invention, a method is provided to fabricate an RF semiconductor device starting with a SOI wafer having a top silicon layer, a buried oxide layer, and a bottom silicon layer. The method comprises the following: forming a new oxide layer on a surface of the top silicon layer; forming a high resistivity polysilicon layer over the new oxide layer; removing the bottom silicon layer of the SOI wafer; and, removing the buried oxide layer of the SOI wafer so as to produce the RF semiconductor device.
- These and other features and advantages of the present invention will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:
- FIG. 1 illustrates is a resistance profile at the interface between the buried oxide and the substrate of a conventional Silicon-on-Insulator wafer;
- FIG. 2 illustrates a resistance profile across a conventional p-type wafer following standard CMOS processing;
- FIG. 3 illustrates an RF device that advantageously uses the present invention;
- FIG. 4 shows a wafer according to the present invention which may be used in the RF device of FIG. 3;
- FIGS. 5a, 5 b, and 5 c illustrate a process of preparing the
RF substrate 20 illustrated in FIG. 4; - FIGS. 6a, 6 b, and 6 c illustrate an alternative process of preparing the
RF substrate 20 illustrated in FIG. 4; and, - FIGS. 7a, 7 b, 7 c, 7 d, and 7 e illustrate a further alternative process of preparing the
RF substrate 20 illustrated in FIG. 4. - As shown in FIG. 3, an
RF device 10 incorporates anintegrated circuit 12 and has anRF input 14 and anoutput 16. AnRF substrate 20 that may be used during the fabrication of the integratedcircuit 12 is shown in FIG. 4. TheRF substrate 20 includes a high resistivitypolysilicon handle wafer 22, a buriedoxide layer 24 formed over thepolysilicon handle wafer 22, and asilicon layer 26 formed over the buriedoxide layer 24. Thesilicon layer 26 of theRF substrate 20 may be then processed to form RF components, such as transistors, capacitors, diodes, varactors, and inductors, incorporated to form theRF device 10. - The buried
oxide layer 24 may be SiO2 or Al2O3. Alternatively, a layer of AlN or Si3N4 may be substituted for the buriedoxide layer 24. Anadditional layer 28 may be provided to control stress and also to reduce any warping of theRF substrate 20 and to act as a barrier layer against contamination impurities. Theadditional layer 28 may be provided, for example, by oxidizing the polysilicon of thepolysilicon handle wafer 22 or by depositing Si3N4 on thepolysilicon handle wafer 22. - The polysilicon of the
polysilicon handle wafer 22 has a high resistivity ρ such as a resistivity ρ greater than 106 Ω-cm. Also, polysilicon is less susceptible to the degradation, such as type conversion, that occurs with the single crystal materials heretofore used. Moreover, high resistivity polysilicon suffers less loss of resistivity during processing. - A process of preparing the
RF substrate 20 is illustrated in FIGS. 5a, 5 b, and 5 c. As shown in FIG. 5a, anoxide layer 30 is formed on a surface of afirst wafer 32 of single crystal silicon. This oxide layer should have the desired thickness of the buriedoxide layer 24. As shown in FIG. 5b, lowatomic weight atoms 34, such as hydrogen or helium atoms, may be implanted in a surface of apolycrystalline wafer 36, where the material of the polysilicon wafer 36. As shown in FIG. 5c, the oxidizedlayer 30 of thefirst wafer 32 and the implanted surface of thesecond wafer 36 are bonded against one another, such as by use of a heat treatment. During heating, the implanted atoms form macrobubbles, and the silicon film above the implanted region is typically released. The resulting structure is theRF substrate 20 which may be polished as needed. Theadditional layer 28 can be added as desired. - Alternatively, as illustrated in FIGS. 6a, 6 b, and 6 c, the
RF substrate 20 may be prepared by oxidizing a surface of afirst wafer 40 of a polycrystalline material, such as polysilicon, to form an oxide layer 42 (FIG. 6a). As shown in FIG. 6b, a surface of asecond wafer 44 comprising single crystal silicon is oxidized to form anoxide layer 46. As shown in FIG. 6c, theoxidized layers second wafers oxide layer 24. If necessary, a portion of the exposed silicon surface of thesecond wafer 44 is removed such as by grinding and/or etching to produce the desiredRF substrate 20 having a top silicon layer of a desired depth. If etching is used, a doped layer may be used in the single crystal wafer before bonding to stop the etching at a desired point. Theadditional layer 28 can be added as desired. - As a further alternative illustrated in FIGS. 7a, 7 b, 7 c, 7 d, and 7 e, the
RF substrate 20 can be fabricated by starting with astandard SOI wafer 50 having atop silicon layer 52, a buriedoxide layer 54, and a thick bottom silicon layer 56 (FIG. 7a). As shown in FIG. 7b, thetop silicon layer 52 of theSOI wafer 50 is oxidized to form anoxide layer 58. As shown in FIG. 7c, apolysilicon layer 60 is formed over theoxide layer 58 such as by deposition. The resulting polysilicon layer may have a thickness, for example, of 500 μm for a wafer of 4 inches. As shown in FIG. 7d, the thickbottom silicon layer 56 of theoriginal SOI wafer 50 is removed, such as by etching and/or grinding. Finally, as shown in FIG. 7e, theoxide layer 54 of theoriginal SOI wafer 50 is removed, such as by etching and/or grinding, leaving theRF substrate 20. Theadditional layer 28 can be added as desired. - Certain modifications of the present invention have been discussed above. Other modifications will occur to those practicing in the art of the present invention. For example, the buried
oxide layers - Moreover, the other oxide layers can be selected from one or a combination of such dielectrics as SiO2, Si3N4, Al2O3, AlN, titanates, etc. These other oxide layers can be deposited using such deposition techniques as CVD, LPCVD, sputtering, MBE, PECVD, high density plasma and thermal growth.
- Accordingly, the description of the present invention is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which are within the scope of the appended claims is reserved.
Claims (31)
1. An RF semiconductor device comprising:
a high resistivity polysilicon handle wafer;
a buried oxide layer over the polysilicon handle wafer; and,
a silicon layer over the buried oxide layer.
2. The RF semiconductor device of claim 2 further comprising an RF input.
3. An RF semiconductor device comprising:
a high resistivity polycrystalline layer;
a buried oxide layer over the polycrystalline layer; and,
a silicon layer over the buried oxide layer.
4. The RF semiconductor device of claim 3 wherein the polycrystalline layer comprises a polysilicon layer.
5. The RF semiconductor device of claim 3 further comprising an RF input.
6. The RF semiconductor device of claim 5 wherein the polycrystalline layer comprises a polysilicon layer.
7. A method of fabricating an RF semiconductor device comprising:
forming an oxide layer on a surface of a first wafer, wherein the first wafer comprises low resistivity silicon; and,
bonding the oxide layer of the first wafer to a second wafer, wherein the second wafer comprises a high resistivity polysilicon wafer, whereby the RF semiconductor device is produced.
8. The method of claim 7 wherein the bonding of the oxide layer of the first wafer to the second wafer comprises:
implanting low atomic weight atoms in a surface of the second wafer; and,
bonding the oxide layer of the first wafer to the implanted surface of the second wafer.
9. The method of claim 7 wherein the bonding of the oxide layer of the first wafer to the second wafer comprises heating the first and second wafers so as to bond the oxide layer of the first wafer to the second wafer.
10. The method of claim 9 wherein the heating of the first and second wafers so as to bond the oxide layer of the first wafer to the second wafer comprises:
implanting low atomic weight atoms in a surface of the second wafer; and,
heating the first and second wafers so as to bond the oxide layer of the first wafer to the implanted surface of the second wafer.
11. The method of claim 7 further comprising processing the silicon of the first wafer to form an integrated circuit of the RF semiconductor device therein.
12. The method of claim 7 further comprising processing the silicon of the first wafer to form transistors and inductors.
13. A method of fabricating an RF semiconductor device comprising:
forming a first oxide layer on a surface of a first wafer, wherein the first wafer comprises a high resistivity polycrystalline material;
forming a second oxide layer on a surface of a second wafer, wherein the second wafer comprises low resistivity silicon; and,
bonding the first and second oxide layers against one another so as to produce the RF semiconductor device.
14. The method of claim 13 wherein the polycrystalline material comprises polysilicon.
15. The method of claim 13 further comprising removing a portion of the silicon of the second wafer.
16. The method of claim 15 wherein the removing of a portion of the silicon of the second wafer comprises etching away the portion of the silicon of the second wafer.
17. The method of claim 15 wherein the removing of a portion of the silicon of the second wafer comprises grinding away the portion of the silicon of the second wafer.
18. The method of claim 15 wherein the removing of a portion of the silicon of the second wafer comprises etching and grinding away the portion of the silicon of the second wafer.
19. The method of claim 13 wherein the bonding of the first and second oxide layers against one another comprises heating the first and second wafers so as to bond the first and second oxide layers against one another.
20. The method of claim 13 further comprising processing the silicon of the second wafer to form an integrated circuit of the RF semiconductor device therein.
21. The method of claim 13 further comprising processing the silicon of the second wafer to form transistors and inductors.
22. A method of fabricating an RF semiconductor device starting with a SOI wafer having a top silicon layer, a buried oxide layer, and a bottom silicon layer, the method comprising:
forming a new oxide layer on a surface of the top silicon layer;
forming a high resistivity polysilicon layer over the new oxide layer;
removing the bottom silicon layer of the SOI wafer; and,
removing the buried oxide layer of the SOI wafer so as to produce the RF semiconductor device.
23. The method of claim 22 wherein the forming of a polysilicon layer over the new oxide layer comprises depositing a polysilicon layer on the new oxide layer.
24. The method of claim 23 wherein the removing of the bottom silicon layer of the SOI wafer comprises grinding and/or etching away the bottom silicon layer of the SOI wafer.
25. The method of claim 23 wherein the removing of the buried oxide layer of the SOI wafer comprises grinding and/or etching away the buried oxide layer of the SOI wafer.
26. The method of claim 25 wherein the removing of the bottom silicon layer of the SOI wafer comprises grinding and/or etching away the bottom silicon layer of the SOI wafer.
27. The method of claim 22 wherein the removing of the bottom silicon layer of the SOI wafer comprises grinding and/or etching away the bottom silicon layer of the SOI wafer.
28. The method of claim 22 wherein the removing of the buried oxide layer of the SOI wafer comprises grinding and/or etching away the buried oxide layer of the SOI wafer.
29. The method of claim 28 wherein the removing of the bottom silicon layer of the SOI wafer comprises grinding and/or etching away the bottom silicon layer of the SOI wafer.
30. The method of claim 22 further comprising processing the silicon remaining from the SOI wafer so as to form an integrated circuit of the RF semiconductor device therein.
31. The method of claim 22 further comprising processing the silicon remaining from the SOI wafer so as to form transistors and inductors.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/764,938 US20040159908A1 (en) | 2002-07-01 | 2004-01-26 | Silicon-on-insulator wafer for RF integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/186,494 US6743662B2 (en) | 2002-07-01 | 2002-07-01 | Silicon-on-insulator wafer for RF integrated circuit |
US10/764,938 US20040159908A1 (en) | 2002-07-01 | 2004-01-26 | Silicon-on-insulator wafer for RF integrated circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/186,494 Division US6743662B2 (en) | 2002-07-01 | 2002-07-01 | Silicon-on-insulator wafer for RF integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040159908A1 true US20040159908A1 (en) | 2004-08-19 |
Family
ID=29779903
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/186,494 Expired - Fee Related US6743662B2 (en) | 2002-07-01 | 2002-07-01 | Silicon-on-insulator wafer for RF integrated circuit |
US10/764,938 Abandoned US20040159908A1 (en) | 2002-07-01 | 2004-01-26 | Silicon-on-insulator wafer for RF integrated circuit |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/186,494 Expired - Fee Related US6743662B2 (en) | 2002-07-01 | 2002-07-01 | Silicon-on-insulator wafer for RF integrated circuit |
Country Status (6)
Country | Link |
---|---|
US (2) | US6743662B2 (en) |
EP (1) | EP1523772A2 (en) |
JP (1) | JP2005532679A (en) |
CN (1) | CN1679159A (en) |
AU (1) | AU2003247695A1 (en) |
WO (1) | WO2004003997A2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090110898A1 (en) * | 2007-10-31 | 2009-04-30 | International Business Machines Corporation | High resistivity soi base wafer using thermally annealed substrate |
US20090197416A1 (en) * | 2005-02-16 | 2009-08-06 | Samsung Electronics Co., Ltd. | Silicon nano wire having a silicon-nitride shell and mthod of manufacturing the same |
US8637381B2 (en) | 2011-10-17 | 2014-01-28 | International Business Machines Corporation | High-k dielectric and silicon nitride box region |
US8658514B2 (en) * | 2009-12-04 | 2014-02-25 | Soitec | Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7672558B2 (en) * | 2004-01-12 | 2010-03-02 | Honeywell International, Inc. | Silicon optical device |
US7217584B2 (en) * | 2004-03-18 | 2007-05-15 | Honeywell International Inc. | Bonded thin-film structures for optical modulators and methods of manufacture |
US7177489B2 (en) * | 2004-03-18 | 2007-02-13 | Honeywell International, Inc. | Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture |
US7149388B2 (en) * | 2004-03-18 | 2006-12-12 | Honeywell International, Inc. | Low loss contact structures for silicon based optical modulators and methods of manufacture |
US20050214989A1 (en) * | 2004-03-29 | 2005-09-29 | Honeywell International Inc. | Silicon optoelectronic device |
US20070065964A1 (en) * | 2005-09-22 | 2007-03-22 | Yinon Degani | Integrated passive devices |
US20070101927A1 (en) * | 2005-11-10 | 2007-05-10 | Honeywell International Inc. | Silicon based optical waveguide structures and methods of manufacture |
US7454102B2 (en) | 2006-04-26 | 2008-11-18 | Honeywell International Inc. | Optical coupling structure |
US20070274655A1 (en) * | 2006-04-26 | 2007-11-29 | Honeywell International Inc. | Low-loss optical device structure |
FR2912838B1 (en) | 2007-02-15 | 2009-06-05 | Commissariat Energie Atomique | METHOD FOR PRODUCING A TRANSISTOR GRID |
JP2009231376A (en) * | 2008-03-19 | 2009-10-08 | Shin Etsu Handotai Co Ltd | Soi wafer and semiconductor device, and method of manufacturing the soi wafer |
FR2933233B1 (en) * | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | GOOD RESISTANCE HIGH RESISTIVITY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME |
JP5532680B2 (en) * | 2009-05-27 | 2014-06-25 | 信越半導体株式会社 | Manufacturing method of SOI wafer and SOI wafer |
CN102023257B (en) * | 2009-09-15 | 2013-05-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor apparatus and method for detecting working condition of plasma flood gun (PFG) |
US9754860B2 (en) | 2010-12-24 | 2017-09-05 | Qualcomm Incorporated | Redistribution layer contacting first wafer through second wafer |
US8481405B2 (en) | 2010-12-24 | 2013-07-09 | Io Semiconductor, Inc. | Trap rich layer with through-silicon-vias in semiconductor devices |
US9553013B2 (en) | 2010-12-24 | 2017-01-24 | Qualcomm Incorporated | Semiconductor structure with TRL and handle wafer cavities |
US9624096B2 (en) | 2010-12-24 | 2017-04-18 | Qualcomm Incorporated | Forming semiconductor structure with device layers and TRL |
EP3734645A1 (en) | 2010-12-24 | 2020-11-04 | QUALCOMM Incorporated | Trap rich layer for semiconductor devices |
US8536021B2 (en) | 2010-12-24 | 2013-09-17 | Io Semiconductor, Inc. | Trap rich layer formation techniques for semiconductor devices |
US8846493B2 (en) | 2011-03-16 | 2014-09-30 | Sunedison Semiconductor Limited | Methods for producing silicon on insulator structures having high resistivity regions in the handle wafer |
FR2973158B1 (en) * | 2011-03-22 | 2014-02-28 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS |
US8741739B2 (en) | 2012-01-03 | 2014-06-03 | International Business Machines Corporation | High resistivity silicon-on-insulator substrate and method of forming |
US8536035B2 (en) * | 2012-02-01 | 2013-09-17 | International Business Machines Corporation | Silicon-on-insulator substrate and method of forming |
CN103077949B (en) * | 2013-01-28 | 2016-09-14 | 上海华虹宏力半导体制造有限公司 | Silicon radio frequency device on insulator and preparation method thereof |
CN103390593B (en) * | 2013-08-05 | 2015-09-23 | 苏州远创达科技有限公司 | A kind of Semiconductor substrate and manufacture method thereof |
US10090327B2 (en) * | 2014-01-17 | 2018-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device and method for forming the same |
EP3266038B1 (en) | 2015-03-03 | 2019-09-25 | GlobalWafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
CN107408532A (en) | 2015-03-17 | 2017-11-28 | 太阳能爱迪生半导体有限公司 | Thermostabilization electric charge capture layer for the manufacture of semiconductor-on-insulator structure |
EP3304586B1 (en) | 2015-06-01 | 2020-10-07 | GlobalWafers Co., Ltd. | A method of manufacturing silicon germanium-on-insulator |
DE102015210384A1 (en) | 2015-06-05 | 2016-12-08 | Soitec | Method for mechanical separation for a double-layer transfer |
DE102015211087B4 (en) * | 2015-06-17 | 2019-12-05 | Soitec | A method of making a high resistance semiconductor on insulator substrate |
CN105336766A (en) * | 2015-10-22 | 2016-02-17 | 上海华虹宏力半导体制造有限公司 | Method for locally thinning SOI top layer silicon thickness |
SG10201913373WA (en) | 2016-10-26 | 2020-03-30 | Globalwafers Co Ltd | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
FR3064398B1 (en) * | 2017-03-21 | 2019-06-07 | Soitec | SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, ESPECIALLY FOR A FRONT-SIDE TYPE IMAGE SENSOR, AND METHOD FOR MANUFACTURING SUCH STRUCTURE |
US10840328B1 (en) * | 2019-05-16 | 2020-11-17 | Vanguard International Semiconductor Corporation | Semiconductor devices having charge-absorbing structure disposed over substrate and methods for forming the semiconductor devices |
US11296190B2 (en) * | 2020-01-15 | 2022-04-05 | Globalfoundries U.S. Inc. | Field effect transistors with back gate contact and buried high resistivity layer |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4905075A (en) * | 1986-05-05 | 1990-02-27 | General Electric Company | Hermetic semiconductor enclosure |
US5168078A (en) * | 1988-11-29 | 1992-12-01 | Mcnc | Method of making high density semiconductor structure |
US5266135A (en) * | 1990-02-07 | 1993-11-30 | Harris Corporation | Wafer bonding process employing liquid oxidant |
US5362667A (en) * | 1992-07-28 | 1994-11-08 | Harris Corporation | Bonded wafer processing |
US5366923A (en) * | 1992-05-15 | 1994-11-22 | International Business Machines Corporation | Bonded wafer structure having a buried insulation layer |
US5376579A (en) * | 1993-07-02 | 1994-12-27 | The United States Of America As Represented By The Secretary Of The Air Force | Schemes to form silicon-on-diamond structure |
US5387555A (en) * | 1992-09-03 | 1995-02-07 | Harris Corporation | Bonded wafer processing with metal silicidation |
US5438220A (en) * | 1987-02-26 | 1995-08-01 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
US5773355A (en) * | 1994-04-08 | 1998-06-30 | Canon Kabushiki Kaisha | Method for manufacturing semiconductor substrate |
US5801084A (en) * | 1992-06-17 | 1998-09-01 | Harris Corporation | Bonded wafer processing |
US5849627A (en) * | 1990-02-07 | 1998-12-15 | Harris Corporation | Bonded wafer processing with oxidative bonding |
US5920764A (en) * | 1997-09-30 | 1999-07-06 | International Business Machines Corporation | Process for restoring rejected wafers in line for reuse as new |
US6150197A (en) * | 1997-04-25 | 2000-11-21 | The Whitaker Corp. | Method of fabricating heterolithic microwave integrated circuits |
US6183857B1 (en) * | 1997-06-18 | 2001-02-06 | Telefonaktiebolaget Lm Ericsson (Publ) | Substrate for high frequency integrated circuits |
US6239004B1 (en) * | 1997-08-29 | 2001-05-29 | Shin-Etsu Handotai Co., Ltd. | Method of forming oxide film on an SOI layer and method of fabricating a bonded wafer |
US6251751B1 (en) * | 1997-10-16 | 2001-06-26 | International Business Machines Corporation | Bulk and strained silicon on insulator using local selective oxidation |
US6255731B1 (en) * | 1997-07-30 | 2001-07-03 | Canon Kabushiki Kaisha | SOI bonding structure |
US6265248B1 (en) * | 1998-11-06 | 2001-07-24 | National Semiconductor Corporation | Method for producing semiconductor-on-insulator structure with reduced parasitic capacitance |
US6291324B1 (en) * | 1999-03-04 | 2001-09-18 | Simplex Solutions, Inc. | Method of modeling IC substrate noises utilizing improved doping profile access |
US20020008268A1 (en) * | 2000-06-13 | 2002-01-24 | Babcock Jeffrey A. | RF voltage controlled capacitor on thick-film SOI |
US6352909B1 (en) * | 2000-01-06 | 2002-03-05 | Silicon Wafer Technologies, Inc. | Process for lift-off of a layer from a substrate |
US6388290B1 (en) * | 1998-06-10 | 2002-05-14 | Agere Systems Guardian Corp. | Single crystal silicon on polycrystalline silicon integrated circuits |
US6410371B1 (en) * | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
US20020092307A1 (en) * | 2000-12-11 | 2002-07-18 | Ibm Corporation | Thermoelectric spot coolers for RF and microwave communication integrated circuits |
US6465324B2 (en) * | 2001-03-23 | 2002-10-15 | Honeywell International Inc. | Recessed silicon oxidation for devices such as a CMOS SOI ICs |
-
2002
- 2002-07-01 US US10/186,494 patent/US6743662B2/en not_active Expired - Fee Related
-
2003
- 2003-06-30 CN CN03820750.8A patent/CN1679159A/en active Pending
- 2003-06-30 JP JP2004518202A patent/JP2005532679A/en not_active Withdrawn
- 2003-06-30 WO PCT/US2003/020804 patent/WO2004003997A2/en not_active Application Discontinuation
- 2003-06-30 EP EP03762306A patent/EP1523772A2/en not_active Withdrawn
- 2003-06-30 AU AU2003247695A patent/AU2003247695A1/en not_active Abandoned
-
2004
- 2004-01-26 US US10/764,938 patent/US20040159908A1/en not_active Abandoned
Patent Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4905075A (en) * | 1986-05-05 | 1990-02-27 | General Electric Company | Hermetic semiconductor enclosure |
US5438220A (en) * | 1987-02-26 | 1995-08-01 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
US5168078A (en) * | 1988-11-29 | 1992-12-01 | Mcnc | Method of making high density semiconductor structure |
US5266135A (en) * | 1990-02-07 | 1993-11-30 | Harris Corporation | Wafer bonding process employing liquid oxidant |
US5849627A (en) * | 1990-02-07 | 1998-12-15 | Harris Corporation | Bonded wafer processing with oxidative bonding |
US5366923A (en) * | 1992-05-15 | 1994-11-22 | International Business Machines Corporation | Bonded wafer structure having a buried insulation layer |
US5801084A (en) * | 1992-06-17 | 1998-09-01 | Harris Corporation | Bonded wafer processing |
US5728624A (en) * | 1992-07-28 | 1998-03-17 | Harris Corporation | Bonded wafer processing |
US5362667A (en) * | 1992-07-28 | 1994-11-08 | Harris Corporation | Bonded wafer processing |
US5387555A (en) * | 1992-09-03 | 1995-02-07 | Harris Corporation | Bonded wafer processing with metal silicidation |
US5569620A (en) * | 1992-09-03 | 1996-10-29 | Harris Corporation | Bonded wafer processing with metal silicidation |
US5376579A (en) * | 1993-07-02 | 1994-12-27 | The United States Of America As Represented By The Secretary Of The Air Force | Schemes to form silicon-on-diamond structure |
US5773355A (en) * | 1994-04-08 | 1998-06-30 | Canon Kabushiki Kaisha | Method for manufacturing semiconductor substrate |
US6150197A (en) * | 1997-04-25 | 2000-11-21 | The Whitaker Corp. | Method of fabricating heterolithic microwave integrated circuits |
US6183857B1 (en) * | 1997-06-18 | 2001-02-06 | Telefonaktiebolaget Lm Ericsson (Publ) | Substrate for high frequency integrated circuits |
US6255731B1 (en) * | 1997-07-30 | 2001-07-03 | Canon Kabushiki Kaisha | SOI bonding structure |
US6239004B1 (en) * | 1997-08-29 | 2001-05-29 | Shin-Etsu Handotai Co., Ltd. | Method of forming oxide film on an SOI layer and method of fabricating a bonded wafer |
US5920764A (en) * | 1997-09-30 | 1999-07-06 | International Business Machines Corporation | Process for restoring rejected wafers in line for reuse as new |
US6251751B1 (en) * | 1997-10-16 | 2001-06-26 | International Business Machines Corporation | Bulk and strained silicon on insulator using local selective oxidation |
US6388290B1 (en) * | 1998-06-10 | 2002-05-14 | Agere Systems Guardian Corp. | Single crystal silicon on polycrystalline silicon integrated circuits |
US6265248B1 (en) * | 1998-11-06 | 2001-07-24 | National Semiconductor Corporation | Method for producing semiconductor-on-insulator structure with reduced parasitic capacitance |
US6291324B1 (en) * | 1999-03-04 | 2001-09-18 | Simplex Solutions, Inc. | Method of modeling IC substrate noises utilizing improved doping profile access |
US6352909B1 (en) * | 2000-01-06 | 2002-03-05 | Silicon Wafer Technologies, Inc. | Process for lift-off of a layer from a substrate |
US20020008268A1 (en) * | 2000-06-13 | 2002-01-24 | Babcock Jeffrey A. | RF voltage controlled capacitor on thick-film SOI |
US20020092307A1 (en) * | 2000-12-11 | 2002-07-18 | Ibm Corporation | Thermoelectric spot coolers for RF and microwave communication integrated circuits |
US6410371B1 (en) * | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
US6465324B2 (en) * | 2001-03-23 | 2002-10-15 | Honeywell International Inc. | Recessed silicon oxidation for devices such as a CMOS SOI ICs |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090197416A1 (en) * | 2005-02-16 | 2009-08-06 | Samsung Electronics Co., Ltd. | Silicon nano wire having a silicon-nitride shell and mthod of manufacturing the same |
US20090110898A1 (en) * | 2007-10-31 | 2009-04-30 | International Business Machines Corporation | High resistivity soi base wafer using thermally annealed substrate |
US7883990B2 (en) * | 2007-10-31 | 2011-02-08 | International Business Machines Corporation | High resistivity SOI base wafer using thermally annealed substrate |
US8658514B2 (en) * | 2009-12-04 | 2014-02-25 | Soitec | Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure |
US8962450B2 (en) | 2009-12-04 | 2015-02-24 | Soitec | Method for manufacturing a semiconductor-on-insulator structure having low electrical losses |
US9293473B2 (en) | 2009-12-04 | 2016-03-22 | Soitec | Method for manufacturing a semiconductor on insulator structure having low electrical losses |
US8637381B2 (en) | 2011-10-17 | 2014-01-28 | International Business Machines Corporation | High-k dielectric and silicon nitride box region |
Also Published As
Publication number | Publication date |
---|---|
AU2003247695A1 (en) | 2004-01-19 |
CN1679159A (en) | 2005-10-05 |
WO2004003997A2 (en) | 2004-01-08 |
EP1523772A2 (en) | 2005-04-20 |
US6743662B2 (en) | 2004-06-01 |
JP2005532679A (en) | 2005-10-27 |
AU2003247695A8 (en) | 2004-01-19 |
US20040002197A1 (en) | 2004-01-01 |
WO2004003997A3 (en) | 2004-06-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6743662B2 (en) | Silicon-on-insulator wafer for RF integrated circuit | |
EP0719452B1 (en) | Bonded wafer process incorporating diamond insulator | |
KR100819222B1 (en) | Composite structure with high heat dissipation | |
US5855693A (en) | Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication | |
JP7206366B2 (en) | High resistivity semiconductor-on-insulator wafer and manufacturing method | |
US20070278574A1 (en) | Compound semiconductor-on-silicon wafer with a thermally soft insulator | |
US10826459B2 (en) | Heterostructure and method of fabrication | |
US20080064197A1 (en) | STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C | |
EP0969500B1 (en) | Single crystal silicon on polycrystalline silicon integrated circuits | |
US7749863B1 (en) | Thermal management substrates | |
JP7470233B2 (en) | Radio Frequency Silicon-on-Insulator Wafer Platform with Superior Performance, Stability and Manufacturability | |
CN110352484A (en) | High resistivity silicon on insulated substrate and its manufacturing method | |
TW201630113A (en) | A method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers | |
US20090224369A1 (en) | IC Substrate and Method of Manufacture of IC Substrate | |
TW201724467A (en) | Structure for radiofrequency applications and process for manufacturing such a structure | |
EP2109883A1 (en) | Method of fabrication of highly heat dissipative substrates | |
US7695564B1 (en) | Thermal management substrate | |
TW201123282A (en) | Method for controlling the distribution of stresses in a semiconductor-on-insulator type structure and corresponding structure | |
GB2451602A (en) | Silicon on diamond microelectronic devices | |
JPH08505009A (en) | Circuit structure of silicon on diamond and method of manufacturing the same | |
JP3528880B2 (en) | Method for manufacturing SOI substrate | |
JP2961522B2 (en) | Substrate for semiconductor electronic device and method of manufacturing the same | |
JPH0613593A (en) | Semiconductor substrate | |
GB2296374A (en) | Fabricating semiconductor devices | |
US6238482B1 (en) | Method of producing a wafer with an epitaxial quality layer and device with epitaxial quality layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |