US20040015678A1 - Microprocessor for executing byte compiled Java code - Google Patents

Microprocessor for executing byte compiled Java code Download PDF

Info

Publication number
US20040015678A1
US20040015678A1 US10/114,678 US11467802A US2004015678A1 US 20040015678 A1 US20040015678 A1 US 20040015678A1 US 11467802 A US11467802 A US 11467802A US 2004015678 A1 US2004015678 A1 US 2004015678A1
Authority
US
United States
Prior art keywords
java
risc
module
microprocessor
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/114,678
Other languages
English (en)
Inventor
Oyvind Strom
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to US10/114,678 priority Critical patent/US20040015678A1/en
Assigned to ATMEL CORPORATION reassignment ATMEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STROM, OYVIND
Publication of US20040015678A1 publication Critical patent/US20040015678A1/en
Priority to US11/619,923 priority patent/US7917732B2/en
Priority to US13/030,984 priority patent/US8166280B2/en
Priority to US13/453,075 priority patent/US8533433B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Definitions

  • the invention relates generally to microprocessors, and more specifically to a microprocessor with a Java Virtual machine core architecture.
  • Java is an object oriented programming language that has become a de facto standard in network programming. At the present time, Java is also beginning to be utilized in the domain of embedded systems, or systems that contain a microprocessor or a microcontroller. Some of the strong points of the Java environment like its object orientation, automatic garbage collection and run time security features can be used with success in embedded applications. However, its run time environment presents a challenge for system designers because of the resource overhead related to running the Java code in a virtual machine such as an interpreter or a just-in-time compiler.
  • the Java binary code, called bytecode is distributed in one or more class files. Bytecodes are the instructions of a hypothetical computer that is specifically designed for the execution of Java programs. Conventional CPUs cannot execute this bytecode and therefore execute it in a software layer called the Java Virtual machine. This machine is an abstract machine specification and no implementation guidelines are given. The Java Virtual Machine Specification is published by Sun Microsystems.
  • a Java program there are basically four ways to execute a Java program on a physical computer platform.
  • the opcode is computed in a Java compiler 915 and the Java bytecode 925 is sent to an interpreter 930 before being sent to the operating system 950 and being executed by the CPU 960 .
  • the interpreter 930 presents a speed penalty of a factor of five compared to executing a program compiled to native code.
  • a second method 903 is similar except that instead of using an interpreter, the Java bytecode is dynamically compiled into the binary format 940 for the native platform by a Just In Time (JIT) compiler 935 .
  • JIT Just In Time
  • This process occurs inside the virtual machine and is not stored after the program has ended.
  • the newest Java JIT technique is called HotSpot and uses a principle where bottlenecks are analyzed and recompiled during program execution.
  • the JIT compiler will suffer from a memory overhead of a factor of two or three while executing the same application.
  • a third method 901 involves the use of cross compilers 910 to compile the Java source code into binary format 920 for the native platform.
  • the platform independence is lost and the binary program cannot be executed on multiple platforms.
  • a Java operating system 945 and Java processor 970 are used to execute the bytecode directly in silicon.
  • Some Java processors have a folding mechanism, which means that several instructions are combined and executed as one. However, most Java processors will execute as an interpreter wherein each opcode is read and then the appropriate action is taken to execute the instruction.
  • Java processor the fourth method 904
  • Java virtual machines have been developed for embedded processor platforms.
  • Most of the software solutions aim for 32 bit processors with some 100K memory size.
  • Java hardware processors for executing Java programs on silicon have also been developed.
  • These processors which support direct execution of Java instructions, implement 32 bits stack machines.
  • Some rely on extensions to the Java binary format in order to offer features like direct addressing and bit manipulation instructions.
  • Others do not execute Java binary codes directly, but have a very close architectural match to thereby increase performance of the virtual machine.
  • the processors are all targeted for medium to large embedded systems. There are currently no 8 or 16 bit processors available for direct execution of Java byte compiled code, even though the eight bit processor market has been considerably larger than the 32 bit processor market.
  • a microprocessor for executing byte compiled Java code in hardware that includes a RISC processor, a Java module for executing a first set of Java instructions in the RISC processor, a RISC module for executing a second set of Java instructions as microcode in the RISC processor, and a data path in the RISC processor, including a register file, shared by both modules.
  • the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the plurality of elements as a register file.
  • the microprocessor architecture is deduced from the observation that, despite Java's high semantic content instruction set, it shares a majority of the executed instructions with instructions of a generic RISC processor.
  • the architecture is intended to provide designers of embedded applications with an easy to integrate, small and cost effective processor solution with a well defined programming model. This results in the processor architecture embracing two programming models, making Java easy to integrate in small to medium size embedded applications.
  • FIG. 1 is a Venn diagram showing the overlap between the Java instruction set and a typical RISC instruction set.
  • FIG. 2 is a block diagram of the architecture of the microprocessor of the present invention.
  • FIG. 3 is a flow chart showing a normal run sequence for the microprocessor of the FIG. 2.
  • FIG. 4 is a block diagram of a portion of the register file of the microprocessor of FIG. 2.
  • FIG. 5 is a block diagram of the complete register file of the microprocessor of FIG. 2.
  • FIG. 6 is a block diagram illustrating the interrupt handling mechanism of the microprocessor of FIG. 2.
  • FIG. 7 is a block diagram illustrating the mode transfer mechanism of the microprocessor of FIG. 2.
  • FIG. 9 is a block diagram illustrating the instruction format for the RISC portion of the microprocessor of FIG. 2.
  • FIG. 20 is a block diagram of the instruction format for the control instructions of the SMILE RISC architecture used in the present invention.
  • FIG. 21 is a block diagram of the instruction format of the LL instructions of the SMILE RISC architecture used in the present invention.
  • Java Virtual machine instruction consists of an opcode specifying the operation to be performed, followed by zero or more operands embodying values to be performed upon. There are a total of 201 opcodes in the Java Virtual machine instruction set.
  • a significant feature of the Java Virtual machine instruction set is that a large number of instructions have a high semantic content. These instructions are difficult to implement in silicon. It is usually not feasible to execute the instructions having a high semantic content in one clock cycle, and the task of breaking them up into several less complex instructions is difficult in respect to resource allocation and timing constraints.
  • a large part of the Java instructions are type specific and therefore, there are many instructions which have the same semantic meaning.
  • the remaining instructions are divided among the RISC low level bit manipulation instructions 23 and Java's high level object creation and manipulation instructions 21 .
  • These observations establish the idea that both a RISC and a Java stack machine require approximately the same hardware resources.
  • a Java Virtual machine implementation in silicon needs to support instructions for bit manipulation, direct memory addressing, and trapping of complex opcodes.
  • the most frequently executed instructions in both architectures are the load/store instructions. In both architectures, they have the same semantic content. Implemented on silicon, these instructions could share the same hardware resources.
  • An arithmetic logic unit (ALU) 42 is connected to the register file 35 and the output of the ALU is supplied to the data bus 40 . This is partly because a large part of the critical path goes through the ALU and partly because this is one of the larger modules in an embedded microprocessor.
  • the minimum ALU implementation should perform the operations: ADD, SUB, AND, OR, XOR, MOVE, SET, CLEAR, SHIFT, and ROTATE.
  • the outputs of the register file 35 and the program counter 34 are processed through an adder 36 to an address multiplexer 37 .
  • the address multiplexer 37 is also connected to the address bus 41 .
  • An instruction fetch decoder 39 receives a signal from the data bus 40 and provides an output to the stack control unit 38 .
  • the microprocessor first powers up in the RISC mode of operation in order for the initialization code to execute. After the initialization 52 , the microprocessor switches to Java mode 53 and starts executing the Java program 54 . The microprocessor operates in Java mode until one of three events occurs: an interrupt 59 , an unimplemented Java instruction 60 , or a designated Java opcode for switching back to RISC mode 58 . If any of these events occur, the processor will jump to a pre-defined address and switch to RISC mode 55 and in this way handle the event. Upon finishing the RISC routine 56 , the processor will switch back to Java mode 57 and continue to execute the Java code at the point where it left off.
  • the Java model is able to execute the Java parts of the program. Such parts may be network capabilities or algorithms which are already implemented in a company's software library, and constitute modules of legacy software for reuse.
  • the RISC model aids in execution of the Java code by executing complex instructions as microcode. It also provides a flexible hardware interface which can be used to, for example, control highly specialized peripheral devices like sensors and actuators.
  • all Java instructions need to be implemented. However, in an embedded processor targeted for small to medium applications, several of the number formats supported by the Java Virtual machine are excessive. For instance, there are few processors in this segment that offer floating point units. Several of Java's more complex instructions have to be trapped and executed as microcode.
  • a key architectural element in the proposed microprocessor architecture is the register file.
  • This module has the function of a push-pop stack in Java mode and as a conventional load/store register file in RISC mode. This is also the module which allows the two virtual processors to communicate.
  • the RISC part of the architecture 71 sees a register file with N registers, and the RISC architecture interfaces the registers with the data memory through load/store instructions 72 , 73 , 74 .
  • the program counter and status register are included in the register file. In order to preserve orthogonality, these special registers are accessible like any other register.
  • FIG. 4 shows half of the register file as it is seen from the RISC and Java modes.
  • the registers 80 , 81 , 82 are seen by both the Java control unit 61 and the RISC portion of the circuit 71 .
  • the remaining N/2 registers are used for, among other things, the program counter, status register, scratch registers and stack control registers.
  • the stack is implemented as a circular stack and the stack sizes required are relatively small.
  • the stack size is scalable, and the number of stack elements is left as an implementation specific issue.
  • a stack overflow/underflow can be copied out in the memory 83 through an overflow/underflow mechanism. Possible stack overflow/underflow mechanisms can also be developed in a case-by-case manner.
  • the complete register file 90 is shown.
  • the RISC module can read and write from all the registers and there are no hardware limitations on which registers the RISC module can access.
  • the verification that the RISC module does not overwrite a special register during program execution is done in the software layer. If the programmer wants to use one of the special registers as a temporary memory, it will have to be stored on the RISC module stack if the value in this register needs to be recovered later during the execution.
  • the complete RISC register file 90 includes the Java operand stack 91 which includes a plurality of registers 92 , 93 , 94 , 95 , as was described with reference to FIG. 4.
  • the RISC registers 90 also includes a plurality of special registers.
  • the special registers include a program counter 106 , a program counter base 105 , a constant pool base address 107 , a local variable base address 104 , a Java stack pointer 103 , a status register 101 , and a RISC stack pointer 102 . Most of these register functions are self-explanatory.
  • the program counter base register 105 is used by the Java processor. When a new method is invoked, the Java module's program counter is set to zero.
  • the program counter base register stores the address where this method is invoked. On the address bus, this register is added with the program counter in order to fetch instructions from the correct place in the program memory.
  • the local variable base address register 104 performs a similar function. It stores the base address for the local variable in a Java method. These registers could of been chosen to reside outside the register file 90 . However, it represents an advantage to be able to have these registers inside the register file since the register can be reached by any RISC instruction, rather than having to implement special instructions to operate on special registers.
  • the Java stack pointer 103 keeps track of the location of the top of the Java operand stack, thus keeps track of the particular register of the M registers from which the operand is going to be fetched or to which the operand is going to be written.
  • the RISC stack pointer 102 points to a place in memory where the RISC can store variables temporarily if the register file is full.
  • the virtual processors communicate through the register file.
  • the RISC unit executes, amongst others, complex Java instructions. These small RISC programs have to fetch their operands from the top of the Java operand stack and place the results back to the top of the Java operand stack, and at the same time make sure that the Java stack pointer is incremented or decremented depending on the operation performed. This presents a problem since the RISC instruction format will only handle static registers.
  • the problem is solved by setting and clearing two status bits in the status register. Each of the status bits controls whether the source (X) or the destination (Y) operand are to be fetched from the register indicated in the instruction or whether the register number is to be dynamically read from the Java stack pointer register.
  • the RISC program which replaces a Java instruction has to set and clear these bits at the appropriate time. By setting the two bits in the register file, the RISC processor can use the content of the top of stack register as an argument for which register to access.
  • the Java control 120 and RISC control 122 modules are connected to a multiplexer 124 which produces the control lines 130 to the data path.
  • the status register 126 in the register file contains a control bit 128 which is supplied to the Java control module 120 , and the RISC control module 122 .
  • the control bit 128 also serves as the control input to the multiplexer 124 .
  • the control bit determines which of the control units, Java control unit 120 or RISC control unit 122 , is in operation. Control is transferred at a predefined state in both control modules. Control is therefore transferred synchronously where both machines will be in the same defined state.
  • interrupt handling mechanism is shown.
  • the processor checks that the implementation specific conditions, like specific flags, are true before jumping to a predefined address and switching to RISC mode. Then, the return address is stored on top of the RISC stack.
  • the jump address (0x63) 112 is shown to be stored at the predefined address (0xaf) 111 . At this predefined address, the jump address is read and an appropriate branch instruction to the new address is performed. Execution continues at this new address in RISC mode. To return to normal program execution, the processor executes the RISC instruction “Return from Interrupt” where the return address is popped off the top of the RISC stack.
  • the instruction trapping mechanism involves steps similar to the interrupt mechanism.
  • the JAVA control module detects this and the return address is stored on the top of the stack. Then, the processor switches to RISC mode and fetches a jump address from a predefined location in the memory. The RISC module then continues execution at the address fetched in the last step. Having the trapping mechanism be similar to the interrupt mechanism achieves maximum flexibility since only the first jump address is predefined in the design. This will enable the software linker to optimally plan the memory usage by only linking the RISC routines for the Java opcodes actually present in the program, thus saving precious memory space.
  • the RISC routine should end by popping the program counter off the top of the stack and saving it in the program counter register. This will ensure that the Java program continues at the correct place.
  • the microprocessor has a stack overflow/underflow handling mechanism. This mechanism in the Java push-pop stack can be implemented by reusing existing logic for instruction trapping. When an overflow occurs, the processor traps the overflow flag and jumps to a predefined address where it finds a jump vector to the software procedure that will handle the overflow/underflow condition.
  • FIG. 8 a typical run-time environment for a system with this processor concept is shown.
  • a developer can compile Java source code 141 in an ordinary Java compiler 142 and end up with Java class files 144 .
  • the processor accommodates an operating system with a file loader and an automatic memory management system, the rest of this process can occur dynamically and automatically.
  • small embedded systems often do not need an operating system and then the rest of this process must be done manually in the sense that a memory image of the program has to be created on an external platform.
  • the Java class files 144 have to be parsed through a linker 148 .
  • the program run through the linker will verify that the class file doesn't contain any illegal opcodes, modify codes or operands depending on instrumentation solutions, link the application with the specified Java class libraries 145 , link an assembly code to the RISC part 143 , set up a heap area, set up branch and jump addresses, and make a memory map.
  • the output from the linker will be a memory image which can be transferred to the ROM or flash memory 151 in the embedded system 152 .
  • Much of the purpose of making a Java processor is that the programmer should be able to use the Java programming language as unconstrained as possible. However, in this case, only supported types can be used and only a limited run-time library will be available. These constraints are, however, not limiting for the use of Java's main features.
  • the Java Virtual machine specification contains 201 instructions, many of them type specific. The number of instructions hardware implemented, and the number of instructions trapped, depends on the RISC architecture that is used. Other types of RISC architectures will have an effect on the number of instructions hardware implemented and trapped. The following instructions were not hardware implemented in the preferred embodiment of the present invention since these instructions are not considered as important in a small embedded processor: all instructions of type “float”, all instructions of type “double”, and all instructions of type “long”. This eliminates approximately 90 instructions from the 201 possible Java instructions. Of the remaining instructions, 68 instructions are implemented in the Java Virtual machine and 43 instructions are trapped and are executed as RISC routines. The instructions that are trapped and executed as RISC routines are noted below in Table 1.
  • Opcode Mnemonics Opcode Mnemonics 18 ldc 104 imul 182 invokevirtual 46 iaload 108 idiv 183 invokespecial 50 aaload 112 irem 184 invokestatic 51 baload 170 tableswitch 185 invokeinterface 52 caload 171 lookupswitch 187 new 53 saload 172 ireturn 188 newarray 79 iastore 173 lreturn 189 anewarray 83 aastore 176 areturn 190 arraylength 84 bastore 177 return 191 athrow 85 castore 178 getstatic 192 checkcast 86 sastore 179 putstatic 193 instanceof 90 dup_x1 180 getfield 194 monitorenter 91 dup_x2 181 putfield 195 monitorexit 92 dup2 197 multianewarray 93 dup2_x1 94 dup2_x2
  • SMILE Scalable Microcontroller Library Element
  • SMILE is targeted for small embedded systems and has certain scalability qualities.
  • the virtual RISC of the present invention implements a modified SMILE instruction set, except that the instructions format was slightly changed in order to accommodate 32 register addressing as is shown in FIG. 9. Additionally, the status registers in the present invention have been modified from the standard SMILE specification registers that are discussed with reference to FIG. 18 below.
  • the status registers of the present invention are shown in FIG. 10 and include a read/write register SR1 180 , and a second register SR2 having a read only portion 185 and a write only portion 188 .
  • the read/write register SR1 180 includes the Java flag 183 , discussed above with reference to FIG. 6, and also includes the Rx 182 and Ry 181 flags, which will be described below with reference to FIG. 14.
  • the remaining bits in the register are the same as in the SMILE specification, which is described below with reference to FIGS. 18 - 21 . Additionally, the range of some instructions were expanded, all registers are defined as type “long”, the register scaling parameters have been changed, and some new instructions were added.
  • the new instructions are: return from Java trap (RJ), RISC to Java control transfer (R2J), shift Java alignment left (SJL), and shift Java alignment right (SJR). The semantics of these new instructions are described below with reference to FIGS. 11-16.
  • the signals shown in each of FIGS. 11 - 16 are the reset signal 241 , the clock signal 242 , the Java instruction register 243 , the RISC instruction register 244 , the Java flag 245 , the data bus 246 , the program counter 247 , the address bus 248 , the Java Stack pointer 249 and the actual time 250 . Also, the instruction sequences 201 - 206 for each time period are shown.
  • FIG. 11 the first ten clock cycles are shown.
  • the processor is in RISC mode and initializes by executing the instruction it reads at address 0x0000. It then executes a series of load instructions to initialize the special registers Stack Pointer, Local Variable Base Address, and Program Counter Base Address. The initialization described is valid for a reset routine.
  • a JAVA call would include initializing only the Local Variable Base Address and the Program Counter Base Address.
  • the Constant Pool Base Address would have to be initialized if a new class was called.
  • the processor executes the instruction R2J which is equivalent to setting bit six in the status register.
  • the processor switches to Java mode in the next clock cycle.
  • the transfer of control is seamless as shown in FIG. 12.
  • the Java flag signal 245 is set high at time 105 and that the program counter 247 is set to zero as all Java methods start at zero.
  • the address on the address-bus 248 is the sum of the Program Counter and the Program Counter Base Address registers.
  • the Top of Stack pointer 249 which points to the register that is currently “Top of Stack”, is decremented as the number is popped off the stack.
  • Execution of “istore” at time 215 takes two clock cycles as shown in FIG. 13. Later in the same figure, an “istore”, is executed again at time 245 . This time, the alignment of the instruction in memory forces the opcode and the operand to be read on different clock cycles. The execution of this instruction is thus done in three clock cycles.
  • the Java control module reaches the unimplemented instruction “newarray”. This instruction is trapped.
  • the trap sequence takes four clock cycles as described above.
  • the Java flag goes low.
  • the processor now starts executing the instruction newarray as a RISC routine.
  • the instruction should initialize an array and return the start address for the array.
  • the RISC instructions SJL and SJR are move instructions to handle the alignment of the Java opcodes in the memory.
  • the Java stack pointer has a post-increment function.
  • the stack pointer is decremented in order for the RISC to access the correct register.
  • the RX flag is set in the status register. This means that the RISC reads the Java Stack Pointer register to determine the “Top of Stack”, and uses this as the RX register in the next instructions. This is what happens at time 465 where a constant is loaded into “Top of Stack”. This constant is the return value from the RISC routine returning the address of the newly created array. In this example, the array is static and the return value is therefore loaded as a constant.
  • Java stack pointer is incremented again at time 495 before the RISC returns control to the Java module again at time 515 in FIG. 16. The processor then continues to execute in Java mode.
  • the SMILE microcontroller must satisfy the following requirements: scalable size, design simplicity, moderate speed and moderate code efficiency. SMILE would typically be part of a larger system including timers, memory and some form of analog interface. The design will follow RISC principles whenever this is practical and relevant.
  • the compact instruction set (24 instructions) will have the following features:
  • Orthogonality The instruction set will be orthogonal, and there will be no undecoded instructions.
  • Parameterization & Scalability as the user may be in a position to modify the core hardware, the design will be parameterized. It will also be possible to scale the design according to the width of the memory, with the smallest width being 4 bits. Functionality will degrade gracefully as the memory width is reduced. Finally, expansion of the instruction set will be allowed through the addition of application specific instructions.
  • NRE is a power of 2.
  • SMILE versions will be specified as SMILEWSR_WIR_NRE.
  • the following parameters are derived from the above: WRF Width of register field in insn 21 ⁇ log 2 (NRE) WCF Width of condn. field in insn.
  • WAF Width of address-mode fields 3 NSR Number of short registers 2 (WRD/2) /2 NLR Number of long registers NSR NPA Number of process addresses 2 WLR NTA Number of total addresses 2 2WLR
  • the processor switches between processes on interrupt. Each process will see a set of NSR+NLR General Purpose Registers. Register L[NLR ⁇ 1] will be the program counter, PC.
  • Status information is held in two registers, SR1 and SR2, as defined by the following diagram.
  • the addressing modes used to access this information are shown in FIG. 18 and are described below.
  • ST x,y is not an allowed instruction.
  • Status bits K and P are affected by all instructions. All instructions may have a further field ⁇ cdn> added to specify a condition (not shown in above table). If this is not specified, then the default condition tests the S bit. This bit is set by all instructions except TB and FB, which sets or clears it depending on the result of the test. Instructions are always executed, and the appropriate status bits set. However, the results are only stored if ⁇ cdn> is true. The y result is always stored in pre-decrement and post-increment instructions.
  • the VS instruction is identical to the JS instruction, except that the jump address is not required to follow the instruction.
  • this address is fetched from an address table that is internal to the SMILE core, and the index used to retrieve the appropriate address is n ⁇ the VS argument.
  • This instruction therefore allows a subroutine jump where the destination of the jump is coded into the instruction itself.
  • the displacement follows the instruction in memory.
  • ⁇ disp> is a displacement, the same width as y. It is added to y and then the result zero-extended so that, when y is short, the mode can be used to access any element of the first page of memory.
  • the arguments Ax and Ay are always treated as having the same width as register x. If the y addressing mode is “register” and y is longer than x, then the least significant part of y is used for the operation.
  • the arrangement of the fields in FIG. 19 is with the rx field 501 at the most significant end.
  • the format is shown in FIG. 20.
  • the fields corresponding to instr, ay and ax of format 1 are occupied with the codes corresponding to ST 555 , “register” 552 and “simple” 553 respectively.
  • the remaining three fields must then be divided up into a part that specifies the instruction 551 and a part which specifies the condition 554 .
  • the condition part is the four least significant bits of the combined field.
  • the remaining instructions are termed “manipulate” instructions (MA instructions).
  • the LL instructions is included in this category. Their format is shown in FIG. 21.
  • the number of bits available to code the MA instructions 582 will be a function of WIR and NRE, and the minimum number of bits will be 5. This is sufficient to allow the coding of the instructions from TB to RC in the instruction table above. Surplus bits are used to code the instructions LL, where the number of literals that can be coded will depend on the number of surplus bits available.
  • 111 MA i.e. the code in the instr field for all the manipulate instructions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
US10/114,678 2001-04-23 2002-04-01 Microprocessor for executing byte compiled Java code Abandoned US20040015678A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/114,678 US20040015678A1 (en) 2001-04-23 2002-04-01 Microprocessor for executing byte compiled Java code
US11/619,923 US7917732B2 (en) 2001-04-23 2007-01-04 Microprocessor for executing byte compiled JAVA code
US13/030,984 US8166280B2 (en) 2001-04-23 2011-02-18 Microprocessor for executing byte compiled JAVA code
US13/453,075 US8533433B2 (en) 2001-04-23 2012-04-23 Microprocessor for executing byte compiled java code

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28619701P 2001-04-23 2001-04-23
US10/114,678 US20040015678A1 (en) 2001-04-23 2002-04-01 Microprocessor for executing byte compiled Java code

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/619,923 Continuation US7917732B2 (en) 2001-04-23 2007-01-04 Microprocessor for executing byte compiled JAVA code

Publications (1)

Publication Number Publication Date
US20040015678A1 true US20040015678A1 (en) 2004-01-22

Family

ID=23097513

Family Applications (4)

Application Number Title Priority Date Filing Date
US10/114,678 Abandoned US20040015678A1 (en) 2001-04-23 2002-04-01 Microprocessor for executing byte compiled Java code
US11/619,923 Expired - Fee Related US7917732B2 (en) 2001-04-23 2007-01-04 Microprocessor for executing byte compiled JAVA code
US13/030,984 Expired - Fee Related US8166280B2 (en) 2001-04-23 2011-02-18 Microprocessor for executing byte compiled JAVA code
US13/453,075 Expired - Lifetime US8533433B2 (en) 2001-04-23 2012-04-23 Microprocessor for executing byte compiled java code

Family Applications After (3)

Application Number Title Priority Date Filing Date
US11/619,923 Expired - Fee Related US7917732B2 (en) 2001-04-23 2007-01-04 Microprocessor for executing byte compiled JAVA code
US13/030,984 Expired - Fee Related US8166280B2 (en) 2001-04-23 2011-02-18 Microprocessor for executing byte compiled JAVA code
US13/453,075 Expired - Lifetime US8533433B2 (en) 2001-04-23 2012-04-23 Microprocessor for executing byte compiled java code

Country Status (9)

Country Link
US (4) US20040015678A1 (ko)
EP (1) EP1410174A2 (ko)
JP (1) JP3786644B2 (ko)
KR (1) KR20040034601A (ko)
AU (1) AU2002307080A1 (ko)
CA (1) CA2444968A1 (ko)
NO (1) NO20034743L (ko)
TW (1) TW575827B (ko)
WO (1) WO2002086699A2 (ko)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030221085A1 (en) * 2002-05-22 2003-11-27 International Business Machines Corporation Implementation of thread-static data in multi-threaded computer systems
US20040109430A1 (en) * 2002-10-28 2004-06-10 Dacosta Francis Low cost implementation for high performance embedded systems
US20060080680A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Platform independent dynamic linking
US20060080648A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Concurrent code loading mechanism
US20060080681A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Mechanism to extend functionality in a restricted computing environment
US20060080682A1 (en) * 2004-10-12 2006-04-13 Picsel Research Ltd. Run time dynamic linking
US20060080683A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Mechanism to circumvent restrictions of pre-written code components
US20060236077A1 (en) * 2005-04-15 2006-10-19 Oyvind Strom Microprocessor access of operand stack as a register file using native instructions
US20070168954A1 (en) * 2001-04-23 2007-07-19 Atmel Corporation Microprocessor for executing byte compiled java code
EP2071455A1 (de) * 2007-11-09 2009-06-17 Giesecke & Devrient GmbH Datenträger und Verfahren zum Betreiben eines Mikroprozessors eines Datenträgers
US20100088739A1 (en) * 2008-10-06 2010-04-08 International Business Machines Corporation Hardware Based Mandatory Access Control
US20100274991A1 (en) * 2007-12-28 2010-10-28 Institute Of Computing Technology Of The Chinese Academy Of Sciences Risc processor device and method of simulating floating-point stack operation thereof
US20140310696A1 (en) * 2011-06-08 2014-10-16 Hyperion Core Inc. Tool-level and hardware-level code optimization and respective hardware modification
US20160004536A1 (en) * 2014-07-02 2016-01-07 Freescale Semiconductor Inc. Systems And Methods For Processing Inline Constants
US9430200B1 (en) * 2015-06-04 2016-08-30 Microsoft Technology Licensing Llc Cross-library framework architecture feature sets
US20170168472A1 (en) * 2015-09-29 2017-06-15 Kabushiki Kaisha Toshiba Information processing apparatus or information communication terminal, and information processing method
US11500653B2 (en) * 2020-02-05 2022-11-15 International Business Machines Corporation Signal handling between programs associated with different addressing modes
US20230010863A1 (en) * 2019-12-11 2023-01-12 Arm Limited Intermodal calling branch instruction

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1447742A1 (en) 2003-02-11 2004-08-18 STMicroelectronics S.r.l. Method and apparatus for translating instructions of an ARM-type processor into instructions for a LX-type processor
US8607299B2 (en) * 2004-04-27 2013-12-10 Microsoft Corporation Method and system for enforcing a security policy via a security virtual machine
KR100597414B1 (ko) * 2004-10-21 2006-07-05 삼성전자주식회사 데이터 처리 장치 및 이를 이용한 레지스터 할당 방법
TWI306215B (en) 2005-04-29 2009-02-11 Ind Tech Res Inst Method and corresponding apparatus for compiling high-level languages into specific processor architectures
KR100725393B1 (ko) 2005-05-19 2007-06-07 삼성전자주식회사 자바 가상 머신에서 바이트 코드의 수행 시간을 줄이는시스템 및 방법
US8458677B2 (en) * 2009-08-20 2013-06-04 International Business Machines Corporation Generating code adapted for interlinking legacy scalar code and extended vector code
US8972705B2 (en) * 2011-11-16 2015-03-03 Andes Technology Corporation Executing instructions for managing constant pool base register used for accessing constants during subroutine execution
US9727353B2 (en) * 2015-10-30 2017-08-08 International Business Machines Corporation Simultaneously capturing status information for multiple operating modes
CN105511942B (zh) * 2015-12-02 2019-02-19 华为技术有限公司 语言虚拟机中热点中间代码的识别方法以及装置
US11106463B2 (en) * 2019-05-24 2021-08-31 Texas Instruments Incorporated System and method for addressing data in memory

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696959A (en) * 1993-11-30 1997-12-09 Texas Instruments Incorporated Memory store from a selected one of a register pair conditional upon the state of a selected status bit
US5812868A (en) * 1996-09-16 1998-09-22 Motorola Inc. Method and apparatus for selecting a register file in a data processing system
US5937193A (en) * 1996-11-27 1999-08-10 Vlsi Technology, Inc. Circuit arrangement for translating platform-independent instructions for execution on a hardware platform and method thereof
US5978901A (en) * 1997-08-21 1999-11-02 Advanced Micro Devices, Inc. Floating point and multimedia unit with data type reclassification capability
US6021469A (en) * 1996-01-24 2000-02-01 Sun Microsystems, Inc. Hardware virtual machine instruction processor
US6076155A (en) * 1995-10-24 2000-06-13 S3 Incorporated Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets
US6324686B1 (en) * 1997-11-11 2001-11-27 International Business Machines Corporation Just in time compiler technique
US6332215B1 (en) * 1998-12-08 2001-12-18 Nazomi Communications, Inc. Java virtual machine hardware for RISC and CISC processors
US6338160B1 (en) * 1998-12-08 2002-01-08 Nazomi Communications, Inc. Constant pool reference resolution method
US6654954B1 (en) * 1998-02-17 2003-11-25 International Business Machines Corporation Computer system, program product and method utilizing executable file with alternate program code attached as a file attribute
US6826749B2 (en) * 1998-12-08 2004-11-30 Nazomi Communications, Inc. Java hardware accelerator using thread manager
US6990567B1 (en) * 2000-12-22 2006-01-24 Lsi Logic Corporation Use of internal general purpose registers of a processor as a Java virtual machine top of stack and dynamic allocation of the registers according to stack status

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19521001A1 (de) * 1995-06-08 1996-12-19 Siemens Ag Kommunikationsfähige Schaltgeräteeinheit
US5701508A (en) * 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file
EP0976029A2 (en) * 1996-01-24 2000-02-02 Sun Microsystems, Inc. A processor for executing instruction sets received from a network or from a local memory
DE19736904A1 (de) * 1997-08-25 1999-03-04 Asea Brown Boveri Stromrichterschaltungsanordnung
KR20040034601A (ko) * 2001-04-23 2004-04-28 아트멜 코포레이숀 바이트 컴파일된 자바 코드를 실행하는 마이크로 프로세서

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696959A (en) * 1993-11-30 1997-12-09 Texas Instruments Incorporated Memory store from a selected one of a register pair conditional upon the state of a selected status bit
US6076155A (en) * 1995-10-24 2000-06-13 S3 Incorporated Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets
US6021469A (en) * 1996-01-24 2000-02-01 Sun Microsystems, Inc. Hardware virtual machine instruction processor
US6026485A (en) * 1996-01-24 2000-02-15 Sun Microsystems, Inc. Instruction folding for a stack-based machine
US5812868A (en) * 1996-09-16 1998-09-22 Motorola Inc. Method and apparatus for selecting a register file in a data processing system
US5937193A (en) * 1996-11-27 1999-08-10 Vlsi Technology, Inc. Circuit arrangement for translating platform-independent instructions for execution on a hardware platform and method thereof
US5978901A (en) * 1997-08-21 1999-11-02 Advanced Micro Devices, Inc. Floating point and multimedia unit with data type reclassification capability
US6324686B1 (en) * 1997-11-11 2001-11-27 International Business Machines Corporation Just in time compiler technique
US6654954B1 (en) * 1998-02-17 2003-11-25 International Business Machines Corporation Computer system, program product and method utilizing executable file with alternate program code attached as a file attribute
US6332215B1 (en) * 1998-12-08 2001-12-18 Nazomi Communications, Inc. Java virtual machine hardware for RISC and CISC processors
US6338160B1 (en) * 1998-12-08 2002-01-08 Nazomi Communications, Inc. Constant pool reference resolution method
US6826749B2 (en) * 1998-12-08 2004-11-30 Nazomi Communications, Inc. Java hardware accelerator using thread manager
US6990567B1 (en) * 2000-12-22 2006-01-24 Lsi Logic Corporation Use of internal general purpose registers of a processor as a Java virtual machine top of stack and dynamic allocation of the registers according to stack status

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110145548A1 (en) * 2001-04-23 2011-06-16 Atmel Corporation Microprocessor for executing byte compiled java code
US8533433B2 (en) 2001-04-23 2013-09-10 Atmel Corporation Microprocessor for executing byte compiled java code
US20070168954A1 (en) * 2001-04-23 2007-07-19 Atmel Corporation Microprocessor for executing byte compiled java code
US8166280B2 (en) 2001-04-23 2012-04-24 Atmel Corporation Microprocessor for executing byte compiled JAVA code
US7917732B2 (en) 2001-04-23 2011-03-29 Atmel Corporation Microprocessor for executing byte compiled JAVA code
US6915408B2 (en) * 2002-05-22 2005-07-05 International Business Machines Corporation Implementation of thread-static data in multi-threaded computer systems
US20030221085A1 (en) * 2002-05-22 2003-11-27 International Business Machines Corporation Implementation of thread-static data in multi-threaded computer systems
US20040109430A1 (en) * 2002-10-28 2004-06-10 Dacosta Francis Low cost implementation for high performance embedded systems
US20060080680A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Platform independent dynamic linking
US20060080683A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Mechanism to circumvent restrictions of pre-written code components
US20060080682A1 (en) * 2004-10-12 2006-04-13 Picsel Research Ltd. Run time dynamic linking
US20060080681A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Mechanism to extend functionality in a restricted computing environment
US20060080648A1 (en) * 2004-10-12 2006-04-13 Majid Anwar Concurrent code loading mechanism
US7444625B2 (en) 2004-10-12 2008-10-28 Picsel (Research) Limited Concurrent code loading mechanism
WO2006112978A3 (en) * 2005-04-15 2007-06-21 Atmel Corp Microprocessor access of operand stack as a register file using native instructions
US7478224B2 (en) 2005-04-15 2009-01-13 Atmel Corporation Microprocessor access of operand stack as a register file using native instructions
EP1875338A4 (en) * 2005-04-15 2008-07-30 Atmel Corp MICROPROCESSOR ACCESS TO AN OPERAND STACK AS A REGISTER FILE USING NATIVE COMMANDS
EP1875338A2 (en) * 2005-04-15 2008-01-09 Atmel Corporation Microprocessor access of operand stack as a register file using native instructions
WO2006112978A2 (en) 2005-04-15 2006-10-26 Atmel Corporation Microprocessor access of operand stack as a register file using native instructions
US20060236077A1 (en) * 2005-04-15 2006-10-19 Oyvind Strom Microprocessor access of operand stack as a register file using native instructions
EP2071455A1 (de) * 2007-11-09 2009-06-17 Giesecke & Devrient GmbH Datenträger und Verfahren zum Betreiben eines Mikroprozessors eines Datenträgers
US20100274991A1 (en) * 2007-12-28 2010-10-28 Institute Of Computing Technology Of The Chinese Academy Of Sciences Risc processor device and method of simulating floating-point stack operation thereof
US8788796B2 (en) * 2007-12-28 2014-07-22 Loongson Technology Corporation Limited Technique for simulating floating-point stack operation involving conversion of certain floating-point register numbers based on a top-of-stack pointer and modulo function
US10802990B2 (en) * 2008-10-06 2020-10-13 International Business Machines Corporation Hardware based mandatory access control
US20100088739A1 (en) * 2008-10-06 2010-04-08 International Business Machines Corporation Hardware Based Mandatory Access Control
US9703538B2 (en) * 2011-06-08 2017-07-11 Hyperion Core, Inc. Tool-level and hardware-level code optimization and respective hardware modification
US20140310696A1 (en) * 2011-06-08 2014-10-16 Hyperion Core Inc. Tool-level and hardware-level code optimization and respective hardware modification
US10324723B2 (en) * 2014-07-02 2019-06-18 Nxp Usa, Inc. Systems and methods for processing both instructions and constant values from a memory of a digital processor accessed by separate pointers
US20160004536A1 (en) * 2014-07-02 2016-01-07 Freescale Semiconductor Inc. Systems And Methods For Processing Inline Constants
US20160357531A1 (en) * 2015-06-04 2016-12-08 Microsoft Technology Licensing, Llc Cross-library framework architecture feature sets
US10152309B2 (en) * 2015-06-04 2018-12-11 Microsoft Technology Licensing, Llc Cross-library framework architecture feature sets
US9430200B1 (en) * 2015-06-04 2016-08-30 Microsoft Technology Licensing Llc Cross-library framework architecture feature sets
US20170168472A1 (en) * 2015-09-29 2017-06-15 Kabushiki Kaisha Toshiba Information processing apparatus or information communication terminal, and information processing method
US10691089B2 (en) * 2015-09-29 2020-06-23 Kabushiki Kaisha Toshiba Information processing apparatus or information communication terminal, and information processing method
US20230010863A1 (en) * 2019-12-11 2023-01-12 Arm Limited Intermodal calling branch instruction
US11500653B2 (en) * 2020-02-05 2022-11-15 International Business Machines Corporation Signal handling between programs associated with different addressing modes

Also Published As

Publication number Publication date
US20120204017A1 (en) 2012-08-09
US8533433B2 (en) 2013-09-10
US7917732B2 (en) 2011-03-29
WO2002086699A2 (en) 2002-10-31
KR20040034601A (ko) 2004-04-28
JP2004532466A (ja) 2004-10-21
TW575827B (en) 2004-02-11
US20070168954A1 (en) 2007-07-19
NO20034743L (no) 2003-12-23
CA2444968A1 (en) 2002-10-31
US20110145548A1 (en) 2011-06-16
US8166280B2 (en) 2012-04-24
NO20034743D0 (no) 2003-10-23
WO2002086699A3 (en) 2004-02-12
JP3786644B2 (ja) 2006-06-14
EP1410174A2 (en) 2004-04-21
AU2002307080A1 (en) 2002-11-05

Similar Documents

Publication Publication Date Title
US7917732B2 (en) Microprocessor for executing byte compiled JAVA code
US7478224B2 (en) Microprocessor access of operand stack as a register file using native instructions
US10055237B2 (en) Virtual machine coprocessor for accelerating software execution
JP2834837B2 (ja) プログラマブルコントローラ
KR100618756B1 (ko) 네트워크또는로컬메모리로부터수신된명령세트를실행하는프로세서및컴퓨터시스템
JP3816961B2 (ja) バーチャルマシン命令を処理するためのデータ処理装置
KR100412920B1 (ko) 데이터 밀도가 높은 ｒｉｓｃ 프로세서
US5933642A (en) Compiling system and method for reconfigurable computing
KR100236527B1 (ko) 벡터 레지스터의 복수 뱅크를 사용한 단일 명령복수 데이터 처 리
US7080362B2 (en) Java virtual machine hardware for RISC and CISC processors
US7243213B2 (en) Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product
EP1622009A1 (en) JSM architecture and systems
US20010010072A1 (en) Instruction translator translating non-native instructions for a processor into native instructions therefor, instruction memory with such translator, and data processing apparatus using them
KR20020028814A (ko) 마이크로코드 엔진을 이용한 자바 하드웨어 가속기
WO1999054813A9 (en) Risc processor with context switch register sets accessible by external coprocessor
Glossner et al. Delft-Java dynamic translation
Säntti et al. Java Co-Processor for Embedded Systems
Egger Development of an Aos Operating System for the DNARD Network Computer
Salamí et al. Initial evaluation of multimedia extensions on vliw architectures
Thomas Mite: a fast and flexible virtual machine
WO1999023549A1 (en) Direct cache accessing primary operations hierarchically organized to snippets and threads implemented in isa processor

Legal Events

Date Code Title Description
AS Assignment

Owner name: ATMEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STROM, OYVIND;REEL/FRAME:012838/0694

Effective date: 20020319

STCB Information on status: application discontinuation

Free format text: EXPRESSLY ABANDONED -- DURING PUBLICATION PROCESS