US20040004260A1 - Method of forming dual-implanted gate and structure formed by the same - Google Patents

Method of forming dual-implanted gate and structure formed by the same Download PDF

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US20040004260A1
US20040004260A1 US10/064,372 US6437202A US2004004260A1 US 20040004260 A1 US20040004260 A1 US 20040004260A1 US 6437202 A US6437202 A US 6437202A US 2004004260 A1 US2004004260 A1 US 2004004260A1
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layer
forming
substrate
stack
structures
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US6673712B1 (en
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Benny Yen
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Promos Technologies Inc
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Promos Technologies Inc
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Priority to DE10233421A priority patent/DE10233421B4/en
Priority to US10/605,426 priority patent/US20040104440A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Definitions

  • the present invention relates to a method of forming a semiconductor device and a structure formed by the same. More particularly, the present invention relates to a method of forming a dual-implanted gate and a structure formed by the same.
  • the gate of most semiconductor devices has a stack structure that includes a doped polysilicon layer and a metallic layer or a metal silicide layer.
  • a semiconductor device having both n-doped and p-doped polysilicon gates the so-called “dual-implanted gate”, polysilicon material is first deposited over a substrate. An ion implantation is carried out to implant ions into the substrate such that n-type dopants are implanted into NMOS region and p-type dopants are implanted into PMOS region. Thereafter, a layer of tungsten or tungsten silicide (WSi x ) is formed over the doped polysilicon layer. Finally, an etching operation is conducted to pattern out a dual-implanted gate structure.
  • WSi x tungsten or tungsten silicide
  • tungsten layer may peel off from the doped polysilicon layer after a subsequent thermal processing operation.
  • one object of the present invention is to provide a method of forming a dual-implanted gate capable of preventing doped ions having different electrical states from cross diffusing through an overhead metallic layer.
  • a second object of this invention is to provide a method of forming a dual-implanted gate capable of preventing any change in concentration of doped ions inside a doped polysilicon layer.
  • a third object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing the degradation of device performance.
  • a fourth object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing the formation of gates having an irregular shape.
  • a fifth object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing an overhead metallic layer from peeling off a doped polysilicon layer.
  • the invention provides a method of forming a dual-implanted gate.
  • the method includes the following steps. First, a substrate having a gate oxide layer thereon is provided. A polysilicon layer, a sacrificial layer and a mask layer are sequentially formed over the substrate. The polysilicon layer, the sacrificial layer and the mask layer are patterned to form a first structure for forming an N-type gate and a second structure for forming a P-type gate. A dielectric layer is formed over the substrate covering the first and the second structure. The dielectric layer is planarized to expose the upper surface of the mask layer in the first and the second structure.
  • the mask layer is removed to form a plurality of trenches.
  • the first and the second structure are implanted using ions having different electrical states.
  • the sacrificial layer is removed.
  • a barrier layer is formed over the substrate.
  • a metallic layer is formed over the substrate completely filling the trenches.
  • the metallic layer is planarized to remove excess metal outside the trench.
  • the exposed barrier layer is removed and then the dielectric layer is removed to form a plurality of gate structures. Finally, spacers may form on the sidewalls of the gate structures.
  • a barrier layer is formed over the doped polysilicon layer before forming the metallic layer.
  • dopants having different electrical states within the doped polysilicon layer are prevented from cross diffusing with the overhead metallic layer.
  • changes in dopant concentration within the doped polysilicon layer and the peeling of the metallic layer away from the doped polysilicon layer are prevented.
  • device performance can be maintained.
  • by enclosing the sidewall of the metallic layer with a barrier layer the formation of irregular-shaped gates due to a difference in material properties between the metallic layer and the polysilicon layer is largely avoided.
  • the invention provides a dual-implanted gate.
  • the dual-implanted gate includes a stack structure and a spacer on a substrate.
  • the stack structure includes a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer.
  • the spacer is formed on the stack layer over the substrate and the stack structure is enclosing by the spacer.
  • the invention provides a dual-implanted gate.
  • the dual-implanted gate includes a plurality of stack structures and a plurality of corresponding spacers.
  • the stack structure includes a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer.
  • the spacer is formed on the stack layers over the substrate and each of the stack structure is enclosed by the corresponding one of the spacers.
  • FIGS. 1A to 1 J are schematic cross-sectional views showing the progression of steps for producing a dual-implanted gate according to one preferred embodiment of this invention.
  • FIGS. 1A to 1 J are schematic cross-sectional views showing the progression of steps for producing a dual-implanted gate according to one preferred embodiment of this invention.
  • a substrate 100 having a gate oxide layer 102 thereon is provided.
  • a plurality of stack structures 110 each having a polysilicon layer 104 , a sacrificial (SAC) layer 106 and a mask layer 108 is formed over the gate oxide layer 102 .
  • the sacrificial layer 106 can be an oxide layer and the mask layer can be a polysilicon layer or other material having a high etching selectivity relative to a subsequently formed dielectric layer, for example.
  • the stack structure 110 is formed, for example, by a series of deposition processes to form a polysilicon layer, a sacrificial layer and a mask layer sequentially over the substrate 100 . Thereafter, the polysilicon layer, the sacrificial layer and the mask layer are patterned to form a first structure 110 a for implanting p-type dopants and a second structure 110 b for implanting n-type dopants.
  • a dielectric layer is formed over the substrate 100 covering the stack structure 110 .
  • the dielectric layer 112 can be a silicon nitride layer, silicon oxide layer or other material having a high etching selectivity ratio relative to the mask layer 108 , for example.
  • the dielectric layer 112 is planarized to expose the upper surface of the mask layer 108 within the stack structures 110 , for example, by conducting a chemical-mechanical polishing (CMP) operation.
  • CMP chemical-mechanical polishing
  • the mask layer 108 is removed to form a plurality of trenches 114 .
  • the mask layer 108 can be removed by dry etching, for example.
  • a patterned photoresist layer 116 is formed over the substrate 100 so that the second structure 110 b for receiving n-type dopants is covered while the first structure 110 a for receiving p-type dopants is exposed. Thereafter, an ion implantation 118 is carried out implanting p-type ions into first structure 110 a so that the polysilicon layer 104 is converted into a p-doped polysilicon layer 104 a .
  • the p-type dopants include boron or boron difluoride (BF 2 ) ions for example.
  • the photoresist layer 116 is removed.
  • Another patterned photoresist layer 120 is formed over the substrate 100 such that the first structure 110 a is covered while the second structure 110 b for receiving n-type dopants is exposed.
  • another ion implantation 122 is carried out implanting n-type ions into the second structure 110 b so that the polysilicon layer 104 is converted into an n-doped polysilicon layer 104 b .
  • the n-type dopants include phosphorus or arsenic, for example.
  • the photoresist layer 120 is removed. Thereafter, the sacrificial layer 106 is removed.
  • a barrier layer 124 is formed over the substrate 100 .
  • the barrier layer 124 can be a composite layer such as a titanium/titanium nitride (Ti/TiN) layer.
  • An annealing operation such as a rapid thermal process (RTP) may be conducted to lower the contact resistance with a subsequently formed overhead metallic layer.
  • a metallic layer 126 is formed over the substrate 100 completely filling the trenches 114 .
  • the metallic layer can be a tungsten layer, for example.
  • the barrier layer 124 between the metallic layer 126 and the doped polysilicon layers 104 a and 104 b prevents n-type or p-type ions from diffusing into another polysilicon layer through the metallic layer 126 .
  • the barrier layer 124 is an effective barrier to the out-diffusion of dopants.
  • the metallic layer 126 is planarized using the barrier layer 124 as an etching end point. This removes the metallic layer 126 above the trenches 114 .
  • the metallic layer 126 is planarized by chemical-mechanical polishing, for example.
  • the exposed barrier layer 124 is removed so that the upper surface of the dielectric layer 112 is exposed.
  • the barrier layer 124 may be removed by chemical-mechanical polishing.
  • the dielectric layer 112 is removed to form a p-doped gate structure 128 a and an n-doped gate structure 128 b .
  • spacers 130 are formed on the sidewalls of the gate structures 128 a and 128 b .
  • the spacers 130 can be a silicon nitride layer, for example.
  • a barrier layer is formed over the doped polysilicon layer before depositing metallic material to form the metallic layer. Hence, dopants having different electrical properties are prevented from out-diffusing from the doped polysilicon layer through the metallic layer and vice versa.

Abstract

A method of forming a dual-implanted gate and a structure formed by the same. Stack structures comprising a polysilicon layer, a sacrificial layer and a mask layer are formed over a substrate with a gate oxide layer thereon. A dielectric layer is formed over the substrate covering the stack structures. The dielectric layer is planarized to expose the upper surface of the mask layer in the first and the second structure. The mask layer is removed to form a plurality of trenches. The stack structures are selectively implanted using ions having different electrical states. The sacrificial layer is removed. Thereafter, a barrier layer is formed over the interior surface of the trenches. A metallic layer is formed over the substrate completely filling the trenches. The dielectric layer is removed to form a plurality of gate structures. Spacers may on the sidewalls of the gate structures as well.

Description

    BACKGROUND OF INVENTION
  • 1. Field of Invention [0001]
  • The present invention relates to a method of forming a semiconductor device and a structure formed by the same. More particularly, the present invention relates to a method of forming a dual-implanted gate and a structure formed by the same. [0002]
  • 2. Description of Related Art [0003]
  • At present, the gate of most semiconductor devices has a stack structure that includes a doped polysilicon layer and a metallic layer or a metal silicide layer. To manufacture a semiconductor device having both n-doped and p-doped polysilicon gates, the so-called “dual-implanted gate”, polysilicon material is first deposited over a substrate. An ion implantation is carried out to implant ions into the substrate such that n-type dopants are implanted into NMOS region and p-type dopants are implanted into PMOS region. Thereafter, a layer of tungsten or tungsten silicide (WSi[0004] x) is formed over the doped polysilicon layer. Finally, an etching operation is conducted to pattern out a dual-implanted gate structure.
  • However, the deposition of tungsten or tungsten silicide over the polysilicon layer often leads to an out-diffusion of dopant ions. This is because the grain boundary of the tungsten or tungsten silicide layer is relatively large. Hence, the n-type or p-type ions within the doped polysilicon layer can easily diffuse through the tungsten or tungsten silicide layer into another polysilicon layer. Under such circumstances, the concentration of dopants within the polysilicon layer is likely to drop, leading to a degradation of device performance. [0005]
  • In addition, if a tungsten layer is formed over the polysilicon layer, difference in material properties between tungsten and polysilicon may lead to the production of gates having an irregular shape after patterning through an etching operation. Similarly, due to a difference in material properties between tungsten and polysilicon, the tungsten layer may peel off from the doped polysilicon layer after a subsequent thermal processing operation. [0006]
    • SUMMARY OF INVENTION
  • Accordingly, one object of the present invention is to provide a method of forming a dual-implanted gate capable of preventing doped ions having different electrical states from cross diffusing through an overhead metallic layer. [0007]
  • A second object of this invention is to provide a method of forming a dual-implanted gate capable of preventing any change in concentration of doped ions inside a doped polysilicon layer. [0008]
  • A third object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing the degradation of device performance. [0009]
  • A fourth object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing the formation of gates having an irregular shape. [0010]
  • A fifth object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing an overhead metallic layer from peeling off a doped polysilicon layer. [0011]
  • To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a dual-implanted gate. The method includes the following steps. First, a substrate having a gate oxide layer thereon is provided. A polysilicon layer, a sacrificial layer and a mask layer are sequentially formed over the substrate. The polysilicon layer, the sacrificial layer and the mask layer are patterned to form a first structure for forming an N-type gate and a second structure for forming a P-type gate. A dielectric layer is formed over the substrate covering the first and the second structure. The dielectric layer is planarized to expose the upper surface of the mask layer in the first and the second structure. The mask layer is removed to form a plurality of trenches. The first and the second structure are implanted using ions having different electrical states. The sacrificial layer is removed. Thereafter, a barrier layer is formed over the substrate. A metallic layer is formed over the substrate completely filling the trenches. The metallic layer is planarized to remove excess metal outside the trench. The exposed barrier layer is removed and then the dielectric layer is removed to form a plurality of gate structures. Finally, spacers may form on the sidewalls of the gate structures. [0012]
  • In this invention, a barrier layer is formed over the doped polysilicon layer before forming the metallic layer. Thus, dopants having different electrical states within the doped polysilicon layer are prevented from cross diffusing with the overhead metallic layer. Hence, changes in dopant concentration within the doped polysilicon layer and the peeling of the metallic layer away from the doped polysilicon layer are prevented. Ultimately, device performance can be maintained. Furthermore, by enclosing the sidewall of the metallic layer with a barrier layer, the formation of irregular-shaped gates due to a difference in material properties between the metallic layer and the polysilicon layer is largely avoided. [0013]
  • To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a dual-implanted gate. The dual-implanted gate includes a stack structure and a spacer on a substrate. The stack structure includes a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer. The spacer is formed on the stack layer over the substrate and the stack structure is enclosing by the spacer. [0014]
  • To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a dual-implanted gate. The dual-implanted gate includes a plurality of stack structures and a plurality of corresponding spacers. The stack structure includes a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer. The spacer is formed on the stack layers over the substrate and each of the stack structure is enclosed by the corresponding one of the spacers. [0015]
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.[0016]
    • BRIEF DESCRIPTION OF DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, [0017]
  • FIGS. 1A to [0018] 1J are schematic cross-sectional views showing the progression of steps for producing a dual-implanted gate according to one preferred embodiment of this invention.
    • DETAILED DESCRIPTION
  • Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. [0019]
  • FIGS. 1A to [0020] 1J are schematic cross-sectional views showing the progression of steps for producing a dual-implanted gate according to one preferred embodiment of this invention. As shown in FIG. 1A, a substrate 100 having a gate oxide layer 102 thereon is provided. A plurality of stack structures 110 each having a polysilicon layer 104, a sacrificial (SAC) layer 106 and a mask layer 108 is formed over the gate oxide layer 102. The sacrificial layer 106 can be an oxide layer and the mask layer can be a polysilicon layer or other material having a high etching selectivity relative to a subsequently formed dielectric layer, for example. The stack structure 110 is formed, for example, by a series of deposition processes to form a polysilicon layer, a sacrificial layer and a mask layer sequentially over the substrate 100. Thereafter, the polysilicon layer, the sacrificial layer and the mask layer are patterned to form a first structure 110 a for implanting p-type dopants and a second structure 110 b for implanting n-type dopants.
  • As shown in FIG. 1B, a dielectric layer is formed over the [0021] substrate 100 covering the stack structure 110. The dielectric layer 112 can be a silicon nitride layer, silicon oxide layer or other material having a high etching selectivity ratio relative to the mask layer 108, for example.
  • As shown in FIG. 1C, the [0022] dielectric layer 112 is planarized to expose the upper surface of the mask layer 108 within the stack structures 110, for example, by conducting a chemical-mechanical polishing (CMP) operation.
  • As shown in FIG. 1D, the [0023] mask layer 108 is removed to form a plurality of trenches 114. The mask layer 108 can be removed by dry etching, for example.
  • As shown in FIG. 1E, a patterned [0024] photoresist layer 116 is formed over the substrate 100 so that the second structure 110 b for receiving n-type dopants is covered while the first structure 110 a for receiving p-type dopants is exposed. Thereafter, an ion implantation 118 is carried out implanting p-type ions into first structure 110 a so that the polysilicon layer 104 is converted into a p-doped polysilicon layer 104 a. The p-type dopants include boron or boron difluoride (BF2) ions for example.
  • As shown in FIG. 1F, the [0025] photoresist layer 116 is removed. Another patterned photoresist layer 120 is formed over the substrate 100 such that the first structure 110 a is covered while the second structure 110 b for receiving n-type dopants is exposed. Thereafter, another ion implantation 122 is carried out implanting n-type ions into the second structure 110 b so that the polysilicon layer 104 is converted into an n-doped polysilicon layer 104 b. The n-type dopants include phosphorus or arsenic, for example.
  • As shown in FIG. 1G, the [0026] photoresist layer 120 is removed. Thereafter, the sacrificial layer 106 is removed. A barrier layer 124 is formed over the substrate 100. The barrier layer 124 can be a composite layer such as a titanium/titanium nitride (Ti/TiN) layer. An annealing operation such as a rapid thermal process (RTP) may be conducted to lower the contact resistance with a subsequently formed overhead metallic layer. A metallic layer 126 is formed over the substrate 100 completely filling the trenches 114. The metallic layer can be a tungsten layer, for example. The barrier layer 124 between the metallic layer 126 and the doped polysilicon layers 104 a and 104 b prevents n-type or p-type ions from diffusing into another polysilicon layer through the metallic layer 126. In other words, the barrier layer 124 is an effective barrier to the out-diffusion of dopants.
  • As shown in FIG. 1H, the [0027] metallic layer 126 is planarized using the barrier layer 124 as an etching end point. This removes the metallic layer 126 above the trenches 114. The metallic layer 126 is planarized by chemical-mechanical polishing, for example.
  • As shown in FIG. 1I, the exposed [0028] barrier layer 124 is removed so that the upper surface of the dielectric layer 112 is exposed. Similarly, the barrier layer 124 may be removed by chemical-mechanical polishing.
  • As shown in FIG. 1J, the [0029] dielectric layer 112 is removed to form a p-doped gate structure 128 a and an n-doped gate structure 128 b. Finally, spacers 130 are formed on the sidewalls of the gate structures 128 a and 128 b. The spacers 130 can be a silicon nitride layer, for example.
  • In conclusion, major aspects of this invention includes: [0030]
  • 1. A barrier layer is formed over the doped polysilicon layer before depositing metallic material to form the metallic layer. Hence, dopants having different electrical properties are prevented from out-diffusing from the doped polysilicon layer through the metallic layer and vice versa. [0031]
  • 2. Since the barrier layer between the doped polysilicon layer and the metallic layer prevents any cross-diffusion of n-type or p-type ions, dopant concentration within various doped polysilicon layers can be maintained. [0032]
  • 3. Without out-diffusion of dopants, device performance is reliable. [0033]
  • 4. By enclosing the sidewall of the metallic layer with a barrier layer, irregularity in gate profile due to a difference in material properties between the metallic layer and the polysilicon layer is prevented. [0034]
  • 5. Because the metallic layer and the doped polysilicon layer are separated from each other by a barrier layer, the metallic layer is prevented from peeling away from an underlying doped polysilicon layer. [0035]
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. [0036]

Claims (20)

1. A method of forming a dual-implanted gate on a substrate having a gate oxide layer thereon, comprising the steps of:
forming a plurality of stack structures on the substrate, wherein each stack structure belongs to a first group or a second group and each stack structure includes a polysilicon layer, a sacrificial layer and a mask layer;
forming a dielectric layer over the substrate covering the stack structures;
planarizing the dielectric layer to expose the upper surface of the mask layer within the stack structures;
removing the mask layer to form a plurality of trenches;
conducting a first ion implantation to implant first type ions into the stack structures belonging to the first group;
conducting a second ion implantation to implant second type ions into the stack structures belonging to the second group;
removing the sacrificial layer;
forming a barrier layer over the substrate covering the interior surface of the trenches;
forming a metallic layer over the substrate completely filling the trenches;
removing the metallic layer and barrier layer above and beyond the trenches; and
removing the dielectric layer to form gate structures.
2. The method of claim 1, wherein the step of forming a plurality of stack structures on the substrate further includes the sub-steps of:
sequentially forming a polysilicon layer, a sacrificial layer and a mask layer over the substrate; and
patterning the polysilicon layer, the sacrificial layer and the mask layer.
3. The method of claim 1, wherein the metallic layer includes a tungsten layer.
4. The method of claim 1, wherein the sacrificial layer includes an oxide layer.
5. The method of claim 1, wherein the barrier layer includes a titanium/titanium nitride composite layer.
6. The method of claim 1, wherein material constituting the mask layer includes a material having a high etching selectivity ratio relative to the dielectric layer.
7. The method of claim 1, wherein the mask layer is made from polysilicon and the dielectric layer is made from silicon oxide.
8. The method of claim 1, wherein the step of planarizing the dielectric layer includes chemical-mechanical polishing.
9. The method of claim 1, wherein after the step of forming the gate structures further includes forming spacers on the sidewalls of the gate structures.
10. The method of claim 1, wherein the first type ions includes p-type ions and the second type ions includes n-type ions.
11. The method of claim 1, wherein after the step of forming the barrier layer over the substrate, further includes conducting an annealing operation.
12. The method of claim 11, wherein the annealing operation includes a rapid thermal process.
13. A method of forming a dual-implanted gate, comprising the steps of:
forming a plurality of stack structures on a substrate, wherein each stack structure comprises a polysilicon bottom layer and a sacrificial top layer;
forming a dielectric layer over the substrate between the stack structures, wherein the upper surface of the dielectric layer is at a level higher than the upper surface of the stack structures so that a trench structure is formed above the stack structures;
covering a portion of the stack structures and conducting a first ion implantation to implant p-type ions;
covering the p-type ion implanted stack structures to expose the other stack structures and conducting a second ion implantation to implant n-type ions;
removing the sacrificial top layer;
forming a barrier layer on the interior surface of the trenches;
forming a metallic layer in the trenches; and
removing the dielectric layer to form a plurality of gate structures.
14. The method of claim 13, wherein the metallic layer includes a tungsten layer.
15. The method of claim 13, wherein after forming the gate structures, further includes forming spacers on the sidewalls of the gate structures.
16. The method of claim 13, wherein the barrier layer includes a titanium/titanium nitride composite layer.
17. The method of claim 13, wherein after forming the barrier layer over the substrate, further includes conducting an annealing operation.
18. The method of claim 17, wherein the annealing operation includes a rapid thermal process.
19. A dual-implanted gate, comprising:
a stack structure on a substrate, the stack structure comprising a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer; and
a spacer formed on the stack layer over the substrate, the stack structure being enclosing by the spacer.
20. A dual-implanted gate, comprising:
a plurality of stack structures on a substrate, each of the stack structure comprising a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer; and
a plurality of spacers formed on the stack layers over the substrate, each of the stack structure being enclosing by the corresponding one of the spacers.
US10/064,372 2002-06-06 2002-07-08 Method of forming dual-implanted gate and structure formed by the same Expired - Lifetime US6673712B1 (en)

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Application Number Priority Date Filing Date Title
TW091112177A TW538467B (en) 2002-06-06 2002-06-06 Method of forming dual-implanted gate
US10/064,372 US6673712B1 (en) 2002-06-06 2002-07-08 Method of forming dual-implanted gate and structure formed by the same
DE10233421A DE10233421B4 (en) 2002-06-06 2002-07-23 Method for forming a double-implanted gate
US10/605,426 US20040104440A1 (en) 2002-06-06 2003-09-30 [method of forming dual-implanted gate and structure formed by the same]

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TW091112177A TW538467B (en) 2002-06-06 2002-06-06 Method of forming dual-implanted gate
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