US20030234421A1 - Structure of discrete nrom cell - Google Patents
Structure of discrete nrom cell Download PDFInfo
- Publication number
- US20030234421A1 US20030234421A1 US10/175,839 US17583902A US2003234421A1 US 20030234421 A1 US20030234421 A1 US 20030234421A1 US 17583902 A US17583902 A US 17583902A US 2003234421 A1 US2003234421 A1 US 2003234421A1
- Authority
- US
- United States
- Prior art keywords
- discrete
- nrom cell
- oxide layer
- ono
- cell according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 150000004767 nitrides Chemical class 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000002019 doping agent Substances 0.000 claims description 10
- -1 arsenic ions Chemical class 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical group [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 2
- 229910052698 phosphorus Inorganic materials 0.000 claims 2
- 239000011574 phosphorus Substances 0.000 claims 2
- 239000007943 implant Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 24
- 125000006850 spacer group Chemical group 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 238000012956 testing procedure Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the invention relates in general to a structure of nitride read-only memory (NROM) cells, and more particularly to the structure of discrete NROM cell fabricated according to the self-aligned process.
- NROM nitride read-only memory
- ROM read only memory
- PROM programmable read only memory
- EPROM erasable programmable read only memory
- EEPROM electrically erasable programmable read only memory
- NROM nitride read-only memory
- NROM N-ROM-ROM-ROM
- FIG. 1 is a cross-sectional view of a conventional NROM cell.
- the substrate 10 is implanted with a source 12 and a drain 14 .
- the top of substrate 10 lies an ONO structure, having a nitride layer 17 between a top oxide layer 16 and a bottom oxide layer (tunneling oxide layer) 18 .
- a numbers of BD (buried diffusion) oxide 20 are formed to isolate the adjacent ONO structure and form the channels 22 .
- the conventional structure of NROM cell in which contains dual bit in one cell is also depicted in FIG. 1.
- the larger region denotes a NROM cell 30
- the two smaller regions encircled with the dashed line denote the first bit 32 and the second bit 34 .
- the nitride layer 17 provides the charge retention mechanism for programming the memory cell. Under normal condition, the electrons are introduced into the nitride layer 17 during programming of the cell, while the holes are introduced into the nitride layer 17 to neutralize or combine the electrons during erasing of the cell. However, nitride tends to trap electrons that are introduced in the nitride layer 17 due to its property. If the electrons trapped in the nitride layer 17 , the cell is under programming.
- the conventional NROM cell is generally fabricated by photolithography, and has the drawback.
- the implant and the bits are not easily formed at the right position could be shifted, so that the efficiency of the NROM cell is decreased.
- the invention achieves the above-identified objects by providing a discrete NROM cell, at least comprising: a substrate; a first ONO stacking gate and a second ONO stacking gate over the substrate, wherein the ONO stacking gate is a structure having a nitride layer between two oxide layers; an oxide layer formed over the substrate and covering the first and second ONO stacking gates; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ONO stacking gates.
- FIG. 1 (prior art) is a cross-sectional view of a conventional NROM cell
- FIG. 2A-FIG. 2F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the first embodiment of the invention
- FIG. 2G is a cross-sectional view of the discrete NROM cell fabricated according to the first embodiment of the invention.
- FIG. 3A-FIG. 3F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the second embodiment of the invention.
- FIG. 3G is a cross-sectional view of the discrete NROM cell fabricated according to the second embodiment of the invention.
- the discrete NROM cell of the invention is fabricated by the self-aligned process. Two slightly different procedures are taken for illustrated in the disclosed embodiments. Also, to avoid obscuring the invention, well-known elements not directly relevant to the invention are not shown or described. Accordingly, the specification and the drawing are to be regard as an illustrative sense rather than a restrictive sense.
- FIG. 2A-FIG. 2F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the first embodiment of the invention.
- a substrate 210 is provided and an ONO layer is formed thereon.
- the ONO layer includes a bottom oxide layer (tunneling oxide layer) 218 grown on the substrate 210 , a nitride layer 217 deposited over the bottom oxide layer 218 , and a top oxide layer 216 produced on the nitride layer 217 .
- a patterned photo-resist (PR) 219 is formed over the top oxide layer 216 .
- PR photo-resist
- the thickness of the bottom oxide layer 218 typically ranges from 50 ⁇ to 150 ⁇ , and preferably about 70 ⁇ .
- the thickness of the nitride layer 217 typically ranges from 20 ⁇ to 150 ⁇ .
- the thickness of the top oxide layer 216 is not limited since it will be removed in the following procedures. However, it will be appreciated that the thickness of ONO layer are generally independent of each other, and variable depending on the field of NROM cell application.
- the top oxide layer 216 is etched according to the patterned PR 219 .
- the top oxide under the patterned PR 219 remains on while the others not be covered are etched away.
- the patterned PR 219 is removed as shown in FIG. 2B.
- a film is then formed over the top oxide layer 216 and portion of the nitride layer 217 by conformal deposition. Subsequently, the film is etched by anisotropic etching process, and the spacers 221 are formed on the sides of the discrete top oxide layer 216 .
- the film could be any material that can be differentiated from Nitride, such as oxide or polysilicon. Also, it is noted that the bottom width of the spacer 221 is controlled at a predetermined value (d).
- the source/drain 222 are implanted by self-aligned process.
- the source/drain 222 is a concentration of N-type dopant such as phosphorous or arsenic ions, or P-type dopant such as boron or boron fluoride ions(BF 2 + ).
- FIG. 2D the top oxide layer 216 and the nitride layer 217 are removed sequentially.
- the nitride sheltered by the spacers 221 remains on the bottom oxide while the other portions not covered by are etched away.
- the spacers 221 are removed, after that, the bottom oxide 218 is removed according to remaining nitride 217 , as shown in FIG. 2E.
- the nitride layer 217 and the bottom oxide layer 218 have been etched and formed as a plurality of stacking gates.
- an oxide layer 226 is formed over the substrate 210 , thereby the spaces between the discrete stacking gates are filled with the oxide, also the ONO stacking gates are fully covered.
- a polysilicon layer 228 is formed over the oxide layer 226 as a wordline.
- the polysilicon layer 228 can be amorphous silicon, or doped polysilicon that is doped by phosphorous or arsenic ions.
- the Tungsten Silicide (WSi x ) is subsequently deposited over the polysilicon layer 228 (not shown in FIG. 2F). The discrete NROM cell is then finished.
- FIG. 2G is a cross-sectional view of the discrete NROM cell fabricated according to the first embodiment of the invention.
- the substrate 210 is implanted with the source/drain 222 .
- the narrow stacking gate forming on the top of substrate 210 is an ONO layer having the nitride layer 217 between the oxide layer 216 and the bottom oxide layer 218 .
- the ONO stacking gates are separated by the oxide layer 226 ; consequently, the discrete structure of NROM cell is created.
- the oxide layer 226 is further capped by the polysilicon layer 228 .
- the larger encircled region denotes a NROM cell 230
- the two smaller encircled regions denote the first bit 232 and the second bit 233 .
- Two bits are controlled at a predetermined width (d). Also, the source/drain 222 is implanted by self-aligned process and the following steps are also performed by self-aligned process. Therefore, the symmetrical position of the source/drain 222 and the ONO layer can be easily and precisely controlled.
- FIG. 3A-FIG. 3F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the second embodiment of the invention.
- the fabricating method of the second embodiment is mostly the same as that of the first embodiment, but some of steps are slightly modified or changed in different orders.
- FIG. 3A The drawing of FIG. 3A is identical with FIG. 2A.
- a substrate 310 is first provided and a ONO structure including a top oxide layer 316 , a nitride layer 317 , and a bottom oxide layer (tunneling oxide layer) 318 is formed thereon.
- a patterned photo-resist (PR) 319 is formed over the top oxide layer 316 .
- the thickness of three layers of ONO structure are generally independent of each other, and variable depending on the field of NROM cell application.
- the top oxide layer 316 is etched according to the patterned PR 319 .
- the source/drain 322 are implanted by self-aligned process.
- the source/drain 322 is typically boron (B) or BF 2 + .
- the patterned PR 319 is de-scummed for exposing the portion of the top oxide layer 316 at the predetermined width of d, as illustrated in FIG. 3B.
- top oxide layer 316 is then etched according to the PR descum, and followed by removing PR 319 , as shown in FIG. 3C.
- a film is then formed over the top oxide layer 316 and the portion of the nitride layer 317 by conformal deposition. Subsequently, the film is etched by anisotropic etching process, and the spacers 321 are formed on the sides of the discrete top oxide layer 316 .
- the film could be any material that can be differentiated from Nitride, such as oxide or polysilicon. Also, it is noted that the bottom width of the spacer 321 is controlled at the predetermined value of d.
- the discrete top oxide layer 316 is removed.
- the nitride layer 317 is then etched according to the spacer 321 .
- the nitride sheltered by the spacers 321 remains on the bottom oxide layer 318 while the other portion not covered by is etched away.
- the spacers 321 are then removed, as shown in FIG. 3E.
- the bottom oxide layer 318 is etched according to the remained nitride layer 317 , and a plurality of ONO stacking gates are formed.
- an oxide layer 326 is formed over the substrate 310 and covers the ONO stacking gates.
- the oxide layer 326 is capped with a polysilicon layer 328 , as shown in FIG. 3F.
- the discrete NROM cell is then finished.
- FIG. 3G is a cross-sectional view of the discrete NROM cell fabricated according to the second embodiment of the invention.
- the substrate 310 is implanted with the source/drain 322 .
- Numerous narrow stacking gates forming on the top of substrate 310 are ONO structures having the nitride layer 317 between the oxide layer 316 and the bottom oxide layer 318 .
- the ONO stacking gates are separated by the oxide layer 326 ; consequently, the discrete structure of NROM cell is created.
- the oxide layer 326 is further capped by the polysilicon layer 328 .
- the larger encircled region denotes a NROM cell 330
- the two smaller encircled regions denote the first bit 332 and the second bit 333 .
- Two bits are controlled at the predetermined width of d.
- the source/drain 322 is implanted by self-aligned process and the following steps are also performed by self-aligned process. Therefore, the symmetrical position of the source/drain 322 and the ONO stacking gate can be easily and precisely controlled.
Abstract
A discrete NROM cell, at least comprising: a substrate; a first ONO stacking gate and a second ONO stacking gate over the substrate, wherein the ONO stacking gate is a structure having a nitride layer between two oxide layers; an oxide layer formed over the substrate covering the first and second ONO stacking gates; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ONO stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ONO structure at precisely symmetrical positions.
Description
- 1. Field of the Invention
- The invention relates in general to a structure of nitride read-only memory (NROM) cells, and more particularly to the structure of discrete NROM cell fabricated according to the self-aligned process.
- 2. Description of the Related Art
- The memory devices for non-volatile storage of information, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and other advanced memory devices, are currently used in the worldwide industries. The other advanced memory devices that involve more complex processing and testing procedures include electrically erasable programmable read only memory (EEPROM), flash EEPROM, and nitride read-only memory (NROM). These advanced memory devices can accomplish the tasks that ROM can't do. For example, using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device.
- The main characteristic of NROM is dual bit cells having multiple threshold voltage levels, where every two threshold voltage levels together store a different bit. Others store one bit on either side of the cell. The conventional structures and fabricating methods of NROM cell are described in a lot of articles and references.
- FIG. 1 is a cross-sectional view of a conventional NROM cell. The
substrate 10 is implanted with asource 12 and adrain 14. The top ofsubstrate 10 lies an ONO structure, having anitride layer 17 between atop oxide layer 16 and a bottom oxide layer (tunneling oxide layer) 18. A numbers of BD (buried diffusion)oxide 20 are formed to isolate the adjacent ONO structure and form thechannels 22. The conventional structure of NROM cell in which contains dual bit in one cell is also depicted in FIG. 1. The larger region (encircled with the dashed line) denotes aNROM cell 30, and the two smaller regions encircled with the dashed line denote thefirst bit 32 and thesecond bit 34. - In the NROM cell, the
nitride layer 17 provides the charge retention mechanism for programming the memory cell. Under normal condition, the electrons are introduced into thenitride layer 17 during programming of the cell, while the holes are introduced into thenitride layer 17 to neutralize or combine the electrons during erasing of the cell. However, nitride tends to trap electrons that are introduced in thenitride layer 17 due to its property. If the electrons trapped in thenitride layer 17, the cell is under programming. - Additionally, according to the hot electron injection phenomenon, some hot electrons will penetrate through the
bottom oxide layer 18, especially when it is thin, and then collected in thenitride layer 17. Concentrated charge caused by the hot electrons significantly raises the threshold voltage of the portion of thechannel 22 under charge to be higher than the threshold voltage of the remaining portion of thechannel 22. When the cell is programmed, the concentrated charge is presented and the raised threshold voltage does not permit the cell to the conductive state. In a normal state, which the concentrated charge is not presented, the reading voltage over the channel can overcome the threshold voltage of thechannel 22 and consequently thechannel 22 is conductive. - Moreover, the conventional NROM cell is generally fabricated by photolithography, and has the drawback. For example, the implant and the bits are not easily formed at the right position could be shifted, so that the efficiency of the NROM cell is decreased.
- It is therefore an object of the invention to provide a structure of discrete NROM cell, so that the symmetrical positions of the source/drain implant and ONO structure can be precisely controlled.
- The invention achieves the above-identified objects by providing a discrete NROM cell, at least comprising: a substrate; a first ONO stacking gate and a second ONO stacking gate over the substrate, wherein the ONO stacking gate is a structure having a nitride layer between two oxide layers; an oxide layer formed over the substrate and covering the first and second ONO stacking gates; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ONO stacking gates.
- Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
- FIG. 1 (prior art) is a cross-sectional view of a conventional NROM cell;
- FIG. 2A-FIG. 2F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the first embodiment of the invention;
- FIG. 2G is a cross-sectional view of the discrete NROM cell fabricated according to the first embodiment of the invention;
- FIG. 3A-FIG. 3F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the second embodiment of the invention; and
- FIG. 3G is a cross-sectional view of the discrete NROM cell fabricated according to the second embodiment of the invention.
- The discrete NROM cell of the invention is fabricated by the self-aligned process. Two slightly different procedures are taken for illustrated in the disclosed embodiments. Also, to avoid obscuring the invention, well-known elements not directly relevant to the invention are not shown or described. Accordingly, the specification and the drawing are to be regard as an illustrative sense rather than a restrictive sense.
-
Method 1 for Fabricating NROM Cell - FIG. 2A-FIG. 2F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the first embodiment of the invention. In FIG. 2A, a
substrate 210 is provided and an ONO layer is formed thereon. The ONO layer includes a bottom oxide layer (tunneling oxide layer) 218 grown on thesubstrate 210, anitride layer 217 deposited over thebottom oxide layer 218, and atop oxide layer 216 produced on thenitride layer 217. Then, a patterned photo-resist (PR) 219 is formed over thetop oxide layer 216. - The thickness of the
bottom oxide layer 218 typically ranges from 50 Å to 150 Å, and preferably about 70 Å. The thickness of thenitride layer 217 typically ranges from 20 Å to 150 Å. The thickness of thetop oxide layer 216 is not limited since it will be removed in the following procedures. However, it will be appreciated that the thickness of ONO layer are generally independent of each other, and variable depending on the field of NROM cell application. - Next, the
top oxide layer 216 is etched according to the patternedPR 219. The top oxide under the patternedPR 219 remains on while the others not be covered are etched away. Then, thepatterned PR 219 is removed as shown in FIG. 2B. - As illustrated by FIG. 2C, a film is then formed over the
top oxide layer 216 and portion of thenitride layer 217 by conformal deposition. Subsequently, the film is etched by anisotropic etching process, and thespacers 221 are formed on the sides of the discretetop oxide layer 216. The film could be any material that can be differentiated from Nitride, such as oxide or polysilicon. Also, it is noted that the bottom width of thespacer 221 is controlled at a predetermined value (d). - Then, the source/
drain 222 are implanted by self-aligned process. The source/drain 222 is a concentration of N-type dopant such as phosphorous or arsenic ions, or P-type dopant such as boron or boron fluoride ions(BF2 +). - In FIG. 2D, the
top oxide layer 216 and thenitride layer 217 are removed sequentially. The nitride sheltered by thespacers 221 remains on the bottom oxide while the other portions not covered by are etched away. Then, thespacers 221 are removed, after that, thebottom oxide 218 is removed according to remainingnitride 217, as shown in FIG. 2E. - As far as the process describe, the
nitride layer 217 and thebottom oxide layer 218 have been etched and formed as a plurality of stacking gates. In FIG. 2F, anoxide layer 226 is formed over thesubstrate 210, thereby the spaces between the discrete stacking gates are filled with the oxide, also the ONO stacking gates are fully covered. - Following oxide deposition, a
polysilicon layer 228 is formed over theoxide layer 226 as a wordline. Thepolysilicon layer 228 can be amorphous silicon, or doped polysilicon that is doped by phosphorous or arsenic ions. Also, in the particular process, the Tungsten Silicide (WSix) is subsequently deposited over the polysilicon layer 228 (not shown in FIG. 2F). The discrete NROM cell is then finished. - Structure of NROM Cell in the First Embodiment
- FIG. 2G is a cross-sectional view of the discrete NROM cell fabricated according to the first embodiment of the invention. The
substrate 210 is implanted with the source/drain 222. The narrow stacking gate forming on the top ofsubstrate 210 is an ONO layer having thenitride layer 217 between theoxide layer 216 and thebottom oxide layer 218. Also, the ONO stacking gates are separated by theoxide layer 226; consequently, the discrete structure of NROM cell is created. Theoxide layer 226 is further capped by thepolysilicon layer 228. The larger encircled region denotes aNROM cell 230, and the two smaller encircled regions denote thefirst bit 232 and thesecond bit 233. Two bits are controlled at a predetermined width (d). Also, the source/drain 222 is implanted by self-aligned process and the following steps are also performed by self-aligned process. Therefore, the symmetrical position of the source/drain 222 and the ONO layer can be easily and precisely controlled. - Method2 for Fabricating NROM Cell
- FIG. 3A-FIG. 3F illustrate the method of fabricating the discrete NROM cell by self-aligned process according to the second embodiment of the invention. The fabricating method of the second embodiment is mostly the same as that of the first embodiment, but some of steps are slightly modified or changed in different orders.
- The drawing of FIG. 3A is identical with FIG. 2A. In FIG. 3A, a
substrate 310 is first provided and a ONO structure including atop oxide layer 316, anitride layer 317, and a bottom oxide layer (tunneling oxide layer) 318 is formed thereon. Then, a patterned photo-resist (PR) 319 is formed over thetop oxide layer 316. Similarly, the thickness of three layers of ONO structure are generally independent of each other, and variable depending on the field of NROM cell application. - The
top oxide layer 316 is etched according to thepatterned PR 319. After that, the source/drain 322 are implanted by self-aligned process. The source/drain 322 is typically boron (B) or BF2 +. Then, thepatterned PR 319 is de-scummed for exposing the portion of thetop oxide layer 316 at the predetermined width of d, as illustrated in FIG. 3B. - The
top oxide layer 316 is then etched according to the PR descum, and followed by removingPR 319, as shown in FIG. 3C. - As illustration of FIG. 3D, a film is then formed over the
top oxide layer 316 and the portion of thenitride layer 317 by conformal deposition. Subsequently, the film is etched by anisotropic etching process, and thespacers 321 are formed on the sides of the discretetop oxide layer 316. The film could be any material that can be differentiated from Nitride, such as oxide or polysilicon. Also, it is noted that the bottom width of thespacer 321 is controlled at the predetermined value of d. - Next, the discrete
top oxide layer 316 is removed. Thenitride layer 317 is then etched according to thespacer 321. The nitride sheltered by thespacers 321 remains on thebottom oxide layer 318 while the other portion not covered by is etched away. Thespacers 321 are then removed, as shown in FIG. 3E. Subsequently, thebottom oxide layer 318 is etched according to the remainednitride layer 317, and a plurality of ONO stacking gates are formed. - Then, an
oxide layer 326 is formed over thesubstrate 310 and covers the ONO stacking gates. - Then, the
oxide layer 326 is capped with apolysilicon layer 328, as shown in FIG. 3F. The discrete NROM cell is then finished. - Structure of NROM Cell in the Second Embodiment
- FIG. 3G is a cross-sectional view of the discrete NROM cell fabricated according to the second embodiment of the invention. The
substrate 310 is implanted with the source/drain 322. Numerous narrow stacking gates forming on the top ofsubstrate 310 are ONO structures having thenitride layer 317 between theoxide layer 316 and thebottom oxide layer 318. Also, the ONO stacking gates are separated by theoxide layer 326; consequently, the discrete structure of NROM cell is created. Theoxide layer 326 is further capped by thepolysilicon layer 328. The larger encircled region denotes aNROM cell 330, and the two smaller encircled regions denote thefirst bit 332 and thesecond bit 333. Two bits are controlled at the predetermined width of d. Also, the source/drain 322 is implanted by self-aligned process and the following steps are also performed by self-aligned process. Therefore, the symmetrical position of the source/drain 322 and the ONO stacking gate can be easily and precisely controlled. - While the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims (20)
1. A structure of discrete NROM cell, at least comprising:
a substrate;
a plurality of ONO stacking gates over the substrate, wherein the ONO stacking gate is a structure having a nitride layer between two oxide layers;
an oxide layer formed over the substrate and covering the ONO stacking gates;
a polysilicon layer formed over the oxide layer; and
a plurality of source/drain implanted in the substrate and next to the ONO stacking gates.
2. The structure of discrete NROM cell according to claim 1 , wherein the ONO stacking gate includes a top oxide layer, a nitride layer, and a bottom oxide layer.
3. The structure of discrete NROM cell according to claim 2 , wherein the thickness of the nitride layer ranges from about 20 Å to 150 Å.
4. The structure of discrete NROM cell according to claim 2 , wherein the thickness of the bottom oxide layer ranges from 50 Å to 150 Å.
5. The structure of discrete NROM cell according to claim 4 , wherein the bottom oxide layer is preferably about 70 Å.
6. The structure of discrete NROM cell according to claim 1 , wherein the polysilicon layer is doped by phosphorus or arsenic ions.
7. The structure of discrete NROM cell according to claim 1 , wherein the source/drain of NROM cell is a concentration of P-type dopant.
8. The structure of discrete NROM cell according to claim 7 , wherein the P-type dopant is Boron or BF2 +.
9. The structure of discrete NROM cell according to claim 1 , wherein the source/drain of NROM cell is a concentration of N-type dopant.
10. The structure of discrete NROM cell according to claim 9 , wherein the N-type dopant is phosphorous or arsenic ions.
11. A discrete NROM cell, at least comprising:
a substrate;
a first ONO stacking gate and a second ONO stacking gate over the substrate, wherein the ONO stacking gate is a structure having a nitride layer between two oxide layers;
an oxide layer formed over the substrate and covering the first ONO stacking gate and the second ONO stacking gate;
a polysilicon layer formed over the oxide layer; and
a source/drain implanted in the substrate and next to the first ONO stacking gate and the second ONO stacking gate.
12. The discrete NROM cell according to claim 11 , wherein the ONO stacking gate includes a top oxide layer, a nitride layer, and a bottom oxide layer.
13. The discrete NROM cell according to claim 11 , wherein the polysilicon layer is doped by phosphorus or arsenic ions.
14. The discrete NROM cell according to claim 11 , wherein a first bit and a second bit are in the virtual position of the first ONO stacking gate and the second ONO stacking gate, respectively.
15. The discrete NROM cell according to claim 12 , wherein the thickness of the nitride layer ranges from about 20 Å to 150 Å.
16. The structure of discrete NROM cell according to claim 12 , wherein the thickness of the bottom oxide layer ranges from 50 Å to 150 Å.
17. The structure of discrete NROM cell according to claim 11 , wherein the source/drain of NROM cell is a concentration of P-type dopant.
18. The structure of discrete NROM cell according to claim 17 , wherein the P-type dopant is Boron or BF2 +.
19. The structure of discrete NROM cell according to claim 11 , wherein the source/drain of NROM cell is a concentration of N-type dopant.
20. The structure of discrete NROM cell according to claim 19 , wherein the N-type dopant is phosphorous or arsenic ions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/175,839 US6670672B1 (en) | 2002-06-21 | 2002-06-21 | Structure of discrete NROM cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/175,839 US6670672B1 (en) | 2002-06-21 | 2002-06-21 | Structure of discrete NROM cell |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030234421A1 true US20030234421A1 (en) | 2003-12-25 |
US6670672B1 US6670672B1 (en) | 2003-12-30 |
Family
ID=29733989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/175,839 Expired - Lifetime US6670672B1 (en) | 2002-06-21 | 2002-06-21 | Structure of discrete NROM cell |
Country Status (1)
Country | Link |
---|---|
US (1) | US6670672B1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357134A (en) * | 1991-10-31 | 1994-10-18 | Rohm Co., Ltd. | Nonvolatile semiconductor device having charge trap film containing silicon crystal grains |
US6218700B1 (en) * | 1997-10-29 | 2001-04-17 | Stmicroelectronics S.A. | Remanent memory device |
US6477084B2 (en) * | 1998-05-20 | 2002-11-05 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
US6531735B1 (en) * | 1999-09-17 | 2003-03-11 | Hitachi, Ltd. | Semiconductor integrated circuit |
US20030075773A1 (en) * | 2001-10-16 | 2003-04-24 | Christoph Deml | Semiconductor memory device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5266509A (en) * | 1990-05-11 | 1993-11-30 | North American Philips Corporation | Fabrication method for a floating-gate field-effect transistor structure |
JPH0555596A (en) * | 1991-08-22 | 1993-03-05 | Rohm Co Ltd | Semiconductor nonvolatile memory device |
JPH05283710A (en) * | 1991-12-06 | 1993-10-29 | Intel Corp | High-voltage mos transistor and manufacture thereof |
-
2002
- 2002-06-21 US US10/175,839 patent/US6670672B1/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357134A (en) * | 1991-10-31 | 1994-10-18 | Rohm Co., Ltd. | Nonvolatile semiconductor device having charge trap film containing silicon crystal grains |
US6218700B1 (en) * | 1997-10-29 | 2001-04-17 | Stmicroelectronics S.A. | Remanent memory device |
US6477084B2 (en) * | 1998-05-20 | 2002-11-05 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
US6531735B1 (en) * | 1999-09-17 | 2003-03-11 | Hitachi, Ltd. | Semiconductor integrated circuit |
US20030075773A1 (en) * | 2001-10-16 | 2003-04-24 | Christoph Deml | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
US6670672B1 (en) | 2003-12-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6201282B1 (en) | Two bit ROM cell and process for producing same | |
JP3966707B2 (en) | Semiconductor device and manufacturing method thereof | |
US7795088B2 (en) | Method for manufacturing memory cell | |
KR20030019917A (en) | Memory cell, memory cell device and method for the production thereof | |
US5814543A (en) | Method of manufacturing a semicondutor integrated circuit device having nonvolatile memory cells | |
JP2004015051A (en) | Non-volatile memory cell, memory element, and method for manufacturing non-volatile memory cell | |
US5851879A (en) | Method for fabricating compact contactless trenched flash memory cell | |
US6797565B1 (en) | Methods for fabricating and planarizing dual poly scalable SONOS flash memory | |
US7838350B2 (en) | Bottom-gate sonos-type cell having a silicide gate | |
US6620693B2 (en) | Non-volatile memory and fabrication thereof | |
US6885070B2 (en) | Semiconductor memory device and fabrication method thereof | |
US7238974B2 (en) | Semiconductor device and method of producing a semiconductor device | |
US6982202B2 (en) | Fabrication method for memory cell | |
US20050145919A1 (en) | [multi-level memory cell] | |
US20050082600A1 (en) | [non-volatile memory device and method of manufacturing the same] | |
US20080080249A1 (en) | Non-volatile memory, fabricating method and operating method thereof | |
US20150054048A1 (en) | Split-Gate Non-Volatile Memory Cells Having Gap Protection Zones | |
JP4443108B2 (en) | Semiconductor device manufacturing method and device | |
US7714374B2 (en) | Structure and fabrication method of flash memory | |
US7450424B2 (en) | Method for reading a memory array with a non-volatile memory structure | |
US6706598B2 (en) | Method of fabricating discrete NROM cell by self aligned process | |
US6670672B1 (en) | Structure of discrete NROM cell | |
US7759726B2 (en) | Non-volatile memory device, non-volatile memory cell thereof and method of fabricating the same | |
US20080020529A1 (en) | Non-volatile memory and fabrication thereof | |
CN1328793C (en) | Structure of discontinuous nitride ROM memory cell |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, KENT KUOHUA;LAI, ERH-KUN;REEL/FRAME:013034/0469 Effective date: 20020508 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |