US20030067322A1 - Multi-threshold flip-flop circuit having an outside feedback - Google Patents
Multi-threshold flip-flop circuit having an outside feedback Download PDFInfo
- Publication number
- US20030067322A1 US20030067322A1 US09/682,716 US68271601A US2003067322A1 US 20030067322 A1 US20030067322 A1 US 20030067322A1 US 68271601 A US68271601 A US 68271601A US 2003067322 A1 US2003067322 A1 US 2003067322A1
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- flop circuit
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- 229910044991 metal oxide Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
- H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
Abstract
A multi-threshold flip-flop circuit having an outside feedback is disclosed. The multi-threshold flip-flop circuit comprises a master latch and a slave latch. Coupled between an output of the slave latch and an input of the master latch, a switchable feedback path is utilized to retain logical values of the slave latch during a sleep mode of the flip-flop circuit.
Description
- 1. Technical Field
- The present invention relates to logic circuits in general, and in particular to flip-flop circuits. Still more particularly, the present invention relates to a multi-threshold flip-flop circuit having an outside feedback.
- 2. Description of the Prior Art
- In order to maintain high performances in electronic devices having a scaled-down power supply voltage, threshold voltages for transistors within the electronic devices need to be scaled down also. However, a lower threshold voltage will give rise to a higher subthreshold leakage current. Especially for battery-powered electronic devices, the relative level of leakage currents increases even more during sleep mode. One solution for reducing the amount of current leakage in sleep mode is to use a circuit commonly known as multi-threshold complementary-metal-oxide semiconductor (MTCMOS) circuit. Generally speaking, a MTCMOS circuit uses low-threshold transistors during active mode but cuts off supply voltage during sleep mode. Such switching scheme works well for combinational circuits but not for sequential circuits because a latch or flip-flop circuit will lose its logical state when the supply voltage is turned off.
- Several solutions have been utilized to tackle the problem of losing logical state in MTCMOS sequential circuits. Most of those solutions are generally based on duplicating the regular flip-flop circuit structure with some form of “shadow” or “balloon” latch. A duplicate latch can be built with high-threshold transistors that will keep the logical states of transistors during sleep mode. However, all the prior art solutions typically result in circuits having significant increased complexity with a large chip area overhead. In addition, most prior art solutions have non-trivial issues related to saving and restoring state. Consequently, it would be desirable to provide an improved flip-flop circuit with relatively low subthreshold leakage currents.
- In accordance with a preferred embodiment of the present invention, a flip-flop circuit includes a master latch having a forward MTCMOS inverter and a feedback standard inverter, and a slave latch having a forward MTCMOS inverter and a feedback standard inverter. A first switch is connect to an input of the master latch. A second switch is connected between an output of the master latch and an input of the slave latch. A third switch is connected between an output of the slave latch and the input of the master latch.
- All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
- The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
- FIG. 1 is a circuit diagram of a typical master-slave flip-flop circuit, according to the prior art;
- FIG. 2 is a circuit diagram of a master-slave flip-flop circuit, in accordance with a preferred embodiment of the present invention;
- FIG. 3 is a circuit diagram of a MTCMOS inverter within the flip-flop circuit from FIG. 2, in accordance with a preferred embodiment of the present invention; and
- FIG. 4 is a circuit diagram of a standard inverter within the flip-flop circuit from FIG. 2, in accordance with a preferred embodiment of the present invention.
- Detailed Description of a Preferred Embodiment
- Referring now to the drawings and in particular to FIG. 1, there is depicted a circuit diagram of a typical master-slave flip-flop circuit, according to the prior art. As shown, a flip-flop circuit10 includes a master latch 11 and a
slave latch 12. Flip-flop circuit 10 has two clock phases, namely, {umlaut over (l)}†1 and {umlaut over (l)}†2. Switches S1 and S2, which can be pass gates or pass transistors, are activated by clock phases {umlaut over (l)}†1 and {umlaut over (l)}†2, respectively. By convention, a switch is closed when the clock is at a logical high (i.e., a logical one), and the switch is opened when the clock is at a logical low (i.e., a logical zero). For flip-flop circuit 10 to function correctly, clock phases {umlaut over (l)}†1 and {umlaut over (l)}†2 need to be non-overlapping (i.e., off-phase with each other). When clock phase {umlaut over (l)}†1 is high, master latch 11 is transparent andslave latch 12 is in store mode during which a data value from a previous clock cycle is being stored. When clock phase {umlaut over (l)}†2 becomes high, master latch 11 is in store mode andslave latch 12 is transparent. Inverters 13-16 used in flip-flop circuit 10 typically have different sizes. For example, the sizes of inverters 13 and 14 are usually larger than the sizes ofinverters 15 and 16. The reason that the sizes of inverters 13 and 14 being relatively larger is because the forward path of flip-flop circuit 10 is critical for performance while the feedback path of flip-flop circuit 10 is necessary only for preserving its logical state. - With reference now to FIG. 2, there is depicted a circuit diagram of a master-slave flip-flop circuit, in accordance with a preferred embodiment of the present invention. As shown, flip-
flop circuit 20 includes amaster latch 51 and aslave latch 52. The input ofmaster latch 51 is connected to the input of flip-flop circuit 20 via a first switch S1. The input ofslave latch 52 is connected to the output ofmaster latch 51 via a second switch S2. The output ofslave latch 52 is connected to the input ofmaster latch 51 via a third switch S3. The output ofslave latch 52 is also the output of flip-flop circuit 20. Flip-flop circuit 20 has two clock phasesâ″{umlaut over (l)}†1 and {umlaut over (l)}†2. First switch S1 and second switch S2, which can be pass gates or pass transistors, are activated by clock phases {umlaut over (l)}†1 and {umlaut over (l)}†2, respectively. Clock phases {umlaut over (l)}†1 and {umlaut over (l)}†2 are non-overlapping. Third switch S3 is activated by a SLEEP signal. A switch is closed when a controlling signal, such as a clock phase or SLEEP signal, is at a logical high (i.e., a logical one), and the switch is opened when the controlling signal is at a logical low (i.e., a logical zero). -
Master latch 51 is comprised of a multi-threshold complementary-metal-oxide semiconductor (MTCMOS)inverter 21 coupled to astandard inverter 22. Similarly,slave latch 52 is comprised of aMTCMOS inverter 23 coupled to astandard inverter 24. Thus,inverters inverters inverters inverter 21 will be explained in further details. Referring now to FIG. 3, there is depicted a circuit diagram ofMTCMOS inverter 21, in accordance with a preferred embodiment of the present invention. As shown, MTCMOSinverter 21 includes two p-channel transistors channel transistors 32, 34 in series.Transistors Transistors 33 and 34 are high-threshold transistors intended to be utilized as gating transistors for cutting off power supply totransistors transistors 33 and 34 are turned off such thattransistors - Because
standard inverters standard inverter 22 will be further explained. With reference now to FIG. 4, there is depicted a circuit diagram ofstandard inverter 22, in accordance with a preferred embodiment of the present invention. As shown,standard inverter 22 includes a p-channel transistor 41 connected to an n-channel transistor 42 in series. The operation ofstandard inverter 22 is well-known to those skilled in the art. - Flip-
flop circuit 20 in FIG. 2 functions as follows. During active mode of operation, the SLEEP signal is de-asserted, which means third switch S3 is open and all gating transistors G1, G2, G3, and G4 are turned on, flip-flop circuit 20 behaves like a regular master-slave flip-flop, similar to flip-flop 10 in FIG. 1. When clock phase {umlaut over (l)}†1 is high during active mode,master latch 51 is transparent andslave latch 52 is in store mode. When clock phase {umlaut over (l)}†2 is high during active mode,master latch 51 is in store mode andslave latch 52 is transparent. - Flip-
flop circuit 20 should enter and exit sleep mode when clock phase {umlaut over (l)}†1 is low and clock phase {umlaut over (l)}†2 is high. Clock phase {umlaut over (l)}†2 also needs to remain high during the entire sleep mode. Sleep mode can be entered simply by asserting the SLEEP signal when clock phase {umlaut over (l)}†1 is low and clock phase {umlaut over (l)}†2 is high. The assertion of the SLEEP signal closes third switch S3 and turns off all gating transistors G1, G2, G3, and G4, which effectively shuts off the power supply toMTCMOS inverters MTCMOS inverters flop circuit 20 is now preserved by the loop formed bystandard inverter 24, second switch S2,standard inverter 22, and third switch S3. At this point, there is not going to be any major current leakage from any transistors within flip-flop circuit 20 because transistors withinstandard inverters MTCMOS inverters - Returning to active mode from sleep mode can simply be done by de-asserting the SLEEP signal. The de-asserting of the SLEEP signal will open third switch S3 and turns on all gating transistors, and the logical state of flip-
flop circuit 20 will be restored to the logical state before entering sleep mode. It is important to note that closing and opening third switch S3 will not lead to any race condition since the output and the input ofmaster latch 51 are identical (either both high or both low) when clock phase {umlaut over (l)}†1 is low and clock phase {umlaut over (l)}†2 is high as required when entering and exiting sleep mode. - There are several salient features to flip-
flop circuit 20. First, only the inverters on the forward path (i.e.,inverter 21 and inverter 23) need to be fast and hence be implemented with MTCMOS inverters.Standard inverters flop circuit 20; thus,standard inverters master latch 51, forming an outside feedback. The outside feedback path formed with third switch S3 and the regular high-threshold feedback inverters flop circuit 20 during sleep mode. First switch S1 is closed when clock phase {umlaut over (l)}†1 is active, second switch S2 is closed when clock phase {umlaut over (l)}†2 is active, third switch S3 is closed when SLEEP signal is asserted. Third, both switches S1 and S2 are implemented with low-threshold transistors for high speed. - As has been described, the present invention provides a multi-threshold flip-flop circuit having an outside feedback. The flip-flop circuit of the present invention keeps its logical state by using an outside feedback from the output of a slave latch to the input of a master latch. Compared to the prior art flip-flop circuits, the present invention uses a minimal area overhead and has no negative impact on performance.
- Although the description of the present invention is related to a master-slave flip-flop structure, it should be understood by those skilled in the art that the concept of the present invention can be applicable to other flip-flop circuits. For example, there may be extra switches on the internal feedbacks for the master and slave latches, or the feedback may have another topology. The outside feedback idea can be applicable to all those cases but a more complex control may be needed to fully close the outside feedback loop. Also, the present invention can also be easily adapted to level sensitive scan design (LSSD) style flip-flop circuits.
- While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (17)
1. A flip-flop circuit comprising:
a master latch;
a slave latch; and
a switchable feedback path, coupled between an output of said slave latch and an input of said master latch, for retaining logical values of said slave latch during a sleep mode of said flip-flop circuit.
2. The flip-flop circuit of claim 1 , wherein said flip-flop circuit further includes a first switch between an input of said flip-flop circuit and said input of said master latch.
3. The flip-flop circuit of claim 2 , wherein said flip-flop circuit further includes a second switch between and an output of said master latch and an input of said slave latch.
4. The flip-flop circuit of claim 1 , wherein said switchable feedback path further includes a third switch.
5. The flip-flop circuit of claim 4 , wherein said third switch is closed during said sleep mode.
6. The flip-flop circuit of claim 1 , wherein said master latch further includes a MTCMOS inverter coupled to a standard inverter.
7. The flip-flop circuit of claim 6 , wherein said MTCMOS inverter further includes a plurality of high-threshold active transistors and a plurality of low-threshold gating transistors.
8. The flip-flop circuit of claim 1 , wherein said slave latch further includes a MTCMOS inverter coupled to a standard inverter.
9. The flip-flop circuit of claim 8 , wherein said MTCMOS inverter further includes a plurality of high-threshold active transistors and a plurality of low-threshold gating transistors.
10. A flip-flop circuit comprising:
a first switch connected to an input of said flip-flop circuit;
a master latch having a forward MTCMOS inverter and a feedback standard inverter;
a slave latch having a forward MTCMOS inverter and a feedback standard inverter;
a second switch connected between an output of said master latch and an input of said slave latch; and
a third switch connected between an output of said slave latch and said input of said master latch.
11. The flip-flop circuit of claim 10 , wherein said MTCMOS inverter in said master latch further includes low-threshold active transistors and high-threshold gating transistors.
12. The flip-flop circuit of claim 10 , wherein said MTCMOS inverter in said slave latch further includes low-threshold active transistors and high-threshold gating transistors.
13. The flip-flop circuit of claim 10 , wherein said feedback standard inverter in said master latch further include high-threshold transistors.
14. The flip-flop circuit of claim 10 , wherein said feedback standard inverter in said slave latch further include high-threshold transistors.
15. The flip-flop circuit of claim 10 , wherein said first switch is a low-threshold transistor.
16. The flip-flop circuit of claim 10 , wherein said second switch is a low-threshold transistor.
17. The flip-flop circuit of claim 10 , wherein said third switch is a high-threshold transistor.
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US09/682,716 US6538471B1 (en) | 2001-10-10 | 2001-10-10 | Multi-threshold flip-flop circuit having an outside feedback |
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---|---|---|---|---|
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US20050285918A1 (en) * | 2004-06-28 | 2005-12-29 | Mcelligott Michael J | Multiple pass aqueous MICR inkjet ink printing |
US20060233293A1 (en) * | 2005-04-19 | 2006-10-19 | Semiconductor Energy Laboratory Co., Ltd. | Shift register, display device, and electronic device |
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US7183825B2 (en) | 2004-04-06 | 2007-02-27 | Freescale Semiconductor, Inc. | State retention within a data processing system |
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US20100011278A1 (en) * | 2008-07-10 | 2010-01-14 | Kerry Bernstein | Soft Error Correction in Sleeping Processors |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6794914B2 (en) * | 2002-05-24 | 2004-09-21 | Qualcomm Incorporated | Non-volatile multi-threshold CMOS latch with leakage control |
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US7391249B2 (en) * | 2005-12-07 | 2008-06-24 | Electronics And Telecommunications Research Institute | Multi-threshold CMOS latch circuit |
US7420403B2 (en) * | 2005-12-08 | 2008-09-02 | Electronics And Telecommunications Research Institute | Latch circuit and flip-flop |
US7414485B1 (en) | 2005-12-30 | 2008-08-19 | Transmeta Corporation | Circuits, systems and methods relating to dynamic ring oscillators |
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US8067970B2 (en) * | 2006-03-31 | 2011-11-29 | Masleid Robert P | Multi-write memory circuit with a data input and a clock input |
US7495466B1 (en) * | 2006-06-30 | 2009-02-24 | Transmeta Corporation | Triple latch flip flop system and method |
US7710153B1 (en) | 2006-06-30 | 2010-05-04 | Masleid Robert P | Cross point switch |
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US11558041B1 (en) * | 2021-08-08 | 2023-01-17 | SambaNova Systems, Inc. | Fast clocked storage element |
US11552622B1 (en) | 2022-03-23 | 2023-01-10 | SambaNova Systems, Inc. | High-performance flip-flop |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4182961A (en) * | 1976-09-27 | 1980-01-08 | Rca Corporation | Inhibitable counter stage and counter |
US4506167A (en) | 1982-05-26 | 1985-03-19 | Motorola, Inc. | High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gates |
JPS62150589A (en) | 1985-12-25 | 1987-07-04 | Hitachi Ltd | Dynamic ram |
US5081377A (en) * | 1990-09-21 | 1992-01-14 | At&T Bell Laboratories | Latch circuit with reduced metastability |
JPH07183771A (en) | 1993-12-22 | 1995-07-21 | Fujitsu Ltd | Flip-flop circuit |
JPH10261946A (en) | 1997-03-19 | 1998-09-29 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
US6097230A (en) * | 1997-12-08 | 2000-08-01 | Texas Instruments Deutschland Gmbh | Clock-independent latch setup-and-hold time in a combined D-type latch and flip-flop |
-
2001
- 2001-10-10 US US09/682,716 patent/US6538471B1/en not_active Expired - Fee Related
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US20070263426A1 (en) * | 2006-02-10 | 2007-11-15 | Takashi Hiraga | Optical flip-flop circuit |
US7346820B2 (en) | 2006-03-23 | 2008-03-18 | Freescale Semiconductor, Inc. | Testing of data retention latches in circuit devices |
US20070226561A1 (en) * | 2006-03-23 | 2007-09-27 | Freescale Semiconductor, Inc. | Testing of data retention latches in circuit devices |
US7646210B2 (en) * | 2007-01-05 | 2010-01-12 | International Business Machines Corporation | Method and system for low-power level-sensitive scan design latch with power-gated logic |
JP2008172770A (en) * | 2007-01-05 | 2008-07-24 | Internatl Business Mach Corp <Ibm> | Method and system for low-power level-sensitive scan design latch with power-gated logic |
TWI425228B (en) * | 2007-01-05 | 2014-02-01 | Ibm | Method and system for low-power level-sensitive scan design latch with power-gated logic |
US20080164912A1 (en) * | 2007-01-05 | 2008-07-10 | Zhibin Cheng | Method and system for low-power level-sensitive scan design latch with power-gated logic |
US20100011278A1 (en) * | 2008-07-10 | 2010-01-14 | Kerry Bernstein | Soft Error Correction in Sleeping Processors |
US8234554B2 (en) | 2008-07-10 | 2012-07-31 | International Business Machines Corporation | Soft error correction in sleeping processors |
GB2489304B (en) * | 2011-03-10 | 2015-07-08 | Advanced Risc Mach Ltd | Storage circuitry and method with increased resilience to single event upsets |
US20140002161A1 (en) * | 2012-07-02 | 2014-01-02 | Klaus Von Arnim | Circuit arrangement, a retention flip-flop, and methods for operating a circuit arrangement and a retention flip-flop |
CN103532540A (en) * | 2012-07-02 | 2014-01-22 | 英特尔移动通信有限责任公司 | Circuit means for operating and holding the trigger and maintain the trigger circuit means method |
WO2016037004A1 (en) * | 2014-09-03 | 2016-03-10 | Texas Instruments Incorporated | Low leakage shadow latch-based multi-threshold cmos sequential circuit |
WO2022125399A3 (en) * | 2020-12-10 | 2022-07-14 | Qualcomm Incorporated | Fault resilient flip-flop with balanced topology and negative feedback |
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