US20030016579A1 - Memory read circuitry - Google Patents
Memory read circuitry Download PDFInfo
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- US20030016579A1 US20030016579A1 US09/908,667 US90866701A US2003016579A1 US 20030016579 A1 US20030016579 A1 US 20030016579A1 US 90866701 A US90866701 A US 90866701A US 2003016579 A1 US2003016579 A1 US 2003016579A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- the present invention generally relates to data processing systems. More specifically, the present invention relates to memory systems, precharge circuitry and read circuitry.
- register files that include a large number of registers.
- Such register files may include multiple read and write access ports. As a result, the register file can be quite large.
- a semiconductor memory typically includes a memory cell array that has a grid of bitlines and wordlines, with memory cells located at intersections of the bitlines and the wordlines. During operation, the bitlines and the wordlines are selectively asserted and negated to enable at least one of the memory cells to be read or written.
- bitlines lengths and loading have driven increases in bitlines lengths and loading.
- the additional lengths of the bitlines and the device count per bitline add wire and diffusion capacitance to an already highly capacitive environment. As a result, additional time is required to charge and discharge this extra capacitance. Such additional time equates to increased read and write times and hence, slower performance.
- FIG. 1 A prior art split bitline read circuit is shown in FIG. 1.
- the read circuit includes a first local bitline, which would typically be coupled to a first group of memory cells (not shown).
- the read circuit also includes a second local bitline, which would typically be connected to a second group of memory cells (not shown).
- the local bitlines are connected to a local sense amp, which, as shown in FIG. 1, is a NAND gate 101 .
- the first local bitline will be precharged through p-type metal oxide semiconductor (PMOS) transistor 102 when the precharge signal is low.
- the second local bitline will be precharged through PMOS transistor 103 and the global bitline will be precharged high through PMOS transistor 104 when the precharge signal is low.
- grounding the precharge signal precharges the first bitline, the second bitline, and the global bitline.
- a local bitline such as the first local bitline
- the local bitline will be discharged if and only if the memory cell is in a logic low state.
- the output of the NAND gate will be conditionally high and the global bitline will be conditionally pulled to ground by the NMOS transistor 105 .
- the global bitline contains the value read from the memory cell.
- PMOS transistor 104 and NMOS transistor 105 can both be active at the same time and a current, known as a crowbar current, can flow from V DD , through PMOS transistor 104 and NMOS transistor 105 , to ground. In addition to wasting power and generating heat, this crowbar current can also result in electro-migration related reliability issues.
- FIG. 2 A prior art bitline read circuit that eliminates the above-discussed crowbar current is shown in FIG. 2.
- This read circuit is similar to the circuit shown in FIG. 1, except that an n-type metal oxide semiconductor (NMOS) transistor is placed in series with NMOS transistor 205 . Because PMOS transistor 204 and NMOS transistor 206 are never both activated, the crowbar current is eliminated.
- NMOS n-type metal oxide semiconductor
- the read circuit shown in FIG. 2 eliminates the crowbar current, the read circuit is not optimal.
- the size of the read circuit shown in FIG. 2 is larger than the read circuit shown in FIG. 1.
- the size of the NMOS transistor 205 and the NAND 201 must be increased.
- the NMOS transistor 206 must rapidly pull down the global bitline, which may be highly loaded, its size must be significant.
- the addition of the NMOS transistor 206 in the read circuit shown in FIG. 2 increases the loading of the precharge line.
- One embodiment of the invention is a circuit on a semiconductor for precharging a local bitline and a global bitline.
- the circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
- the read circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to a local bitline; a first delay element, the input of the first delay element coupled to the precharge input; a second delay element, the input of the second delay element coupled to the output of the first delay element; a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline; a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source; a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground; a fifth switch, the gate of the fifth switch coupled to the bitline, the source of the fifth switch coupled to the
- the above read circuit includes: a seventh switch, the gate of the seventh switch coupled to the global bitline, the drain of the seventh switch coupled to the gate of the sixth switch, the source of the seventh switch coupled to ground; and an eighth switch, the gate of the eighth switch coupled to the gate of the sixth switch, the source of the eighth switch coupled to the voltage source, the drain of the eighth switch coupled to the local bitline.
- the read circuit described in the preceding paragraph includes: a ninth switch, the gate of the ninth switch coupled to the precharge input, the source of the ninth switch coupled to the voltage source, the drain of the ninth switch coupled to the second local bitline; a tenth switch, the gate of the tenth switch coupled to the gate of the sixth switch, the source of the tenth switch coupled to the voltage source, the drain of the tenth switch coupled to the second local bitline; and an eleventh switch, the gate of the eleventh switch coupled to the second local bitline, the source of the eleventh switch coupled to the drain of the third switch, the drain of the eleventh switch is coupled to the gate of the sixth switch.
- Still another embodiment of the invention is a computer system.
- the computer system includes a central processing unit.
- the central processing unit includes a circuit on a semiconductor for precharging a local bitline and a global bitline.
- the circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
- the DRAM includes a circuit on a semiconductor for precharging a local bitline and a global bitline.
- the circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
- FIG. 1 presents a prior art read circuit.
- FIG. 2 presents a second prior art read circuit.
- FIG. 3 presents one embodiment of an improved read circuit.
- FIG. 4 presents a second embodiment of an improved read circuit.
- FIG. 5 presents a computer system that includes an improved read circuit.
- FIG. 3 presents an improved read circuit 300 .
- the read circuit 300 includes a precharge input 301 .
- the read circuit 300 also includes a first switch 302 .
- the first switch is a PMOS transistor.
- the gate of the first switch is coupled to the precharge input 301 .
- the source of the first switch is coupled to a voltage source, V DD .
- the drain of the first switch 302 is coupled to a local bitline 303 .
- the read circuit 300 also includes a first delay element 304 .
- the first delay element 304 is an inverter.
- the input of the first delay element 304 is coupled to the precharge input 301 .
- the read circuit 300 also includes a second switch 305 .
- the second switch 305 is a PMOS transistor.
- the gate of the second switch 305 is coupled to the output of the first delay element 304 .
- the gate of the second switch 305 is directly coupled to the output of the first delay element 304 .
- the gate of the second switch 305 is indirectly coupled to the output of the first delay element 304 by one or more additional components.
- the source of the second switch 305 is coupled to V DD .
- the drain of the second switch 305 is coupled to a global bitline 306 .
- the read circuit 300 includes a second delay element 307 .
- the second delay element 307 is an inverter.
- the input of the second delay element 307 is coupled to the output of the first delay element 304 .
- the output of the second delay element 307 is directly coupled to the gate of the second switch 305 .
- the precharge input 301 When the precharge input 301 is in a low logic state, the local bitline 303 is precharged through the first switch 302 . Similarly, when the precharge input 301 is in a low logic state, the global bitline 306 is precharged through the second switch 305 after a delay created by the first delay element 304 and the second delay element 307 .
- the read circuit 300 also includes a third switch 308 .
- the third switch 308 is a PMOS transistor.
- the gate of the third switch 308 is coupled to the output of the first delay element 304 .
- the source of the third switch 308 is coupled to V DD .
- the read circuit 300 also includes a fourth switch 309 .
- the fourth switch 309 is an NMOS transistor.
- the gate of the fourth switch 309 is coupled to the output of the first delay element 304 .
- the source of the fourth switch 309 is coupled to ground.
- the read circuit 300 also includes a fifth switch 310 .
- the fifth switch 310 is a PMOS transistor.
- the gate of the fifth switch 310 is coupled to the local bitline 303 .
- the source of the fifth switch 310 is coupled to the drain of the third switch 308 .
- the drain of the fifth switch 310 is coupled to the drain of the fourth switch 309 .
- the read circuit 300 also includes a sixth switch 311 .
- the sixth switch 311 is an NMOS transistor.
- the gate of the sixth switch 311 is coupled to the drain of the fifth switch 310 .
- the drain of the sixth switch 311 is coupled to the global bitline 306 .
- the source of the sixth switch 311 is coupled to ground.
- the read circuit 300 includes a seventh switch 312 .
- the seventh switch 312 is an NMOS transistor.
- the gate of the seventh switch 312 is coupled to the global bitline 306 .
- the drain of the seventh switch is coupled to the gate of the sixth switch.
- the source of the seventh switch is coupled to ground.
- the read circuit 300 also includes an eighth switch 313 .
- the eighth switch 313 is a PMOS transistor.
- the gate of the eighth switch 313 is coupled to the gate of the sixth switch 311 .
- the source of the eighth switch 313 is coupled to V DD .
- the drain of the eighth switch 313 is coupled to the local bitline 303 .
- the sixth switch 311 will be ON only when the signal connected to the gate of switch 308 is low. This signal turns OFF switch 305 . Therefore, switches 305 and 311 are never ON at the same time. This is true even if the timing between the local bitline 303 and the precharge input 301 is different due to timing mismatches. Thus, the read circuit 300 eliminates the crowbar current without addition of the footer device and resulting overheads.
- Read circuit 300 includes a single local bitline 303 .
- other embodiments of the invention include multiple bitlines.
- read circuit 400 as shown in FIG. 4, includes a first local bitline 403 and second local bitline 414 .
- read circuit 400 includes a ninth switch 415 .
- the ninth switch 415 is a PMOS transistor.
- the gate of the ninth switch 415 is coupled to the precharge input 401 .
- the source of the ninth switch 415 is coupled to V DD .
- the drain of the ninth switch 415 is coupled to the second local bitline 415 .
- Read circuit 400 also includes a tenth switch 416 .
- the tenth switch 416 is a PMOS transistor.
- the gate of the tenth switch 416 is coupled to the gate of the sixth switch 411 .
- the source of the tenth switch 416 is coupled to V DD .
- the drain of the tenth switch 416 is coupled to the second local bitline 414 .
- Read circuit 400 also includes an eleventh switch 417 .
- the eleventh switch 417 is a PMOS transistor.
- the gate of the eleventh switch 417 is coupled to the second local bitline 414 .
- the source of the eleventh switch 417 is coupled to the drain of the third switch 408 .
- the drain of the eleventh switch 417 is coupled to the gate of the sixth switch 411 .
- the second switch 405 and the sixth switch 411 can never both pass current at the same time.
- the read circuit 400 also eliminates the crowbar current.
- FIG. 5 shows a computer system 500 that includes a computer 505 .
- Computer 505 may include a central processor (CPU) 510 , a read only memory (ROM) 515 , random access memory (RAM) 520 , such as DRAM, SDRAM, RDRAM, or RLDRAM, an audio system 525 , a digital versatile disk (DVD) drive 530 , a floppy disk drive 535 , a hard disk drive 540 , and a compact disk (CD) drive 545 .
- the computer 505 may be coupled to a mouse 550 , a keyboard 555 , a network device 560 , a speaker 565 , and a display monitor 570 .
- the above-described read circuits 300 and 400 may be included in the CPU's register file. In addition the read circuits 300 and 400 may be included in the ROM 515 and/or the RAM 520 . Further, the read circuits 300 and 400 may be included in any subsystem that accesses memory such as the network device 560 .
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Abstract
Description
- The present invention generally relates to data processing systems. More specifically, the present invention relates to memory systems, precharge circuitry and read circuitry.
- As technology advances, memories in semiconductor devices have become larger and more advanced. The number of memory cells on Dynamic Random Access Memories is ever increasing. In addition, modern microprocessors utilize register files that include a large number of registers. Such register files may include multiple read and write access ports. As a result, the register file can be quite large.
- A semiconductor memory typically includes a memory cell array that has a grid of bitlines and wordlines, with memory cells located at intersections of the bitlines and the wordlines. During operation, the bitlines and the wordlines are selectively asserted and negated to enable at least one of the memory cells to be read or written.
- Increasing demands for larger memories have driven increases in bitlines lengths and loading. The additional lengths of the bitlines and the device count per bitline add wire and diffusion capacitance to an already highly capacitive environment. As a result, additional time is required to charge and discharge this extra capacitance. Such additional time equates to increased read and write times and hence, slower performance.
- To decrease the bitline capacitance, prior art memory systems split the bitline into global bitlines and local bitlines. One example of such a memory system is shown in U.S. Pat. No. 6,058,065 to Lattimore.
- A prior art split bitline read circuit is shown in FIG. 1. The read circuit includes a first local bitline, which would typically be coupled to a first group of memory cells (not shown). The read circuit also includes a second local bitline, which would typically be connected to a second group of memory cells (not shown). The local bitlines are connected to a local sense amp, which, as shown in FIG. 1, is a NAND
gate 101. - As is shown in FIG. 1, the first local bitline will be precharged through p-type metal oxide semiconductor (PMOS)
transistor 102 when the precharge signal is low. Similarly, the second local bitline will be precharged throughPMOS transistor 103 and the global bitline will be precharged high throughPMOS transistor 104 when the precharge signal is low. Thus, grounding the precharge signal precharges the first bitline, the second bitline, and the global bitline. - When a memory cell is desired to be read, a local bitline, such as the first local bitline, will be conditionally discharged based upon the content of the memory cell, i.e., the local bitline will be discharged if and only if the memory cell is in a logic low state. As a result, the output of the NAND gate will be conditionally high and the global bitline will be conditionally pulled to ground by the
NMOS transistor 105. As a result, the global bitline contains the value read from the memory cell. - Due to differences in physical locations of drivers, different gate and wire loads, and/or variations due to manufacturing processes, voltages and temperatures, it is possible that the timing of the local bitlines and the precharge signals can vary. Therefore, under some circumstances,
PMOS transistor 104 andNMOS transistor 105 can both be active at the same time and a current, known as a crowbar current, can flow from VDD, throughPMOS transistor 104 andNMOS transistor 105, to ground. In addition to wasting power and generating heat, this crowbar current can also result in electro-migration related reliability issues. - A prior art bitline read circuit that eliminates the above-discussed crowbar current is shown in FIG. 2. This read circuit is similar to the circuit shown in FIG. 1, except that an n-type metal oxide semiconductor (NMOS) transistor is placed in series with
NMOS transistor 205. BecausePMOS transistor 204 andNMOS transistor 206 are never both activated, the crowbar current is eliminated. - Even though the read circuit shown in FIG. 2 eliminates the crowbar current, the read circuit is not optimal. First, the size of the read circuit shown in FIG. 2 is larger than the read circuit shown in FIG. 1. In order to maintain the same performance, the size of the
NMOS transistor 205 and the NAND 201 must be increased. Also, because theNMOS transistor 206 must rapidly pull down the global bitline, which may be highly loaded, its size must be significant. Second, the addition of theNMOS transistor 206 in the read circuit shown in FIG. 2 increases the loading of the precharge line. - Thus, a need exists for an improved read circuit.
- One embodiment of the invention is a circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
- Another embodiment of the invention is a read circuit on a semiconductor. The read circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to a local bitline; a first delay element, the input of the first delay element coupled to the precharge input; a second delay element, the input of the second delay element coupled to the output of the first delay element; a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline; a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source; a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground; a fifth switch, the gate of the fifth switch coupled to the bitline, the source of the fifth switch coupled to the drain of the third switch, the drain of the fifth switch coupled to the drain of the fourth switch; and a sixth switch, the gate of the sixth switch coupled to the drain of the fifth switch, the drain of the sixth switch coupled to the global bitline, the source of the sixth switch coupled to ground.
- In still another embodiment, the above read circuit includes: a seventh switch, the gate of the seventh switch coupled to the global bitline, the drain of the seventh switch coupled to the gate of the sixth switch, the source of the seventh switch coupled to ground; and an eighth switch, the gate of the eighth switch coupled to the gate of the sixth switch, the source of the eighth switch coupled to the voltage source, the drain of the eighth switch coupled to the local bitline.
- In still another embodiment, the read circuit described in the preceding paragraph includes: a ninth switch, the gate of the ninth switch coupled to the precharge input, the source of the ninth switch coupled to the voltage source, the drain of the ninth switch coupled to the second local bitline; a tenth switch, the gate of the tenth switch coupled to the gate of the sixth switch, the source of the tenth switch coupled to the voltage source, the drain of the tenth switch coupled to the second local bitline; and an eleventh switch, the gate of the eleventh switch coupled to the second local bitline, the source of the eleventh switch coupled to the drain of the third switch, the drain of the eleventh switch is coupled to the gate of the sixth switch.
- Still another embodiment of the invention is a computer system. The computer system includes a central processing unit. The central processing unit includes a circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
- Yet still another embodiment of the invention is a Dynamic Random Access Device (DRAM). The DRAM includes a circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
- FIG. 1 presents a prior art read circuit.
- FIG. 2 presents a second prior art read circuit.
- FIG. 3 presents one embodiment of an improved read circuit.
- FIG. 4 presents a second embodiment of an improved read circuit.
- FIG. 5 presents a computer system that includes an improved read circuit.
- The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
- 5.1 Improved Read Circuit
- FIG. 3 presents an
improved read circuit 300. Theread circuit 300 includes aprecharge input 301. Theread circuit 300 also includes afirst switch 302. In this embodiment, the first switch is a PMOS transistor. The gate of the first switch is coupled to theprecharge input 301. The source of the first switch is coupled to a voltage source, VDD. The drain of thefirst switch 302 is coupled to alocal bitline 303. - The
read circuit 300 also includes afirst delay element 304. In this embodiment, thefirst delay element 304 is an inverter. The input of thefirst delay element 304 is coupled to theprecharge input 301. - The
read circuit 300 also includes asecond switch 305. In this embodiment, thesecond switch 305 is a PMOS transistor. The gate of thesecond switch 305 is coupled to the output of thefirst delay element 304. In some embodiments of the invention, the gate of thesecond switch 305 is directly coupled to the output of thefirst delay element 304. In other embodiments, as shown in FIG. 3, the gate of thesecond switch 305 is indirectly coupled to the output of thefirst delay element 304 by one or more additional components. The source of thesecond switch 305 is coupled to VDD. The drain of thesecond switch 305 is coupled to aglobal bitline 306. - Referring again to FIG. 3, the
read circuit 300 includes asecond delay element 307. In one embodiment of the invention, thesecond delay element 307 is an inverter. The input of thesecond delay element 307 is coupled to the output of thefirst delay element 304. The output of thesecond delay element 307 is directly coupled to the gate of thesecond switch 305. - When the
precharge input 301 is in a low logic state, thelocal bitline 303 is precharged through thefirst switch 302. Similarly, when theprecharge input 301 is in a low logic state, theglobal bitline 306 is precharged through thesecond switch 305 after a delay created by thefirst delay element 304 and thesecond delay element 307. - The
read circuit 300 also includes athird switch 308. In one embodiment of the invention, thethird switch 308 is a PMOS transistor. The gate of thethird switch 308 is coupled to the output of thefirst delay element 304. The source of thethird switch 308 is coupled to VDD. - The
read circuit 300 also includes afourth switch 309. In one embodiment of the invention, thefourth switch 309 is an NMOS transistor. The gate of thefourth switch 309 is coupled to the output of thefirst delay element 304. The source of thefourth switch 309 is coupled to ground. - The
read circuit 300 also includes afifth switch 310. In one embodiment of the invention, thefifth switch 310 is a PMOS transistor. The gate of thefifth switch 310 is coupled to thelocal bitline 303. The source of thefifth switch 310 is coupled to the drain of thethird switch 308. The drain of thefifth switch 310 is coupled to the drain of thefourth switch 309. - The
read circuit 300 also includes asixth switch 311. In one embodiment of the invention, thesixth switch 311 is an NMOS transistor. The gate of thesixth switch 311 is coupled to the drain of thefifth switch 310. The drain of thesixth switch 311 is coupled to theglobal bitline 306. The source of thesixth switch 311 is coupled to ground. - Referring again to FIG. 3, the
read circuit 300 includes aseventh switch 312. In one embodiment of the invention, theseventh switch 312 is an NMOS transistor. The gate of theseventh switch 312 is coupled to theglobal bitline 306. The drain of the seventh switch is coupled to the gate of the sixth switch. The source of the seventh switch is coupled to ground. - The
read circuit 300 also includes aneighth switch 313. In one embodiment theeighth switch 313 is a PMOS transistor. The gate of theeighth switch 313 is coupled to the gate of thesixth switch 311. The source of theeighth switch 313 is coupled to VDD. The drain of theeighth switch 313 is coupled to thelocal bitline 303. - As is evident from FIG. 3, the
sixth switch 311 will be ON only when the signal connected to the gate ofswitch 308 is low. This signal turns OFFswitch 305. Therefore, switches 305 and 311 are never ON at the same time. This is true even if the timing between thelocal bitline 303 and theprecharge input 301 is different due to timing mismatches. Thus, theread circuit 300 eliminates the crowbar current without addition of the footer device and resulting overheads. - 5.2 Improved Read Circuit with Two Bitline Inputs
-
Read circuit 300 includes a singlelocal bitline 303. However, other embodiments of the invention include multiple bitlines. For example, readcircuit 400, as shown in FIG. 4, includes a firstlocal bitline 403 and secondlocal bitline 414. - In addition to the electrical components included in
read circuit 300, readcircuit 400 includes aninth switch 415. In one embodiment, theninth switch 415 is a PMOS transistor. The gate of theninth switch 415 is coupled to theprecharge input 401. The source of theninth switch 415 is coupled to VDD. The drain of theninth switch 415 is coupled to the secondlocal bitline 415. -
Read circuit 400 also includes atenth switch 416. In one embodiment of the invention, thetenth switch 416 is a PMOS transistor. The gate of thetenth switch 416 is coupled to the gate of thesixth switch 411. The source of thetenth switch 416 is coupled to VDD. The drain of thetenth switch 416 is coupled to the secondlocal bitline 414. -
Read circuit 400 also includes an eleventh switch 417. In one embodiment of the invention, the eleventh switch 417 is a PMOS transistor. The gate of the eleventh switch 417 is coupled to the secondlocal bitline 414. The source of the eleventh switch 417 is coupled to the drain of thethird switch 408. The drain of the eleventh switch 417 is coupled to the gate of thesixth switch 411. - As is evident from FIG. 4, the
second switch 405 and thesixth switch 411 can never both pass current at the same time. Thus, just as withread circuit 300, theread circuit 400 also eliminates the crowbar current. - 5.3 Computer System Utilizing an Improved Read Circuit
- The above-described
read circuits computer system 500 that includes acomputer 505.Computer 505 may include a central processor (CPU) 510, a read only memory (ROM) 515, random access memory (RAM) 520, such as DRAM, SDRAM, RDRAM, or RLDRAM, anaudio system 525, a digital versatile disk (DVD) drive 530, afloppy disk drive 535, ahard disk drive 540, and a compact disk (CD)drive 545. In addition, thecomputer 505 may be coupled to amouse 550, akeyboard 555, anetwork device 560, aspeaker 565, and adisplay monitor 570. - The above-described
read circuits circuits ROM 515 and/or theRAM 520. Further, the readcircuits network device 560. - 5.4 Conclusion
- The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.
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US10241499B1 (en) * | 2015-02-11 | 2019-03-26 | Lightforce Orthodontics, Inc. | Ceramic processing for the direct manufacture of customized labial and lingual orthodontic brackets |
US10930340B2 (en) * | 2017-04-20 | 2021-02-23 | Socionext Inc. | Semiconductor storage circuit, semiconductor storage apparatus, and data detection method |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US6707721B2 (en) * | 2002-03-13 | 2004-03-16 | Sun Microsystems, Inc. | Low power memory design with asymmetric bit line driver |
US7280401B2 (en) * | 2003-07-10 | 2007-10-09 | Telairity Semiconductor, Inc. | High speed data access memory arrays |
US7362621B2 (en) * | 2003-09-30 | 2008-04-22 | Intel Corporation | Register file with a selectable keeper circuit |
US20060176747A1 (en) * | 2005-02-09 | 2006-08-10 | International Business Machines Corporation | Circuit for interfacing local bitlines with global bitline |
US7170774B2 (en) * | 2005-02-09 | 2007-01-30 | International Business Machines Corporation | Global bit line restore timing scheme and circuit |
US7355881B1 (en) | 2005-11-22 | 2008-04-08 | Advanced Micro Devices, Inc. | Memory array with global bitline domino read/write scheme |
US7376027B1 (en) * | 2006-11-07 | 2008-05-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | DRAM concurrent writing and sensing scheme |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6125051A (en) * | 1997-12-12 | 2000-09-26 | Hyundai Electronics Industries Co., Ltd. | Circuit for driving nonvolatile ferroelectric memory |
US5892725A (en) | 1998-05-13 | 1999-04-06 | International Business Machines Corporation | Memory in a data processing system having uneven cell grouping on bitlines and method therefor |
US6215692B1 (en) | 1998-05-13 | 2001-04-10 | Hyundai Electronics Industries Co., Ltd. | Non-volatile ferroelectric memory |
US6058065A (en) | 1998-05-21 | 2000-05-02 | International Business Machines Corporation | Memory in a data processing system having improved performance and method therefor |
US6081458A (en) | 1998-08-26 | 2000-06-27 | International Business Machines Corp. | Memory system having a unidirectional bus and method for communicating therewith |
KR100287882B1 (en) | 1998-11-03 | 2001-05-02 | 김영환 | Nonvolatile Ferroelectric Memory Device |
US6373753B1 (en) * | 1999-02-13 | 2002-04-16 | Robert J. Proebsting | Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD |
US6157584A (en) * | 1999-05-20 | 2000-12-05 | Advanced Micro Devices, Inc. | Redundancy circuit and method for semiconductor memory |
US6538932B2 (en) * | 2001-06-13 | 2003-03-25 | International Business Machines Corporation | Timing circuit and method for a compilable DRAM |
-
2001
- 2001-07-17 US US09/908,667 patent/US6512712B1/en not_active Expired - Lifetime
-
2002
- 2002-11-15 US US10/295,953 patent/US6597611B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10241499B1 (en) * | 2015-02-11 | 2019-03-26 | Lightforce Orthodontics, Inc. | Ceramic processing for the direct manufacture of customized labial and lingual orthodontic brackets |
US10930340B2 (en) * | 2017-04-20 | 2021-02-23 | Socionext Inc. | Semiconductor storage circuit, semiconductor storage apparatus, and data detection method |
Also Published As
Publication number | Publication date |
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US6597611B2 (en) | 2003-07-22 |
US6512712B1 (en) | 2003-01-28 |
US20030067823A1 (en) | 2003-04-10 |
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