US20030013298A1 - Coupling capacitance reduction - Google Patents
Coupling capacitance reduction Download PDFInfo
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- US20030013298A1 US20030013298A1 US10/171,701 US17170102A US2003013298A1 US 20030013298 A1 US20030013298 A1 US 20030013298A1 US 17170102 A US17170102 A US 17170102A US 2003013298 A1 US2003013298 A1 US 2003013298A1
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- electrically conductive
- interconnect lines
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- conductive layer
- conductive interconnect
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- 230000008878 coupling Effects 0.000 title claims abstract description 10
- 238000010168 coupling process Methods 0.000 title claims abstract description 10
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 10
- 239000011800 void material Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 230000000379 polymerizing effect Effects 0.000 claims 6
- 238000007517 polishing process Methods 0.000 claims 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- 229910000077 silane Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron halide Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical class C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates generally to the field of integrated circuit fabrication, and in particular the invention relates to reducing the coupling capacitance between closely spaced electrically conductive interconnect lines, or in other words reducing the effective dielectric constant of the material between closely spaced electrically conductive interconnect lines.
- Highly conductive materials such as metals, are often used for forming the electrically conductive interconnect lines of integrated circuits.
- the capacitance between closely spaced interconnects tends to increase, causing a generally commensurate increase in cross talk and power dissipation between adjacent interconnect lines.
- Cross talk is the signal interference between electrically conductive interconnect lines, which tends to adversely affect signal integrity and signal strength.
- Power dissipation is the dynamic power drained by unwanted capacitance charging and discharging in a circuit.
- a conductive layer is deposited on a substrate, and etched to define electrically conductive interconnect lines having negatively sloped sidewalls.
- the negatively sloping sidewalls of adjacent electrically conductive interconnect lines form undercut gaps in the conductive layer.
- An insulating layer is deposited on the etched conductive layer using a directional physical vapor deposition to cover the undercut gaps and form a void in each of the undercut gaps. The void is directly adjacent the negative sloping sidewalls of adjacent electrically conductive interconnect lines.
- the invention provides an integrated circuit having closely spaced electrically conductive interconnect lines.
- a void is formed between and directly adjacent undercut sidewalls of adjacent electrically conductive interconnect lines.
- the void preferably has a dielectric constant that is less than about two.
- An advantage of the invention is that it provides an integrated circuit having air gaps between electrically conductive interconnect lines so that more closely spaced interconnect lines can be provided on a substrate surface. Furthermore, the dielectric constant of the void between adjacent interconnect lines tends to be substantially lower than those of the insulating materials that are typically used, such as silicon oxide. Because of the negatively sloping sidewalls of the adjacent interconnect lines, the void space in the gap is preferably relatively high, resulting in a relatively small effective dielectric constant, which in turn results in a substantially lower effective capacitance between adjacent electrically conductive interconnect lines.
- FIG. 1 is a cross sectional view of an electrically conductive layer on a substrate
- FIG. 2 is a cross sectional view of the electrically conductive layer on a substrate with a patterned layer of photoresist
- FIG. 3 is a cross sectional view of an etched electrically conductive layer on a substrate
- FIG. 4 is a cross sectional view of negatively sloped sidewalls of adjacent electrically conductive interconnect lines
- FIG. 5 is a cross sectional view of a layer sealing a void between adjacent electrically conductive interconnect lines
- FIG. 4 is a cross sectional view of the planarized layer over the void.
- the integrated circuit 10 preferably includes one or more active or passive elements that are electrically connected by electrically conductive interconnect lines
- An electrically conductive material such as gold, aluminum, copper, tin, tantalum, titanium, platinum, tungsten, molybdenum, polysilicon, or a mixture or alloy of two or more of the foregoing is deposited on a substrate 12 to provide an electrically conductive layer 14 .
- the electrically conductive layer 14 is preferably substantially evenly deposited over the whole surface of the substrate 12 .
- the substrate 12 may further comprise a plurality of various layers. Most preferably, the topmost layer of the substrate 12 on which the electrically conductive layer 14 is deposited is a non electrically conductive, or insulating layer.
- a masking layer 16 such as photoresist, is deposited on the conductive layer 14 .
- the masking layer 16 is preferably patterned using conventional photolithography techniques to provide an opening 18 in the masking layer 16 , which opening 18 corresponds to the spacing between adjacent interconnect lines that are to be formed in the conductive layer 14 .
- gap 20 between adjacent electrically conductive interconnect lines is formed in the conductive layer 14 by a process such as plasma etching the conductive layer 14 through the opening 18 in the masking layer 16 .
- Etching of the conductive layer 14 is preferably conducted in a manner whereby the sidewalls 22 of the gap 20 have a negative slope, or in other words, where the sidewalls 22 of the gap 20 are closer together at the top of the gap 20 than they are at the bottom of the gap 20 .
- the gap 20 may be plasma etched in the absence of a magnetic field.
- polymer forming gases such as halogenated methane and the like are used to form polymeric substances on the sidewalls 22 of the conductive layer 14 as they start to be formed, thereby passivating the upper portions of the sidewalls 22 so that boron halide species such as BCl 3 anisotropically etch the conductive layer 14 .
- the plasma chamber is purposefully depleted of polymer forming gases so that the lower portions of the sidewalls 22 of the conductive layer 14 are not passivated.
- the conductive layer 14 is etched isotropically, resulting in undercut regions and negatively sloping sidewalls 22 as illustrated in FIG. 3.
- the process produces a gap 20 in the conductive layer 14 , where the width 24 at the top of the gap 20 is substantially smaller than the width 26 at the bottom of the gap 20 .
- the etching process thus produces ledges or overhangs 28 in the conductive layer 14 at the top of the gap 20 , as depicted in FIG. 4.
- the overhangs 28 preferably enable the formation of a sealed void 34 in the conductive layer 14 , as depicted in FIG. 5.
- a dielectric layer 30 is preferably deposited on top of the etched conductive layer 14 under conditions sufficient to form the void 34 in the gap 20 .
- the dielectric layer 30 is preferably a layer of substantially non electrically conductive material such as, but not limited to silicon nitride, silicon oxide such as silicon dioxide, boron nitride, and silicon carbide.
- a particularly preferred dielectric layer 30 is a silicon oxide layer deposited with a modified silane physical vapor deposition process.
- the deposition reactor in which the dielectric layer 30 is deposited is preferably detuned and highly directional to provide poor step coverage of the dielectric layer 30 over the gap 20 in the conductive layer 14 . Accordingly, a deposit 32 of the dielectric material may be deposited in the gap 20 . However, the portions of gap 20 directly adjacent the sidewalls 22 of the conductive layer 14 are filled with the void 34 created in the gap 20 . In other words, the dielectric material 32 formed at the bottom of the gap 20 preferably does not substantially contact the sidewalls 22 of the conductive layer 14 .
- the void 34 is not filled with any solid material.
- the void 34 preferably extends substantially completely across the gap 20 between the negatively sloping sidewalls 22 of the gap 20 , as depicted in FIG. 5.
- the deposited dielectric material 32 may contact the layer 30 of dielectric material, as depicted in FIG. 6.
- the void 34 may be filled with any one of a number of gases, such as the precursor gases used during the deposition process whereby the dielectric layer 30 was formed. Most preferably the void 34 is filled with air.
- a gas that has a dielectric constant that is preferably less than the dielectric constant of the insulating material used to form the dielectric layer 30 , which for the materials most commonly used is no less than about two the capacitive coupling between adjacent interconnect lines is preferably commensurately reduced.
- the effective dielectric constant of the void 34 is preferably between about one and about one and a half.
- the gas within the void 34 may be at a pressure that is alternately greater than, less than, or substantially equal to atmospheric pressure.
- the dielectric layer 30 is preferably planarized, such as with a chemical mechanical polish, as depicted in FIG. 6. Additional layers may be selectively deposited on the planarized dielectric layer 30 and the process of etching the layers is repeated to create an integrated circuit having relatively low coupling capacitance between adjacent interconnect lines.
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
- This invention relates generally to the field of integrated circuit fabrication, and in particular the invention relates to reducing the coupling capacitance between closely spaced electrically conductive interconnect lines, or in other words reducing the effective dielectric constant of the material between closely spaced electrically conductive interconnect lines.
- During fabrication of an integrated circuit, a variety of layers of electrically insulating materials and electrically conducting materials are typically deposited on a substrate. The layers are patterned by selectively removing portions of the layers, to form the desired electrical circuits. The need for faster and more complex integrated circuits provides incentive to decrease the size of the integrated circuits. As the size of the integrated circuit decreases, the size of the electrically conductive interconnects between the various components of the integrated circuit also tends to decrease. For proper performance of the integrated circuit, it is desirable to maintain high reliability and low electrical resistance while decreasing both the size of the electrical interconnects and the spacing between adjacent electrical interconnects.
- Highly conductive materials, such as metals, are often used for forming the electrically conductive interconnect lines of integrated circuits. As the size of and spacing between the electrically conductive interconnect lines decreases, the capacitance between closely spaced interconnects tends to increase, causing a generally commensurate increase in cross talk and power dissipation between adjacent interconnect lines. Cross talk is the signal interference between electrically conductive interconnect lines, which tends to adversely affect signal integrity and signal strength. Power dissipation is the dynamic power drained by unwanted capacitance charging and discharging in a circuit.
- What is needed, therefore, is a method for reducing coupling capacitance between adjacent electrically conductive interconnect lines in an integrated circuit.
- These and other needs are provided by a method for reducing the coupling capacitance between electrically conductive interconnect lines of an integrated circuit. A conductive layer is deposited on a substrate, and etched to define electrically conductive interconnect lines having negatively sloped sidewalls. The negatively sloping sidewalls of adjacent electrically conductive interconnect lines form undercut gaps in the conductive layer. An insulating layer is deposited on the etched conductive layer using a directional physical vapor deposition to cover the undercut gaps and form a void in each of the undercut gaps. The void is directly adjacent the negative sloping sidewalls of adjacent electrically conductive interconnect lines.
- In another aspect the invention provides an integrated circuit having closely spaced electrically conductive interconnect lines. A void is formed between and directly adjacent undercut sidewalls of adjacent electrically conductive interconnect lines. The void preferably has a dielectric constant that is less than about two.
- An advantage of the invention is that it provides an integrated circuit having air gaps between electrically conductive interconnect lines so that more closely spaced interconnect lines can be provided on a substrate surface. Furthermore, the dielectric constant of the void between adjacent interconnect lines tends to be substantially lower than those of the insulating materials that are typically used, such as silicon oxide. Because of the negatively sloping sidewalls of the adjacent interconnect lines, the void space in the gap is preferably relatively high, resulting in a relatively small effective dielectric constant, which in turn results in a substantially lower effective capacitance between adjacent electrically conductive interconnect lines.
- Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:
- FIG. 1 is a cross sectional view of an electrically conductive layer on a substrate,
- FIG. 2 is a cross sectional view of the electrically conductive layer on a substrate with a patterned layer of photoresist,
- FIG. 3 is a cross sectional view of an etched electrically conductive layer on a substrate,
- FIG. 4 is a cross sectional view of negatively sloped sidewalls of adjacent electrically conductive interconnect lines,
- FIG. 5 is a cross sectional view of a layer sealing a void between adjacent electrically conductive interconnect lines, and
- FIG. 4 is a cross sectional view of the planarized layer over the void.
- Referring now to FIG. 1, a method is provided for reducing the coupling capacitance between the closely spaced electrically conductive interconnect lines of an integrated
circuit 10. The integratedcircuit 10 preferably includes one or more active or passive elements that are electrically connected by electrically conductive interconnect lines An electrically conductive material such as gold, aluminum, copper, tin, tantalum, titanium, platinum, tungsten, molybdenum, polysilicon, or a mixture or alloy of two or more of the foregoing is deposited on asubstrate 12 to provide an electricallyconductive layer 14. The electricallyconductive layer 14 is preferably substantially evenly deposited over the whole surface of thesubstrate 12. Thesubstrate 12 may further comprise a plurality of various layers. Most preferably, the topmost layer of thesubstrate 12 on which the electricallyconductive layer 14 is deposited is a non electrically conductive, or insulating layer. - Referring now to FIG. 2, a
masking layer 16, such as photoresist, is deposited on theconductive layer 14. Themasking layer 16 is preferably patterned using conventional photolithography techniques to provide anopening 18 in themasking layer 16, which opening 18 corresponds to the spacing between adjacent interconnect lines that are to be formed in theconductive layer 14. - As illustrated in FIG. 3,
gap 20 between adjacent electrically conductive interconnect lines is formed in theconductive layer 14 by a process such as plasma etching theconductive layer 14 through theopening 18 in themasking layer 16. Etching of theconductive layer 14 is preferably conducted in a manner whereby thesidewalls 22 of thegap 20 have a negative slope, or in other words, where thesidewalls 22 of thegap 20 are closer together at the top of thegap 20 than they are at the bottom of thegap 20. - Without being bound to a particular method of formation of the
gap 20, or a particular theory of how the negative slope of thesidewalls 22 of thegap 20 are formed, thegap 20 may be plasma etched in the absence of a magnetic field. During an initial etching period, polymer forming gases, such as halogenated methane and the like are used to form polymeric substances on thesidewalls 22 of theconductive layer 14 as they start to be formed, thereby passivating the upper portions of thesidewalls 22 so that boron halide species such as BCl3 anisotropically etch theconductive layer 14. However, unlike conventional etching processes, after about ten to about fifteen seconds into the etching process, the plasma chamber is purposefully depleted of polymer forming gases so that the lower portions of thesidewalls 22 of theconductive layer 14 are not passivated. - At this point in the etching process, the
conductive layer 14 is etched isotropically, resulting in undercut regions and negatively slopingsidewalls 22 as illustrated in FIG. 3. The process produces agap 20 in theconductive layer 14, where the width 24 at the top of thegap 20 is substantially smaller than thewidth 26 at the bottom of thegap 20. The etching process thus produces ledges or overhangs 28 in theconductive layer 14 at the top of thegap 20, as depicted in FIG. 4. - Regardless of the exact process used to form the
overhangs 28 in theconductive layer 14, theoverhangs 28 preferably enable the formation of asealed void 34 in theconductive layer 14, as depicted in FIG. 5. Adielectric layer 30 is preferably deposited on top of the etchedconductive layer 14 under conditions sufficient to form thevoid 34 in thegap 20. Thedielectric layer 30 is preferably a layer of substantially non electrically conductive material such as, but not limited to silicon nitride, silicon oxide such as silicon dioxide, boron nitride, and silicon carbide. A particularly preferreddielectric layer 30 is a silicon oxide layer deposited with a modified silane physical vapor deposition process. - The deposition reactor in which the
dielectric layer 30 is deposited is preferably detuned and highly directional to provide poor step coverage of thedielectric layer 30 over thegap 20 in theconductive layer 14. Accordingly, adeposit 32 of the dielectric material may be deposited in thegap 20. However, the portions ofgap 20 directly adjacent thesidewalls 22 of theconductive layer 14 are filled with thevoid 34 created in thegap 20. In other words, thedielectric material 32 formed at the bottom of thegap 20 preferably does not substantially contact thesidewalls 22 of theconductive layer 14. - Most of the
void 34 is not filled with any solid material. Thevoid 34 preferably extends substantially completely across thegap 20 between the negatively slopingsidewalls 22 of thegap 20, as depicted in FIG. 5. In other words, there is preferably substantially no deposited material on the negatively slopedsidewalls 22, or on a substantial portion of thesubstrate 12 at the bottom of thegap 20. Thus, according to the method of the present invention, it is preferred that a minimal amount of material be deposited within thegap 20, and that thevoid 34 comprise a relatively large portion of thegap 20. However, the depositeddielectric material 32 may contact thelayer 30 of dielectric material, as depicted in FIG. 6. - The
void 34 may be filled with any one of a number of gases, such as the precursor gases used during the deposition process whereby thedielectric layer 30 was formed. Most preferably thevoid 34 is filled with air. By filling thegap 20 between the interconnect lines formed in theconductive layer 14 with a gas that has a dielectric constant that is preferably less than the dielectric constant of the insulating material used to form thedielectric layer 30, which for the materials most commonly used is no less than about two, the capacitive coupling between adjacent interconnect lines is preferably commensurately reduced. The effective dielectric constant of the void 34 is preferably between about one and about one and a half. The gas within the void 34 may be at a pressure that is alternately greater than, less than, or substantially equal to atmospheric pressure. - After depositing the
dielectric layer 30 on the etchedconductive layer 14, thedielectric layer 30 is preferably planarized, such as with a chemical mechanical polish, as depicted in FIG. 6. Additional layers may be selectively deposited on theplanarized dielectric layer 30 and the process of etching the layers is repeated to create an integrated circuit having relatively low coupling capacitance between adjacent interconnect lines. - The foregoing description of preferred embodiments for this invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide the best illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as is suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
Claims (18)
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US10/171,701 US20030013298A1 (en) | 2001-07-16 | 2002-06-14 | Coupling capacitance reduction |
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US09/906,331 US6432812B1 (en) | 2001-07-16 | 2001-07-16 | Method of coupling capacitance reduction |
US10/171,701 US20030013298A1 (en) | 2001-07-16 | 2002-06-14 | Coupling capacitance reduction |
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US09/906,331 Division US6432812B1 (en) | 2001-07-16 | 2001-07-16 | Method of coupling capacitance reduction |
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US09/906,331 Expired - Lifetime US6432812B1 (en) | 2001-07-16 | 2001-07-16 | Method of coupling capacitance reduction |
US10/171,701 Abandoned US20030013298A1 (en) | 2001-07-16 | 2002-06-14 | Coupling capacitance reduction |
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Cited By (6)
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US20050082628A1 (en) * | 2003-10-21 | 2005-04-21 | Hirohisa Kawasaki | Semiconductor device and method of manufacturing the same |
US20070116126A1 (en) * | 2005-11-18 | 2007-05-24 | Apple Computer, Inc. | Multipass video encoding and rate control using subsampling of frames |
US20110227977A1 (en) * | 2005-12-05 | 2011-09-22 | Silverbrook Research Pty Ltd | Method of modulating peak power fluctuations in multi-colored printhead having respective power supply |
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US11450601B2 (en) * | 2019-09-18 | 2022-09-20 | Micron Technology, Inc. | Assemblies comprising memory cells and select gates |
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US6850747B1 (en) | 2000-06-30 | 2005-02-01 | International Business Machines Corporation | Image trap filter |
EP1835530A3 (en) * | 2006-03-17 | 2009-01-28 | Samsung Electronics Co., Ltd. | Non-volatile memory device and method of manufacturing the same |
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JPS63238288A (en) * | 1987-03-27 | 1988-10-04 | Fujitsu Ltd | Dry etching method |
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US5407860A (en) * | 1994-05-27 | 1995-04-18 | Texas Instruments Incorporated | Method of forming air gap dielectric spaces between semiconductor leads |
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US6114766A (en) * | 1997-12-18 | 2000-09-05 | Advanced Micro Devices, Inc. | Integrated circuit with metal features presenting a larger landing area for vias |
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KR100286126B1 (en) * | 1999-02-13 | 2001-03-15 | 윤종용 | Process for forming air gaps using a multilayer passivation in a dielectric between interconnections |
US6130151A (en) * | 1999-05-07 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing air gap in multilevel interconnection |
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2001
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2002
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Cited By (7)
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US20050082628A1 (en) * | 2003-10-21 | 2005-04-21 | Hirohisa Kawasaki | Semiconductor device and method of manufacturing the same |
US20070116126A1 (en) * | 2005-11-18 | 2007-05-24 | Apple Computer, Inc. | Multipass video encoding and rate control using subsampling of frames |
US8031777B2 (en) * | 2005-11-18 | 2011-10-04 | Apple Inc. | Multipass video encoding and rate control using subsampling of frames |
US20110227977A1 (en) * | 2005-12-05 | 2011-09-22 | Silverbrook Research Pty Ltd | Method of modulating peak power fluctuations in multi-colored printhead having respective power supply |
CN103165522A (en) * | 2011-12-15 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method of semiconductor structure |
TWI716313B (en) * | 2019-08-21 | 2021-01-11 | 南亞科技股份有限公司 | Semiconductor device with air spacer and method for preparing the same |
US11450601B2 (en) * | 2019-09-18 | 2022-09-20 | Micron Technology, Inc. | Assemblies comprising memory cells and select gates |
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