US20020178318A1 - Apparatus and method for reducing reflexions in a memory bus system - Google Patents
Apparatus and method for reducing reflexions in a memory bus system Download PDFInfo
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- US20020178318A1 US20020178318A1 US10/145,579 US14557902A US2002178318A1 US 20020178318 A1 US20020178318 A1 US 20020178318A1 US 14557902 A US14557902 A US 14557902A US 2002178318 A1 US2002178318 A1 US 2002178318A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
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- the present invention relates to an apparatus and a method for reducing reflexions in a memory bus system in which data are sent and received.
- reflexions or multiple reflexions typically occur in the bus during the sending and receiving of data at the connecting points of components such as, for example, memory components. Further causes for reflexions are, in general, branches of the bus with a different load, changes in impedance inside the bus and, in general, the topology of the bus.
- reflexions are usually reduced with the aid of passive or active terminations, the active terminations being optimized only for a specific operating point in the working range of the bus, and reducing the reflexions optimally only there.
- a problem in the prior art therefore consists in that the measures for reducing reflexions in buses do not reduce reflexions for a wide working range of the bus.
- a working range is determined, for example, by the distinguishability of the sent and received data, that is to say, for example, the bit pattern, the temporal changes in the bus characteristics and the connecting characteristics of components on the bus, and the frequency of the sent and received data signals. If the reflexions are not adequately reduced, this can lead, inter alia, to a loss in the temporal alignment of the data in the bus and, for example, in the case of high frequencies to smearing or rounding of binary signal edges.
- the object of the present invention therefore consists in creating an apparatus and a method for reducing reflexions in a bus for transmitting data, which permit a reduction in reflexions over the entire working range of the bus.
- One advantage of the apparatus and the method of the present invention consists in that the same permit a reduction in reflexions in a bus over a wide working range of the bus in conjunction with variations in the frequency of the data signal and the characteristics of the bus etc.
- a further advantage of the apparatus and the method of the present invention consists in that in the case of high frequencies, in particular, reflexions are reduced which can effect strong smearing or rounding of signal edges.
- the device for evaluating and setting is arranged in order to control the impedance as a function of the evaluation result in such a way that the latter is constant over the frequency.
- An advantage of this preferred development consists in that, particularly in the case of high frequencies, smearing or rounding of signal edges is avoided by keeping the impedance constant over the entire frequency range.
- the device for receiving is a detecting amplifier which detects the settling time and the hold time of data, which are represented by the test signal, at the device for receiving.
- the device for evaluating and setting is, furthermore, arranged in order to set the impedance in such a way that the settling time and the hold time are optimized.
- the device for evaluating and setting is arranged, furthermore, in order to set the impedance in such a way that overshooting and undershooting in the bus are reduced.
- the device for evaluating and setting is arranged, furthermore, in order to set the transmission strength and the time profile of the transmission strength of the device for sending in such a way that the data alignment in the bus is maintained.
- the device for evaluating and setting has a memory in which setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals are stored.
- the test signal is a digital signal which has a predefined bit pattern.
- the impedance is a series impedance which has a first input, a second input and an output which is connected to the output, there being connected between the first input and the output a first impedance whose impedance value can be controlled, and between the output and the second input a second impedance whose impedance value can be controlled.
- the first impedance has a first transistor whose impedance value can be controlled
- the second impedance has a second transistor whose impedance value can be controlled.
- the first transistor is connected to a first power supply in a controllable fashion via a third transistor, which is controlled by the device for evaluating and setting, and the second transistor is connected to a second power supply in a controllable fashion via a fourth transistor, which is controlled by the device for evaluating and setting.
- the first, second, third and fourth transistors in each case have a control input which is connected to the device for evaluating and setting.
- the first and the second transistor in each case have a JFET transistor
- the third and the fourth transistor in each case have a MOSFET transistor.
- the bus has a memory subsystem bus to which memory components can be connected.
- the memory components have dynamic random access memory (DRAM) memory components.
- DRAM dynamic random access memory
- the steps of evaluating and setting have the step of controlling the impedance as a function of the evaluation result in such a way that the impedance is constant over the frequency.
- the step of receiving further has [lacuna] the detection of the settling time and the hold time of data which are represented by the test signal.
- the steps of evaluating and setting further have the step of setting the impedance in such a way that the settling time and the holding time are optimized.
- the steps of evaluating and setting further have the step of setting the impedance in such a way that overshooting and undershooting in the bus are reduced.
- the steps of evaluating and setting further have the step of setting the transmission strength and the time profile of the transmission strength during the step of sending in such a way that the data alignment in the bus is maintained.
- the steps of evaluating and setting further have the step of storing the setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals.
- FIG. 1 shows an exemplary embodiment of an apparatus in accordance with the present invention
- FIG. 2 shows the frequency-dependent behavior of the impedance at the output of the apparatus of FIG. 1;
- FIG. 3 shows an exemplary embodiment of a method in accordance with the present invention.
- FIG. 1 shows an exemplary embodiment of an apparatus according to the invention for reducing reflexions in a bus, in which data can be transmitted.
- the apparatus 100 for reducing reflexions in a bus 102 is connected to an input of the bus 102 via an output 104 .
- the bus 102 is preferably a memory subsystem bus to which memory components ( 130 ), preferably dynamic random access memory (DRAM) memory elements can be connected.
- memory components 130
- DRAM dynamic random access memory
- the apparatus 100 has a device 106 for sending a test signal into the input of the bus 102 , the device 106 for sending being connected to the output 104 .
- the device 106 for sending is preferably a driver for driving test signals or data signals into the bus 102 .
- the test signal is preferably a digital signal which preferably has a predefined bit pattern.
- the predefined bit pattern is a function of the system and preferably includes instructions with the aid of which the apparatus 100 is calibrated in order to reduce reflexions in the bus 102 .
- the apparatus 100 for reducing reflexions further has a device 108 for receiving reflexions from the bus 102 , which is connected to the output 104 .
- the device for receiving is preferably a detecting amplifier which detects the settling time and the hold time of data, which are represented by the test signal, at the device 108 for receiving.
- the apparatus 100 for reducing reflexions further has a device 110 for evaluating the reflexions from the bus 102 , in order to supply an evaluation result, and for setting the impedance Z IN at the output 104 as a function of the evaluation result, in order to reduce the reflexions from the bus 102 .
- the device 110 for evaluating and setting is preferably arranged in such a way that the same controls the impedance ZIN as a function of the evaluation result in such a way that said impedance is constant over the frequency, and can, furthermore, preferably be arranged in order to set the impedance in such a way that the settling time and the hold time of data which are detected by the device 108 for receiving are optimized.
- the device 110 for evaluating and setting is preferably arranged, furthermore, in order to set the impedance Z IN in such a way that overshooting and undershooting in the bus 102 are reduced.
- the device 110 for evaluating and setting can be arranged, moreover, in order to set the transmission strength and the time profile of the transmission strength of the device 106 for sending in such a way that the data alignment in the bus 102 is maintained.
- the apparatus 100 sends a calibration sequence or bit sequence into the bus, preferably a memory channel for memory components, and the reflexions or the returning bits are detected by the device 108 for receiving, in order to calibrate appropriately the transmission strength and the time profile of the transmission strength of the device for sending. This relates, in particular, to the slew rate of the transmission strength in order to prevent a loss in the temporal tuning between the data or a temporal alignment between the data.
- the device 110 for evaluating and setting the apparatus 100 can, furthermore, preferably have a memory in which setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals can be stored. It is possible, for example, to store in this memory settings of the impedance Z IN which are suitable for optimally reducing reflexions in the bus 102 in the case of different bit patterns of the transmitted data or test signals and/or in the case of varying characteristics of the bus.
- the impedance ZIN can thereby be adapted dynamically to the type of data signals in the bus.
- the apparatus 100 preferably has an impedance in the form of a series impedance which has a first input 112 , a second input 114 and an output 116 which is connected to the output 104 , there being connected between the first input 112 and the output 116 a first impedance 118 whose impedance value can be controlled, and between the output 116 and the second input 114 a second impedance 120 whose impedance value can be controlled.
- the first impedance 118 preferably has a first transistor 118 whose impedance value can be controlled
- the second impedance 120 preferably has a second transistor 120 whose impedance value can be controlled.
- the first transistor 118 is connected to a first power supply 124 , which is preferably a positive power supply, in a controllable fashion via a third transistor 122 , which is controlled by the device 110 for evaluating and setting, and the second transistor 120 is connected to a second power supply 128 , preferably a negative power supply, in a controllable fashion via a fourth transistor 126 , which is controlled by the device 110 for evaluating and setting.
- a first power supply 124 which is preferably a positive power supply
- a third transistor 122 which is controlled by the device 110 for evaluating and setting
- the second transistor 120 is connected to a second power supply 128 , preferably a negative power supply, in a controllable fashion via a fourth transistor 126 , which is controlled by the device 110 for evaluating and setting.
- the first, second, third and fourth transistors 118 , 120 , 122 , 126 in each case have a control input which is connected, preferably via lines, to the device 110 for evaluating and setting.
- the first and the second transistors 118 , 120 are in each case preferably a JFET transistor whose gate-source control voltage can be controlled via the control input.
- the third and the fourth transistors 122 , 126 are preferably in each case a MOSFET transistor whose impedance between drain and source can be controlled by the gate-source control voltage at the control input of the respective transistor.
- the third transistor 122 is preferably a p-MOSFET transistor
- the fourth transistor 126 is preferably an n-MOSFET transistor which is connected via an inverter 128 to the device 110 for evaluating and setting.
- the termination impedance and the profile of this impedance value over the frequency is set suitably by the device 110 for evaluating and setting, in order to reduce the reflexions in a bus optimally.
- the arrangement of the output 104 between the first transistor 118 and the second transistor 120 is usually denoted as a push-pull driver.
- the first or upper transistor 118 draws the voltage upward (“push”)
- the second or lower transistor 120 draws the voltage downward (“pull”).
- FIG. 2 shows the frequency-dependent behavior of the impedance ZIN at the output 104 of the apparatus 100 for reducing reflexions.
- the curve 200 shows the profile of the frequency dependence of the impedance in the case of a lack of control of the impedance at the output 104 in such a way as to reduce reflexions in the bus.
- the curve 202 shows the profile of the impedance against the frequency in the case of optimization of the impedance ZIN by controlling the gate-source voltages of the third transistor 122 and of the fourth transistor 126 .
- the curve 204 shows the profile of the impedance against the frequency for optimized control of the gate-source voltage of the third and fourth transistor 122 , 126 and of the impedance of the first transistor 118 and of the second transistor 120 , as a function of the gate-source voltage at the control inputs of the same. It may easily be seen that by controlling both the gate-source voltage of the third and the fourth transistor 1122 , 126 and the impedance of the first and the second transistor 118 , 210 , it is possible to achieve a virtually constant profile of the impedance over the entire frequency range, and this reduces the rounding of binary signal edges, particularly in the case of high frequencies.
- a further preferred exemplary embodiment of the present invention comprises a controller for a bus 102 , which has the apparatus 100 , described above, for reducing reflexions in a bus 102 .
- the device 106 for sending is then a device 106 for sending data or data signals via the bus, which can also be used to send a test signal for calibrating the controller for the purpose of driving a bus optimally with low reflexion
- the device 108 for receiving is then a device for receiving data which can further be used for receiving reflexions which are caused by the test signals, in order to set the apparatus 100 for reducing reflexions in a bus 102 optimally in order to be able to transmit data without reflexions.
- a further preferred exemplary embodiment of the present invention comprises a memory component which, in a way similar to the controller just described, has an apparatus 100 , described above, for reducing reflexions.
- FIG. 3 shows a preferred exemplary embodiment of a method for reducing reflexions in a bus 102 for the purpose of transmitting data in accordance with the present invention.
- a test signal is sent into a input of the bus 102 , preferably by the above-described device 106 for sending a test signal.
- reflexions from the bus 102 which are caused by the sent test signal in the bus 102 are received, preferably by the above-described device 108 for receiving reflexions.
- a step S 3 the reflexions from the bus 102 are preferably evaluated by the above-described device 110 for evaluating reflexions, in order to supply an evaluation result, and the impedance Z IN at the input of the bus 102 is set in a step S 4 as a function of the evaluation result, in order to reduce reflexions of the bus 102 .
- the steps of evaluating S 3 and setting S 4 also include controlling the impedance as a function of the evaluation result, preferably by the device 110 for evaluating and setting, in such a way that said impedance is constant over the frequency.
- the step of receiving S 2 can include, furthermore, the step of detecting the settling time and the hold time of data which are represented by the test signal, preferably by the above-described device 108 for receiving reflexions, which preferably has a detecting amplifier.
- the steps of evaluating S 3 and setting S 4 can preferably include setting the impedance Z IN , preferably by the above-described device 110 for evaluating and setting, in such a way that the settling time and hold time are optimized and, furthermore, preferably the step of setting the impedance Z IN in such a way that overshooting and undershooting in the bus 102 are reduced.
- the steps of evaluating S 3 and setting S 4 can include, furthermore, the step of setting the transmission strength and the time profile of the transmission strength in the step S 2 of sending, preferably by the device 106 for sending, in such a way that the data alignment in the bus 102 is maintained.
- the steps of evaluating S 3 and setting S 4 can preferably include the step of storing the setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals, preferably in the memory of the above-described device 110 for evaluating and setting.
- An advantage of the present invention consists in that the same permits the reliable operation of, for example, a memory subsystem bus with connected memory components, for example DRAM memories, over a wide operating range and, in particular, a wide frequency range.
Abstract
Description
- This application claims the benefit of German application number 101 24 176.3, filed May 17, 2001, currently pending, the disclosure of which is hereby incorporated by reference in its entirety.
- The present invention relates to an apparatus and a method for reducing reflexions in a memory bus system in which data are sent and received.
- In conventional buses, such as memory subsystem buses in computer systems, reflexions or multiple reflexions typically occur in the bus during the sending and receiving of data at the connecting points of components such as, for example, memory components. Further causes for reflexions are, in general, branches of the bus with a different load, changes in impedance inside the bus and, in general, the topology of the bus.
- In the prior art, such reflexions are usually reduced with the aid of passive or active terminations, the active terminations being optimized only for a specific operating point in the working range of the bus, and reducing the reflexions optimally only there.
- A problem in the prior art therefore consists in that the measures for reducing reflexions in buses do not reduce reflexions for a wide working range of the bus. Such a working range is determined, for example, by the distinguishability of the sent and received data, that is to say, for example, the bit pattern, the temporal changes in the bus characteristics and the connecting characteristics of components on the bus, and the frequency of the sent and received data signals. If the reflexions are not adequately reduced, this can lead, inter alia, to a loss in the temporal alignment of the data in the bus and, for example, in the case of high frequencies to smearing or rounding of binary signal edges.
- The object of the present invention therefore consists in creating an apparatus and a method for reducing reflexions in a bus for transmitting data, which permit a reduction in reflexions over the entire working range of the bus.
- This object is achieved by means of an apparatus for reducing reflexions in a bus for transmitting data in accordance with
claim 1, a controller for a bus in accordance with claim 16, a memory component in accordance with claim 17, and a method for reducing reflexions in a bus for transmitting data in accordance with claim 18. - One advantage of the apparatus and the method of the present invention consists in that the same permit a reduction in reflexions in a bus over a wide working range of the bus in conjunction with variations in the frequency of the data signal and the characteristics of the bus etc.
- A further advantage of the apparatus and the method of the present invention consists in that in the case of high frequencies, in particular, reflexions are reduced which can effect strong smearing or rounding of signal edges.
- Advantageous developments and improvements of the apparatus specified in
claim 1 and of the method specified in claim 17 are to be found in the subclaims. - In accordance with a preferred development of the apparatus of the present invention, the device for evaluating and setting is arranged in order to control the impedance as a function of the evaluation result in such a way that the latter is constant over the frequency.
- An advantage of this preferred development consists in that, particularly in the case of high frequencies, smearing or rounding of signal edges is avoided by keeping the impedance constant over the entire frequency range.
- In accordance with a further preferred development of the apparatus of the present invention, the device for receiving is a detecting amplifier which detects the settling time and the hold time of data, which are represented by the test signal, at the device for receiving.
- In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting is, furthermore, arranged in order to set the impedance in such a way that the settling time and the hold time are optimized.
- In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting is arranged, furthermore, in order to set the impedance in such a way that overshooting and undershooting in the bus are reduced.
- In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting is arranged, furthermore, in order to set the transmission strength and the time profile of the transmission strength of the device for sending in such a way that the data alignment in the bus is maintained.
- In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting has a memory in which setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals are stored.
- In accordance with a further preferred development of the apparatus of the present invention, the test signal is a digital signal which has a predefined bit pattern.
- In accordance with a further preferred development of the present invention [sic], the impedance is a series impedance which has a first input, a second input and an output which is connected to the output, there being connected between the first input and the output a first impedance whose impedance value can be controlled, and between the output and the second input a second impedance whose impedance value can be controlled.
- In accordance with a further preferred development of the present invention [sic], the first impedance has a first transistor whose impedance value can be controlled, and the second impedance has a second transistor whose impedance value can be controlled.
- In accordance with a further preferred development of the apparatus of the present invention, the first transistor is connected to a first power supply in a controllable fashion via a third transistor, which is controlled by the device for evaluating and setting, and the second transistor is connected to a second power supply in a controllable fashion via a fourth transistor, which is controlled by the device for evaluating and setting.
- In accordance with a further preferred development of the apparatus of the present invention, the first, second, third and fourth transistors in each case have a control input which is connected to the device for evaluating and setting.
- In accordance with a further preferred development of the apparatus of the present invention, the first and the second transistor in each case have a JFET transistor, and the third and the fourth transistor in each case have a MOSFET transistor.
- In accordance with a further preferred development of the apparatus of the present invention, the bus has a memory subsystem bus to which memory components can be connected.
- In accordance with a further preferred development of the present invention [sic], the memory components have dynamic random access memory (DRAM) memory components.
- In accordance with a preferred development of the method of the present invention, the steps of evaluating and setting have the step of controlling the impedance as a function of the evaluation result in such a way that the impedance is constant over the frequency.
- In accordance with a further preferred development of the method of the present invention, the step of receiving further has [lacuna] the detection of the settling time and the hold time of data which are represented by the test signal.
- In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of setting the impedance in such a way that the settling time and the holding time are optimized.
- In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of setting the impedance in such a way that overshooting and undershooting in the bus are reduced.
- In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of setting the transmission strength and the time profile of the transmission strength during the step of sending in such a way that the data alignment in the bus is maintained.
- In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of storing the setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals.
- Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the attached drawings, in which:
- FIG. 1 shows an exemplary embodiment of an apparatus in accordance with the present invention;
- FIG. 2 shows the frequency-dependent behavior of the impedance at the output of the apparatus of FIG. 1; and
- FIG. 3 shows an exemplary embodiment of a method in accordance with the present invention.
- FIG. 1 shows an exemplary embodiment of an apparatus according to the invention for reducing reflexions in a bus, in which data can be transmitted. The
apparatus 100 for reducing reflexions in abus 102 is connected to an input of thebus 102 via anoutput 104. Thebus 102 is preferably a memory subsystem bus to which memory components (130), preferably dynamic random access memory (DRAM) memory elements can be connected. - The
apparatus 100 has adevice 106 for sending a test signal into the input of thebus 102, thedevice 106 for sending being connected to theoutput 104. Thedevice 106 for sending is preferably a driver for driving test signals or data signals into thebus 102. The test signal is preferably a digital signal which preferably has a predefined bit pattern. The predefined bit pattern is a function of the system and preferably includes instructions with the aid of which theapparatus 100 is calibrated in order to reduce reflexions in thebus 102. - The
apparatus 100 for reducing reflexions further has adevice 108 for receiving reflexions from thebus 102, which is connected to theoutput 104. The device for receiving is preferably a detecting amplifier which detects the settling time and the hold time of data, which are represented by the test signal, at thedevice 108 for receiving. - The
apparatus 100 for reducing reflexions further has adevice 110 for evaluating the reflexions from thebus 102, in order to supply an evaluation result, and for setting the impedance ZIN at theoutput 104 as a function of the evaluation result, in order to reduce the reflexions from thebus 102. Thedevice 110 for evaluating and setting is preferably arranged in such a way that the same controls the impedance ZIN as a function of the evaluation result in such a way that said impedance is constant over the frequency, and can, furthermore, preferably be arranged in order to set the impedance in such a way that the settling time and the hold time of data which are detected by thedevice 108 for receiving are optimized. Thedevice 110 for evaluating and setting is preferably arranged, furthermore, in order to set the impedance ZIN in such a way that overshooting and undershooting in thebus 102 are reduced. Thedevice 110 for evaluating and setting can be arranged, moreover, in order to set the transmission strength and the time profile of the transmission strength of thedevice 106 for sending in such a way that the data alignment in thebus 102 is maintained. In this case, theapparatus 100 sends a calibration sequence or bit sequence into the bus, preferably a memory channel for memory components, and the reflexions or the returning bits are detected by thedevice 108 for receiving, in order to calibrate appropriately the transmission strength and the time profile of the transmission strength of the device for sending. This relates, in particular, to the slew rate of the transmission strength in order to prevent a loss in the temporal tuning between the data or a temporal alignment between the data. - The
device 110 for evaluating and setting theapparatus 100 can, furthermore, preferably have a memory in which setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals can be stored. It is possible, for example, to store in this memory settings of the impedance ZIN which are suitable for optimally reducing reflexions in thebus 102 in the case of different bit patterns of the transmitted data or test signals and/or in the case of varying characteristics of the bus. The impedance ZIN can thereby be adapted dynamically to the type of data signals in the bus. - For the purpose of supplying an impedance at its
output 104, theapparatus 100 preferably has an impedance in the form of a series impedance which has a first input 112, asecond input 114 and anoutput 116 which is connected to theoutput 104, there being connected between the first input 112 and the output 116 afirst impedance 118 whose impedance value can be controlled, and between theoutput 116 and the second input 114 asecond impedance 120 whose impedance value can be controlled. Thefirst impedance 118 preferably has afirst transistor 118 whose impedance value can be controlled, and thesecond impedance 120 preferably has asecond transistor 120 whose impedance value can be controlled. - The
first transistor 118 is connected to afirst power supply 124, which is preferably a positive power supply, in a controllable fashion via athird transistor 122, which is controlled by thedevice 110 for evaluating and setting, and thesecond transistor 120 is connected to asecond power supply 128, preferably a negative power supply, in a controllable fashion via afourth transistor 126, which is controlled by thedevice 110 for evaluating and setting. - The first, second, third and
fourth transistors device 110 for evaluating and setting. The first and thesecond transistors fourth transistors third transistor 122 is preferably a p-MOSFET transistor, and thefourth transistor 126 is preferably an n-MOSFET transistor which is connected via aninverter 128 to thedevice 110 for evaluating and setting. Via the gate-source voltages at the control input of the first and thesecond transistor device 110 for evaluating and setting, in order to reduce the reflexions in a bus optimally. The arrangement of theoutput 104 between thefirst transistor 118 and thesecond transistor 120 is usually denoted as a push-pull driver. The first orupper transistor 118 draws the voltage upward (“push”), and the second orlower transistor 120 draws the voltage downward (“pull”). - FIG. 2 shows the frequency-dependent behavior of the impedance ZIN at the
output 104 of theapparatus 100 for reducing reflexions. Thecurve 200 shows the profile of the frequency dependence of the impedance in the case of a lack of control of the impedance at theoutput 104 in such a way as to reduce reflexions in the bus. Thecurve 202 shows the profile of the impedance against the frequency in the case of optimization of the impedance ZIN by controlling the gate-source voltages of thethird transistor 122 and of thefourth transistor 126. Finally, thecurve 204 shows the profile of the impedance against the frequency for optimized control of the gate-source voltage of the third andfourth transistor first transistor 118 and of thesecond transistor 120, as a function of the gate-source voltage at the control inputs of the same. It may easily be seen that by controlling both the gate-source voltage of the third and thefourth transistor 1122, 126 and the impedance of the first and thesecond transistor 118, 210, it is possible to achieve a virtually constant profile of the impedance over the entire frequency range, and this reduces the rounding of binary signal edges, particularly in the case of high frequencies. - A further preferred exemplary embodiment of the present invention comprises a controller for a
bus 102, which has theapparatus 100, described above, for reducing reflexions in abus 102. In the case of the controller, thedevice 106 for sending is then adevice 106 for sending data or data signals via the bus, which can also be used to send a test signal for calibrating the controller for the purpose of driving a bus optimally with low reflexion, and thedevice 108 for receiving is then a device for receiving data which can further be used for receiving reflexions which are caused by the test signals, in order to set theapparatus 100 for reducing reflexions in abus 102 optimally in order to be able to transmit data without reflexions. - A further preferred exemplary embodiment of the present invention comprises a memory component which, in a way similar to the controller just described, has an
apparatus 100, described above, for reducing reflexions. - FIG. 3 shows a preferred exemplary embodiment of a method for reducing reflexions in a
bus 102 for the purpose of transmitting data in accordance with the present invention. In a step S1 of the method according to the invention, a test signal is sent into a input of thebus 102, preferably by the above-describeddevice 106 for sending a test signal. Subsequently, reflexions from thebus 102 which are caused by the sent test signal in thebus 102 are received, preferably by the above-describeddevice 108 for receiving reflexions. In a step S3, the reflexions from thebus 102 are preferably evaluated by the above-describeddevice 110 for evaluating reflexions, in order to supply an evaluation result, and the impedance ZIN at the input of thebus 102 is set in a step S4 as a function of the evaluation result, in order to reduce reflexions of thebus 102. - The steps of evaluating S3 and setting S4 also include controlling the impedance as a function of the evaluation result, preferably by the
device 110 for evaluating and setting, in such a way that said impedance is constant over the frequency. The step of receiving S2 can include, furthermore, the step of detecting the settling time and the hold time of data which are represented by the test signal, preferably by the above-describeddevice 108 for receiving reflexions, which preferably has a detecting amplifier. Furthermore, the steps of evaluating S3 and setting S4 can preferably include setting the impedance ZIN, preferably by the above-describeddevice 110 for evaluating and setting, in such a way that the settling time and hold time are optimized and, furthermore, preferably the step of setting the impedance ZIN in such a way that overshooting and undershooting in thebus 102 are reduced. The steps of evaluating S3 and setting S4 can include, furthermore, the step of setting the transmission strength and the time profile of the transmission strength in the step S2 of sending, preferably by thedevice 106 for sending, in such a way that the data alignment in thebus 102 is maintained. Finally, the steps of evaluating S3 and setting S4 can preferably include the step of storing the setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals, preferably in the memory of the above-describeddevice 110 for evaluating and setting. - Although the present invention is described with the aid of preferred exemplary embodiments, it is not limited thereto, but can be modified in multifarious ways.
- An advantage of the present invention consists in that the same permits the reliable operation of, for example, a memory subsystem bus with connected memory components, for example DRAM memories, over a wide operating range and, in particular, a wide frequency range.
Claims (24)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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DE10124176.3 | 2001-05-17 | ||
DE10124176 | 2001-05-17 | ||
DE10124176A DE10124176B4 (en) | 2001-05-17 | 2001-05-17 | Apparatus and method for reducing reflections in a memory bus system |
Publications (2)
Publication Number | Publication Date |
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US20020178318A1 true US20020178318A1 (en) | 2002-11-28 |
US6686764B2 US6686764B2 (en) | 2004-02-03 |
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US10/145,579 Expired - Lifetime US6686764B2 (en) | 2001-05-17 | 2002-05-14 | Apparatus and method for reducing reflexions in a memory bus system |
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US (1) | US6686764B2 (en) |
DE (1) | DE10124176B4 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004046957A1 (en) * | 2004-09-28 | 2006-04-06 | Infineon Technologies Ag | Method and circuit arrangements for matching signal propagation times in a memory system |
US20090284281A1 (en) * | 2006-06-02 | 2009-11-19 | Kyung Suk Oh | Memory-module buffer with on-die termination |
US8588012B2 (en) | 2010-06-17 | 2013-11-19 | Rambus, Inc. | Balanced on-die termination |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI247402B (en) * | 2002-02-05 | 2006-01-11 | Via Tech Inc | Pad circuit and method for automatically adjusting gain for same |
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US5134311A (en) * | 1990-06-07 | 1992-07-28 | International Business Machines Corporation | Self-adjusting impedance matching driver |
JPH0993165A (en) * | 1995-09-22 | 1997-04-04 | Internatl Business Mach Corp <Ibm> | Impedance matching device |
US6166563A (en) * | 1999-04-26 | 2000-12-26 | Intel Corporation | Method and apparatus for dual mode output buffer impedance compensation |
US6541996B1 (en) * | 1999-12-21 | 2003-04-01 | Ati International Srl | Dynamic impedance compensation circuit and method |
-
2001
- 2001-05-17 DE DE10124176A patent/DE10124176B4/en not_active Expired - Fee Related
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2002
- 2002-05-14 US US10/145,579 patent/US6686764B2/en not_active Expired - Lifetime
Cited By (32)
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DE102004046957A1 (en) * | 2004-09-28 | 2006-04-06 | Infineon Technologies Ag | Method and circuit arrangements for matching signal propagation times in a memory system |
US20060109869A1 (en) * | 2004-09-28 | 2006-05-25 | Andreas Jakobs | Method and circuit arrangements for adjusting signal propagation times in a memory system |
US7573741B2 (en) | 2004-09-28 | 2009-08-11 | Infineon Technologies Ag | Method and circuit arrangements for adjusting signal propagation times in a memory system |
DE102004046957B4 (en) * | 2004-09-28 | 2016-02-04 | Polaris Innovations Ltd. | Method and circuit arrangements for matching signal propagation times in a memory system |
US9135206B2 (en) | 2006-06-02 | 2015-09-15 | Rambus Inc. | Command-triggered on-die termination |
US9166583B2 (en) | 2006-06-02 | 2015-10-20 | Rambus Inc. | Buffered memory module having multi-valued on-die termination |
US7782082B2 (en) | 2006-06-02 | 2010-08-24 | Rambus Inc. | Memory-module buffer with on-die termination |
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US20110156750A1 (en) * | 2006-06-02 | 2011-06-30 | Kyung Suk Oh | Integrated circuit device with dynamically selected on-die termination |
US8089298B2 (en) | 2006-06-02 | 2012-01-03 | Rambus Inc. | Integrated circuit device with dynamically selected on-die termination |
US8188762B2 (en) | 2006-06-02 | 2012-05-29 | Rambus Inc. | Controlling dynamic selection of on-die termination |
US11349478B2 (en) | 2006-06-02 | 2022-05-31 | Rambus Inc. | Integrated circuit that applies different data interface terminations during and after write data reception |
US8610455B2 (en) | 2006-06-02 | 2013-12-17 | Rambus Inc. | Dynamic on-die termination selection |
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US9225328B2 (en) | 2006-06-02 | 2015-12-29 | Rambus Inc. | Nonvolatile memory device with time-multiplexed, on-die-terminated signaling interface |
US20090284281A1 (en) * | 2006-06-02 | 2009-11-19 | Kyung Suk Oh | Memory-module buffer with on-die termination |
US9306564B2 (en) | 2006-06-02 | 2016-04-05 | Rambus Inc. | Nonvolatile memory device with on-die control and data signal termination |
US9306568B2 (en) | 2006-06-02 | 2016-04-05 | Rambus Inc. | Controlling on-die termination in a nonvolatile memory |
US9306567B2 (en) | 2006-06-02 | 2016-04-05 | Rambus Inc. | Memory device with programmed device address and on-die-termination |
US9306565B2 (en) | 2006-06-02 | 2016-04-05 | Rambus Inc. | Nonvolatile memory with chip-select/device-address triggered on-die termination |
US9306566B2 (en) | 2006-06-02 | 2016-04-05 | Rambus Inc. | Nonvolatile memory with command-driven on-die termination |
US9337835B2 (en) | 2006-06-02 | 2016-05-10 | Rambus Inc. | Controlling a flash device having time-multiplexed, on-die-terminated signaling interface |
US9660648B2 (en) | 2006-06-02 | 2017-05-23 | Rambus Inc. | On-die termination control |
US10056902B2 (en) | 2006-06-02 | 2018-08-21 | Rambus Inc. | On-die termination control |
US10270442B2 (en) | 2006-06-02 | 2019-04-23 | Rambus Inc. | Memory component with on-die termination |
US10651849B2 (en) | 2006-06-02 | 2020-05-12 | Rambus Inc. | Transaction-based on-die termination |
US10944400B2 (en) | 2006-06-02 | 2021-03-09 | Rambus Inc. | On-die termination control |
US8588012B2 (en) | 2010-06-17 | 2013-11-19 | Rambus, Inc. | Balanced on-die termination |
Also Published As
Publication number | Publication date |
---|---|
US6686764B2 (en) | 2004-02-03 |
DE10124176A1 (en) | 2002-11-28 |
DE10124176B4 (en) | 2005-10-06 |
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