US20020177284A1 - Method of using sacrificial spacers to reduce short channel effect - Google Patents

Method of using sacrificial spacers to reduce short channel effect Download PDF

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US20020177284A1
US20020177284A1 US10/154,281 US15428102A US2002177284A1 US 20020177284 A1 US20020177284 A1 US 20020177284A1 US 15428102 A US15428102 A US 15428102A US 2002177284 A1 US2002177284 A1 US 2002177284A1
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gate electrode
electrode stack
spacers
oxide layer
sacrificial
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Jing-Xian Huang
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Promos Technologies Inc
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Promos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • U.S. Pat. No. 5,863,824 to Gardner et al. describes a method of forming semiconductor devices using gate electrode length and spacer width for controlling drive current strength.
  • U.S. Pat. No. 5,846,857 to Ju describes a method of manufacturing a CMOS device employing removable sidewall spacers for independently optimized N- and P-channel transistor performance.
  • a substrate having a gate electrode stack formed thereover is provided.
  • the substrate having an exposed surface and the gate electrode stack including a lower portion with exposed side walls.
  • a first oxide layer is formed over: the exposed side walls of the lower portion of the gate electrode stack; and the exposed surface of the substrate.
  • LDD implants may then be implanted into the substrate adjacent the first oxide layer formed over the exposed side walls of the lower portion of the gate electrode stack.
  • a conformal dielectric layer is formed over the gate electrode stack and the first oxide layer.
  • a sacrificial dielectric layer is formed over the conformal dielectric layer.
  • the horizontal portions of the sacrificial dielectric layer, the conformal dielectric layer and the underlying portions of the first oxide layer are patterned to form: sacrificial dielectric spacers; L-shaped conformal dielectric spacers thereunder; and L-shaped first oxide layer spacers thereunder. Then, using the gate electrode stack and the sacrificial dielectric spacers as masks, source/drain implants are implanted adjacent the sacrificial dielectric spacers and the sacrificial dielectric spacers are removed.
  • nitride spacers are formed with the L-shaped first oxide spacers with sacrificial oxide spacers being formed over the nitride spacers before formation of the source/drain implants.
  • FIGS. 1 and 2 schematically illustrate a process common to both preferred embodiments of the present invention.
  • FIGS. 3 to 5 schematically illustrate a first preferred embodiment of the present invention in conjunction with FIGS. 1 and 2.
  • FIGS. 6 to 9 schematically illustrate a second preferred embodiment of the present invention in conjunction with FIGS. 1 and 2.
  • FIG. 1 illustrates a substrate 10 having at least one gate electrode stack 18 formed thereover. Adjacent gate electrode stacks 18 may be separated by an isolation structure 12 . Gate electrode stack 18 has an underlying gate oxide layer 14 , an intermediate polycide portion 16 with exposed side walls 9 and an overlying SiN cap 23 .
  • Structure 10 is preferably a silicon or germanium substrate and isolation structure 12 is preferably a shallow trench isolation (STI) structure.
  • STI shallow trench isolation
  • an oxide layer 19 is thermally grown over the exposed side walls 9 of polycide portion 16 and over the exposed surface of substrate 10 , covering the exposed side walls of gate oxide layer 14 , to form initial sidewall spacers 20 over gate electrode stack 18 .
  • Initial oxide spacers 20 have a lower base width 21 of preferably from about 70 to 150 ⁇ and more preferably from about 80 to 130 ⁇ .
  • Initial oxide spacers 20 serve as barriers to prevent/mitigate damage otherwise caused by subsequent implantations.
  • LDD implants 22 are formed through the horizontal portions of oxide layer 19 and into substrate 10 adjacent initial oxide spacers 20 to a depth of preferably from about 300 to 1500 ⁇ and more preferably from about 500 to 1200 ⁇ .
  • BF 2 , P or As ions are preferably used to form LDD implants 22 and are preferably at a energy of preferably from about 5 to 45 keV.
  • a conformal SiN dielectric layer 100 is formed over gate electrode stack 18 , initial oxide spacers 20 , the horizontal portions of oxide layer 19 and STI 12 .
  • a sacrificial oxide layer 102 is then formed over conformal SiN layer 100 .
  • Conformal sacrificial oxide layer 102 is preferably comprised of chemical vapor deposition (CVD) oxide (SiO 2 ).
  • a conventional photolithography and etch process is performed to remove: the horizontal portions of sacrificial oxide layer 102 to form sacrificial oxide spacers 26 having a lower base width of preferably from about 80 to 300 ⁇ and more preferably from about 100 to 200 ⁇ ; the underlying portions of conformal SiN layer 100 to form initial L-shaped SiN spacers 28 (leaving a portion of SIN layer 100 over SiN cap 23 ); and the underlying horizontal portions of oxide layer 19 to complete formation of L-shaped oxide spacers 27 .
  • source/drain (S/D) implants 29 are formed within substrate 10 adjacent sacrificial oxide spacers 26 to a depth of preferably from about 500 to 2000 ⁇ and more preferably from about 800 to 1500 ⁇ .
  • BF 2 , P or As ions are preferably used to form S/D implants 29 and are preferably used at an energy of preferably from about 5 to 50 keV.
  • the portion of SiN layer 100 overlying SiN cap 23 is removed to form the final SiN spacers 28 and sacrificial oxide spacers 26 are removed preferably using a wet clean process with chemical HF to complete the structure of the first embodiment.
  • the effective gate length will become wider due to a sacrificial oxide spacer and in the same time without loss of gap fill for the following interlayer dielectric film. It does not change aspect ratio of gate stack to space as well.
  • a conformal SiN dielectric layer 200 is formed over gate electrode stack 18 , initial oxide spacers 20 , the horizontal portions of oxide layer 19 and STI 12 .
  • the conformal SiN dielectric layer 200 is patterned with the underlying horizontal portions of oxide layer 19 to form: SiN spacers 201 ; and thus L-shaped oxide spacers 202 .
  • Nitride spacers 201 have a lower base width of preferably from about 150 to 500 ⁇ and more preferably from about 200 to 400 ⁇ .
  • sacrificial oxide (SiO 2 ) spacers 204 are formed over nitride spacers 201 .
  • Sacrificial oxide spacers 204 are more preferably formed of CVD oxide (SiO 2 ).
  • Sacrificial oxide spacers 204 have a lower base width of preferably from about 80 to 300 ⁇ and more preferably from about 100 to 200 ⁇ .
  • source/drain (S/D) implants 206 are formed within substrate 10 adjacent sacrificial oxide spacers 204 to a depth of preferably from about 500 to 2000 ⁇ and more preferably from about 800 to 1500 ⁇ .
  • BF 2 , P or As ions are preferably used to form S/D implants 54 and preferably used at an energy of preferably from about 5 to 50 keV.
  • sacrificial oxide spacers 204 are removed from nitride spacers 201 preferably using a wet clean process with chemical HF to complete the structure of the second embodiment.
  • the effective gate length will become wider due to a sacrificial oxide spacer and in the same time without loss of gap fill for the following interlayer dielectric film. It does not change aspect ratio of gate stack to space as well.
  • the advantages of one or more embodiments of the present invention include effectively broadening the channel length without suffering the aspect ratio.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
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Abstract

A method of forming a semiconductor device comprising the following sequential steps. A substrate having a gate electrode stack formed thereover is provided. The substrate having an exposed surface and the gate electrode stack including a lower portion with exposed side walls. A first oxide layer is formed over: the exposed side walls of the lower portion of the gate electrode stack; and the exposed surface of the substrate. A conformal dielectric layer is formed over the gate electrode stack and the first oxide layer. A sacrificial dielectric layer is formed over the conformal dielectric layer. The horizontal portions of the sacrificial dielectric layer, the conformal dielectric layer and the underlying portions of the first oxide layer are patterned to form: sacrificial dielectric spacers; L-shaped conformal dielectric spacers thereunder; and L-shaped first oxide layer spacers thereunder. Then, using the gate electrode stack and the sacrificial dielectric spacers as masks, source/drain implants are implanted adjacent the sacrificial dielectric spacers and the sacrificial dielectric spacers are removed. In an alternate embodiment, nitride spacers are formed with the L-shaped first oxide spacers with sacrificial oxide spacers being formed over the nitride spacers before formation of the source/drain implants.

Description

    BACKGROUND OF THE INVENTION
  • As semiconductor devices become smaller and smaller, the devices, such as transistors, suffer severe short channel effect. [0001]
  • U.S. Pat. No. 5,863,824 to Gardner et al. describes a method of forming semiconductor devices using gate electrode length and spacer width for controlling drive current strength. [0002]
  • U.S. Pat. No. 5,846,857 to Ju describes a method of manufacturing a CMOS device employing removable sidewall spacers for independently optimized N- and P-channel transistor performance. [0003]
  • U.S. Pat. No. 6,156,598 to Zhou et al. describes a dual spacer process. [0004]
  • U.S. Pat. No. 5,789,298 to Gardner et al. describes another dual spacer process. [0005]
    • SUMMARY OF THE INVENTION
  • Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming semiconductor devices while minimizing short channel effect. [0006]
  • Other objects will appear hereinafter. [0007]
  • It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a gate electrode stack formed thereover is provided. The substrate having an exposed surface and the gate electrode stack including a lower portion with exposed side walls. A first oxide layer is formed over: the exposed side walls of the lower portion of the gate electrode stack; and the exposed surface of the substrate. LDD implants may then be implanted into the substrate adjacent the first oxide layer formed over the exposed side walls of the lower portion of the gate electrode stack. A conformal dielectric layer is formed over the gate electrode stack and the first oxide layer. A sacrificial dielectric layer is formed over the conformal dielectric layer. The horizontal portions of the sacrificial dielectric layer, the conformal dielectric layer and the underlying portions of the first oxide layer are patterned to form: sacrificial dielectric spacers; L-shaped conformal dielectric spacers thereunder; and L-shaped first oxide layer spacers thereunder. Then, using the gate electrode stack and the sacrificial dielectric spacers as masks, source/drain implants are implanted adjacent the sacrificial dielectric spacers and the sacrificial dielectric spacers are removed. In an alternate embodiment, nitride spacers are formed with the L-shaped first oxide spacers with sacrificial oxide spacers being formed over the nitride spacers before formation of the source/drain implants. [0008]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which: [0009]
  • FIGS. 1 and 2 schematically illustrate a process common to both preferred embodiments of the present invention. [0010]
  • FIGS. [0011] 3 to 5 schematically illustrate a first preferred embodiment of the present invention in conjunction with FIGS. 1 and 2.
  • FIGS. [0012] 6 to 9 schematically illustrate a second preferred embodiment of the present invention in conjunction with FIGS. 1 and 2.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Figures Common to Both Embodiments (FIGS. 1 and 2) [0013]
  • Initial Structure [0014]
  • FIG. 1 illustrates a [0015] substrate 10 having at least one gate electrode stack 18 formed thereover. Adjacent gate electrode stacks 18 may be separated by an isolation structure 12. Gate electrode stack 18 has an underlying gate oxide layer 14, an intermediate polycide portion 16 with exposed side walls 9 and an overlying SiN cap 23.
  • [0016] Structure 10 is preferably a silicon or germanium substrate and isolation structure 12 is preferably a shallow trench isolation (STI) structure.
  • Formation of [0017] Initial Oxide Spacers 20
  • As shown in FIG. 1, an [0018] oxide layer 19 is thermally grown over the exposed side walls 9 of polycide portion 16 and over the exposed surface of substrate 10, covering the exposed side walls of gate oxide layer 14, to form initial sidewall spacers 20 over gate electrode stack 18.
  • [0019] Initial oxide spacers 20 have a lower base width 21 of preferably from about 70 to 150 Å and more preferably from about 80 to 130 Å.
  • [0020] Initial oxide spacers 20 serve as barriers to prevent/mitigate damage otherwise caused by subsequent implantations.
  • Formation of LDD [0021] Implants 22
  • As shown in FIG. 2 and using [0022] gate electrode stack 18 and the vertical portions of initial oxide spacers 20 as masks, LDD implants 22 are formed through the horizontal portions of oxide layer 19 and into substrate 10 adjacent initial oxide spacers 20 to a depth of preferably from about 300 to 1500 Å and more preferably from about 500 to 1200 Å. BF2, P or As ions are preferably used to form LDD implants 22 and are preferably at a energy of preferably from about 5 to 45 keV.
  • First Embodiment—FIGS. ([0023] 1, 2), and 3 and 5
  • Formation of [0024] Sacrificial Oxide Spacers 26, L-Shaped SiN Spacers 28 and L-Shaped Oxide Spacers 27
  • As shown in FIG. 3, a conformal SiN [0025] dielectric layer 100 is formed over gate electrode stack 18, initial oxide spacers 20, the horizontal portions of oxide layer 19 and STI 12.
  • A [0026] sacrificial oxide layer 102 is then formed over conformal SiN layer 100. Conformal sacrificial oxide layer 102 is preferably comprised of chemical vapor deposition (CVD) oxide (SiO2).
  • Then, a conventional photolithography and etch process is performed to remove: the horizontal portions of [0027] sacrificial oxide layer 102 to form sacrificial oxide spacers 26 having a lower base width of preferably from about 80 to 300 Å and more preferably from about 100 to 200 Å; the underlying portions of conformal SiN layer 100 to form initial L-shaped SiN spacers 28 (leaving a portion of SIN layer 100 over SiN cap 23); and the underlying horizontal portions of oxide layer 19 to complete formation of L-shaped oxide spacers 27.
  • Source/Drain (S/D) [0028] 29 Implantation
  • As shown in FIG. 4, using the [0029] gate electrode stack 18 and sacrificial oxide spacers 26 as masks, source/drain (S/D) implants 29 are formed within substrate 10 adjacent sacrificial oxide spacers 26 to a depth of preferably from about 500 to 2000 Å and more preferably from about 800 to 1500 Å. BF2, P or As ions are preferably used to form S/D implants 29 and are preferably used at an energy of preferably from about 5 to 50 keV.
  • Removal of [0030] Sacrificial Oxide Spacers 26
  • As shown in FIG. 5, the portion of [0031] SiN layer 100 overlying SiN cap 23 is removed to form the final SiN spacers 28 and sacrificial oxide spacers 26 are removed preferably using a wet clean process with chemical HF to complete the structure of the first embodiment.
  • Further processing may then proceed. [0032]
  • Thus, the effective gate length will become wider due to a sacrificial oxide spacer and in the same time without loss of gap fill for the following interlayer dielectric film. It does not change aspect ratio of gate stack to space as well. [0033]
  • Second Embodiment—FIGS. ([0034] 1, 2) and 6 to 9
  • Formation of Conformal SiN [0035] Layer 200
  • As shown in FIG. 6, a conformal SiN [0036] dielectric layer 200 is formed over gate electrode stack 18, initial oxide spacers 20, the horizontal portions of oxide layer 19 and STI 12.
  • Formation of Nitride [0037] Spacers 201 and L-Shaped Oxide Spacers 202
  • As shown in FIG. 7, the conformal SiN [0038] dielectric layer 200 is patterned with the underlying horizontal portions of oxide layer 19 to form: SiN spacers 201; and thus L-shaped oxide spacers 202.
  • Nitride [0039] spacers 201 have a lower base width of preferably from about 150 to 500 Å and more preferably from about 200 to 400 Å.
  • Formation of [0040] Sacrificial Oxide Spacers 204 Over Nitride Spacers 201
  • As shown in FIG. 8, sacrificial oxide (SiO[0041] 2) spacers 204 are formed over nitride spacers 201. Sacrificial oxide spacers 204 are more preferably formed of CVD oxide (SiO2). Sacrificial oxide spacers 204 have a lower base width of preferably from about 80 to 300 Å and more preferably from about 100 to 200 Å.
  • Formation of Source/Drain (S/D) [0042] Implants 206
  • As shown in FIG. 8, using [0043] gate electrode stack 18, sacrificial oxide spacers 204 and nitride spacers 201 as masks, source/drain (S/D) implants 206 are formed within substrate 10 adjacent sacrificial oxide spacers 204 to a depth of preferably from about 500 to 2000 Å and more preferably from about 800 to 1500 Å. BF2, P or As ions are preferably used to form S/D implants 54 and preferably used at an energy of preferably from about 5 to 50 keV.
  • Removal of [0044] Sacrificial Oxide Spacers 204
  • As shown in FIG. 9, [0045] sacrificial oxide spacers 204 are removed from nitride spacers 201 preferably using a wet clean process with chemical HF to complete the structure of the second embodiment.
  • Further processing may then proceed. [0046]
  • Thus, the effective gate length will become wider due to a sacrificial oxide spacer and in the same time without loss of gap fill for the following interlayer dielectric film. It does not change aspect ratio of gate stack to space as well. [0047]
  • Advantages of the Present Invention [0048]
  • The advantages of one or more embodiments of the present invention include effectively broadening the channel length without suffering the aspect ratio. [0049]
  • While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims. [0050]

Claims (17)

I claim:
1. A method of forming a semiconductor device, comprising the sequential steps of:
providing a substrate having a gate electrode stack formed thereover; the substrate having an exposed surface; the gate electrode stack including a lower portion with exposed side walls;
forming a first oxide layer over:
the exposed side walls of the lower portion of the gate electrode stack; and
the exposed surface of the substrate;
forming a conformal dielectric layer over the gate electrode stack and the first oxide layer;
forming a sacrificial dielectric layer over the conformal dielectric layer;
patterning the horizontal portions of the sacrificial dielectric layer, the conformal dielectric layer and the underlying portions of the first oxide layer to form:
sacrificial dielectric spacers;
L-shaped conformal dielectric spacers thereunder; and
L-shaped first oxide layer spacers thereunder;
using the gate electrode stack and the sacrificial dielectric spacers as masks, implanting source/drain implants adjacent the sacrificial dielectric spacers; and
removing the sacrificial dielectric spacers.
2. The method of claim 1, wherein the first oxide layer is comprised of thermal silicon oxide; the conformal dielectric layer is comprised of nitride or silicon nitride; and the sacrificial dielectric layer is comprised of oxide, silicon oxide or CVD silicon oxide.
3. The method of claim 1, wherein the first oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack has a base width of from about 70 to 150 Å and the sacrificial dielectric spacers have a base width of from about 80 to 300 Å.
4. The method of claim 1, wherein the source/drain implants are formed within the substrate to a depth of from about 500 to 2000 Å at an energy of from about 5 to 45 KeV and using ions selected from the group consisting of BF2, P and As.
5. The method of claim 1, including the step of using the gate electrode stack and the first oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack as masks, implanting LDD implants into the silicon substrate adjacent the first thermal layer over the exposed sidewalls of the lower portion of the gate electrode stack before the formation of the conformal dielectric layer.
6. A method of forming a semiconductor device, comprising the sequential steps of:
providing a silicon substrate having a gate electrode stack formed thereover; the silicon substrate having an exposed surface; the gate electrode stack including a lower portion with exposed side walls;
forming a first thermal oxide layer over:
the exposed side walls of the lower portion of the gate electrode stack; and
the exposed surface of the silicon substrate;
using the gate electrode stack and the first thermal oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack as masks, implanting LDD implants into the silicon substrate adjacent the first thermal layer over the exposed sidewalls of the lower portion of the gate electrode stack;
forming a conformal SiN layer over the gate electrode stack and the first thermal oxide layer;
forming a sacrificial oxide layer over the conformal SiN layer;
patterning the horizontal portions of the sacrificial oxide layer, the conformal SiN layer and the underlying portions of the first thermal oxide layer to form:
sacrificial oxide spacers;
L-shaped conformal SiN spacers thereunder; and
L-shaped first thermal oxide layer spacers thereunder;
using the gate electrode stack and the sacrificial oxide spacers as masks, implanting source/drain implants adjacent the sacrificial oxide spacers; and
removing the sacrificial oxide spacers.
7. The method of claim 6, wherein the first thermal oxide layer is comprised of thermal silicon oxide and the sacrificial oxide layer is comprised of oxide, silicon oxide or CVD silicon oxide.
8. The method of claim 6, wherein the first thermal oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack has a base width of from about 70 to 150 Å and the sacrificial oxide spacers have a base width of from about 80 to 300 Å.
9. The method of claim 6, wherein the LDD implants are formed within the silicon substrate to a depth of from about 500 to 2000 Å using ions selected from the group consisting of BF2, P and As; and the source/drain implants are formed within the silicon substrate to a depth of from about 500 to 2000 Å using ions selected from the group consisting of BF2, P and As.
10. A method of forming a semiconductor device, comprising the sequential steps of:
providing a substrate having a gate electrode stack formed thereover; the substrate having an exposed surface; the gate electrode stack including a lower portion with exposed side walls;
forming a first oxide layer over:
the exposed side walls of the lower portion of the gate electrode stack; and
the exposed surface of the substrate;
using the gate electrode stack and the first oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack as masks, implanting LDD implants into the substrate adjacent the first oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack;
forming a conformal dielectric layer over the gate electrode stack and the first oxide layer;
patterning the conformal dielectric layer and the underlying portions of the first oxide layer to form:
conformal dielectric spacers; and
L-shaped first oxide layer spacers thereunder;
forming sacrificial dielectric spacers over the conformal dielectric spacers;
using the gate electrode stack, the conformal dielectric spacers and the sacrificial dielectric spacers as masks, implanting source/drain implants adjacent the sacrificial dielectric spacers; and
removing the sacrificial dielectric spacers.
11. The method of claim 10, wherein the first oxide layer is comprised of thermal silicon oxide; the conformal dielectric layer is comprised of nitride or silicon nitride; and the sacrificial dielectric spacers are comprised CVD oxide or CVD silicon oxide.
12. The method of claim 10, wherein the conformal dielectric spacers have a base width of from about 150 to 500 Å and the sacrificial dielectric spacers have a base width of from about 80 to 300 Å.
13. The method of claim 10, wherein the LDD implants are formed within the substrate to a depth of from about 500 to 2000 Å using ions selected from the group consisting of BF2, P and As; and the source/drain implants are formed within the substrate to a depth of from about 500 to 2000 Å using ions selected from the group consisting of BF2, P and As.
14. A method of forming a semiconductor device, comprising the sequential steps of:
providing a silicon substrate having a gate electrode stack formed thereover; the silicon substrate having an exposed surface; the gate electrode stack including a lower portion with exposed side walls;
forming a thermal oxide layer over:
the exposed side walls of the lower portion of the gate electrode stack; and
the exposed surface of the silicon substrate;
using the gate electrode stack and the thermal oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack as masks, implanting LDD implants into the silicon substrate adjacent the thermal oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack;
forming a conformal dielectric layer over the gate electrode stack and the thermal oxide layer; the conformal dielectric layer being comprised of nitride or silicon nitride;
patterning the conformal dielectric layer and the underlying portions of the thermal oxide layer to form:
conformal dielectric spacers; and
L-shaped thermal oxide layer spacers thereunder;
forming sacrificial dielectric spacers over the conformal dielectric spacers; the sacrificial dielectric spacers being comprised CVD oxide or CVD silicon oxide
using the gate electrode stack, the conformal dielectric spacers and the sacrificial dielectric spacers as masks, implanting source/drain implants adjacent the sacrificial dielectric spacers; and
removing the sacrificial dielectric spacers.
15. The method of claim 14, wherein the conformal dielectric layer is comprised of silicon nitride; and the sacrificial dielectric spacers are comprised CVD silicon oxide.
16. The method of claim 14, wherein the conformal dielectric spacers have a base width of from about 150 to 500 Å and the sacrificial dielectric spacers have a base width of from about 80 to 300 Å.
17. The method of claim 14, wherein the LDD implants are formed within the silicon substrate to a depth of from about 500 to 2000 Å using ions selected from the group consisting of BF2, P and As; and the source/drain implants are formed within the silicon substrate to a depth of from about 500 to 2000 Å using ions selected from the group consisting of BF2, P and As.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060148269A1 (en) * 2004-02-27 2006-07-06 Micron Technology, Inc. Semiconductor devices and methods for depositing a dielectric film
US20070122988A1 (en) * 2005-11-29 2007-05-31 International Business Machines Corporation Methods of forming semiconductor devices using embedded l-shape spacers
KR101226077B1 (en) 2007-11-27 2013-01-24 삼성전자주식회사 Method of forming a sidewall spacer and method of manufacturing a semiconductor device using the same
US20140099751A1 (en) * 2012-10-08 2014-04-10 United Microelectronics Corp. Method for forming doping region and method for forming mos
US20170194455A1 (en) * 2015-12-31 2017-07-06 Taiwan Semiconductor Manufacturing Company Ltd. Spacer structure and manufacturing method thereof
US11362098B2 (en) * 2019-11-20 2022-06-14 Winbond Electronics Corp. Method for manufacturing memory device

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Publication number Priority date Publication date Assignee Title
US20060148269A1 (en) * 2004-02-27 2006-07-06 Micron Technology, Inc. Semiconductor devices and methods for depositing a dielectric film
US20070122988A1 (en) * 2005-11-29 2007-05-31 International Business Machines Corporation Methods of forming semiconductor devices using embedded l-shape spacers
US7759206B2 (en) * 2005-11-29 2010-07-20 International Business Machines Corporation Methods of forming semiconductor devices using embedded L-shape spacers
KR101226077B1 (en) 2007-11-27 2013-01-24 삼성전자주식회사 Method of forming a sidewall spacer and method of manufacturing a semiconductor device using the same
US20140099751A1 (en) * 2012-10-08 2014-04-10 United Microelectronics Corp. Method for forming doping region and method for forming mos
US9209344B2 (en) * 2012-10-08 2015-12-08 United Microelectronics Corp. Method for forming doping region and method for forming MOS
US20170194455A1 (en) * 2015-12-31 2017-07-06 Taiwan Semiconductor Manufacturing Company Ltd. Spacer structure and manufacturing method thereof
US10868141B2 (en) * 2015-12-31 2020-12-15 Taiwan Semiconductor Manufacturing Company Ltd. Spacer structure and manufacturing method thereof
US10937891B2 (en) 2015-12-31 2021-03-02 Taiwan Semiconductor Manufacturing Company Ltd. Spacer structure and manufacturing method thereof
US11362098B2 (en) * 2019-11-20 2022-06-14 Winbond Electronics Corp. Method for manufacturing memory device

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