US20020137292A1 - High voltage metal oxide device with enhanced well region - Google Patents

High voltage metal oxide device with enhanced well region Download PDF

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US20020137292A1
US20020137292A1 US09/808,966 US80896601A US2002137292A1 US 20020137292 A1 US20020137292 A1 US 20020137292A1 US 80896601 A US80896601 A US 80896601A US 2002137292 A1 US2002137292 A1 US 2002137292A1
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region
well
conductivity type
area
implant
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Zia Hossain
Evgueniy Stefanov
Mohammed Quddus
Joe Fulton
Mohamed Imam
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Deutsche Bank AG New York Branch
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Semiconductor Components Industries LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Definitions

  • the present invention relates to semiconductor MOS devices and more specifically to a high voltage metal oxide device with an enhanced n-well region.
  • V BD very high breakdown voltage
  • RDS ON on-resistance
  • V BD and RDS ON have been proposed to form devices with acceptable combinations of V BD and RDS ON .
  • One such family of devices is fabricated according to the reduced surface field (RESURF) principal. These devices utilize an extended drain region (in one embodiment a n-well) to support high off-state voltage (V BD ). These devices have a maximum number of charges in the drain area of about 1 ⁇ 10 12 cm ⁇ 2 before avalanche breakdown occurs. This maximum charge sets up the lowest RDS ON possible since RDS ON is proportional to the charge in the drain region.
  • RESURF reduced surface field
  • some devices utilize a top layer of a conductivity type opposite the extended drain region (in one embodiment a p-type layer) inside the drain region.
  • the top layer allows for a drain region having approximately double the charge than previous designs, which decreases the RDS ON .
  • the top layer helps to deplete the extended drain when the extended drain is supporting high voltage, thus allowing for high breakdown voltage.
  • FIG. 1 is a cross-sectional side view of the device showing an enhanced n-well
  • FIG. 2 is a cross-sectional side view of the device including multiple p-regions
  • FIGS. 3 a , 3 b and 3 c are top views of the device showing different alignments of the p-top layer.
  • FIGS. 4 through 9 illustrate a method for manufacturing the device.
  • the present invention relates to high voltage metal oxide devices (MOS devices) that have a high breakdown voltage and low on resistance. While the discussion below concerns n-channel devices, the discussion also pertains to p-channel devices, which may be formed by reversing the conductivity of the described regions and layers.
  • MOS devices metal oxide devices
  • FIG. 1 illustrates an exemplary n-channel MOS device 100 showing an embodiment of the present invention. Illustrated is a lightly doped p-type substrate region 101 . A N+ source diffusion region 104 is formed at the top of substrate region 101 . A P+ diffusion region 102 is formed adjacent to N+ source diffusion region 104 . The P+ diffusion region 102 increases the integrity of the source to substrate connection as well as reduces the device's susceptibility to parasitic bipolar effects. Associated with the N+ source region 104 and P+ region 102 is a source electrode 116 , which provides electrical contact to the N+ source region 104 and P+ region 102 .
  • An insulating layer 103 (comprising silicon dioxide or some other insulating dielectric material) is formed at the top of the substrate 101 .
  • a gate 105 typically comprising silicon.
  • a gate contact 118 is coupled to the gate 105 .
  • a drain diffusion region 106 is formed at the top of substrate 101 away from source region 104 and connected electrically to drain contact 120 .
  • Drain contact 120 may comprise a number of conductive metals or metal alloys.
  • An optional diffused P region 114 may be formed in the substrate 101 to enclose P+ region 102 and N+ source region 104 .
  • This diffused P region 114 is a lightly doped (high voltage) P-region (PHV) and helps to reduce the device's susceptibility to drain-to-source punch through as well as helps to provide an appropriate threshold voltage.
  • a device including this region is known as a double diffused metal oxide, or DMOS, device.
  • the device is a lateral double diffused metal oxide or LDMOS device.
  • a channel region 115 exists at the top of the substrate 101 from the N+ source region 104 to the end of the diffused region 114 .
  • n-well region 113 comprising a first region of high doping concentration 110 and second region of lower concentration 112 is formed in substrate 101 such that n-well region 113 extends from the surface of substrate 101 adjacent to the channel region 115 and into the substrate 101 and enclosing the drain region 106 .
  • N-well 113 is formed via performing a first n-well implant with a fairly light doping and then forming a second n-well implant inside first n-well implant but laterally offset towards the drain by a fixed amount. This process is shown in FIGS. 5 through 9.
  • the second n-well implant has a much higher concentration of dopants.
  • Second region 112 is formed from where the two implants do not overlap and the concentration of dopants is based on the doping of first n-well implant and the out diffusion of the second n-well implant.
  • the number of charge can approach 2 ⁇ 10 12 cm ⁇ 2 .
  • P-top layer 108 is formed inside n-well 113 for charge balancing.
  • P-top layer 108 may be located adjacent to the top of n-well 113 or implanted inside n-well 113 .
  • more than one p-top layer or layers 108 may be formed within n-well 113 , which is discussed with more detail in FIG. 2.
  • a surface p-top layer 108 allows for downward depletion when voltage is blocked. This, along with the upward depletion from the bottom of n-well 113 , allows for a high breakdown voltage.
  • the increased doping in the first n-well region 110 allows for lower on-resistance.
  • a field oxide layer 107 is formed over n-well 113 to protect the n-well 113 from mobile contaminants.
  • P-top layer 108 can be grounded or left floating.
  • a feature of the present invention is second region 112 .
  • Second region 112 is formed where the first n-well implant and the second n-well implant did not overlap.
  • Second region 112 has a doping concentration based on the doping of the first n-well implant and the out diffusion of the second n-well implant. This provides a lighter doping in a region underlying the gate 105 .
  • the lighter doping in this region provides several advantages. This lighter doping region increases the depletion extension into the n-well region 113 and adjacent to diffused region 114 , which helps prevent premature breakdown due to critical points of the electric field at the surface of the device. One such critical area is by the gate region adjacent to the channel region 115 .
  • Lower doping concentration in this area helps to increase the breakdown voltage when the device is blocking voltage (“off state”). Also, when the device is in the “on” state the surface of the light region becomes accumulated [as if a richer n-well is present] which helps to reduce RDS ON .
  • FIG. 2 is a cross-sectional side view of the device including multiple p-regions 202 . Illustrated is device 100 with an n-well 113 comprising the first region of high concentration 110 offset from the second region of low concentration 112 . Also, illustrated below p-top layer 108 are a plurality of p-regions 202 separated by conductivity channels 204 . These p-regions 202 are formed, for example, by high-energy ion implantation. The conductivity channels 204 can each carry a large charge, which allows for a lower on-resistance.
  • FIG. 3 a is a top view of device 100 . Illustrated is the source region 104 , the adjacent p-region 102 , a drain region 106 and p-top layer 108 , which, in this embodiment, is one solid p-top layer. P-top layer 108 overlies n-well 113 , which, in this illustration overlies the first region 112 of lower concentration and a second region 110 of higher concentration. As discussed in conjunction with FIG. 2, there can be multiple p-regions under the p-top layer 108 . P-top layer 108 also is not necessary at the top but can be below the surface of the n-well 113 .
  • FIG. 3 b represents the same device 100 with p-top layer 108 comprising multiple “stripes” of p-top material, each one separated by a channel region 302 which is parallel to current flow (current will flow from the source to the drain).
  • FIG. 3 c also illustrates n-well 113 having a first region of high dopant concentration 110 and a second region of lower dopant concentration 112 .
  • FIG. 3 c is similar to FIG. 3 b except the “stripes” of p-top material are aligned perpendicular to current flow.
  • n-well 113 is illustrated having a first region of high dopant concentration 110 and a second region of low dopant concentration 112 . While “stripes” are shown in FIGS. 3 b and 3 c , other arrangements of the p-top layers 108 are possible, including individual islands shaped as circulars, squares or polygons.
  • FIGS. 4 through 9 illustrate steps in an exemplary process to manufacture the present invention. These illustrations are for a half-cell.
  • a p substrate 101 is provided.
  • a first n-well implant is performed. In this step dopants are implanted through an opening first mask 502 .
  • the first implant is a low dose implant.
  • Dotted line 504 shows the extent of the first n-well implant.
  • a second n-well implant is performed. In this step, dopants are implanted through an opening in a second mask 602 .
  • Second mask 602 is offset laterally from first mask 502 .
  • the second implant is a higher concentration implant.
  • Solid line 604 shows the extent of the second n-well implant.
  • the order of steps shown in FIGS. 5 and 6 can be interchanged.
  • a heat cycle is performed to cause first n-well and second n-well to diffuse. Due to the fact the second n-well implant was offset from the first n-well implant, after diffusion an n-well region 110 with two distinct regions will be formed. In the offset region, the concentration of dopants is primarily due to the first implant, which was a low concentration implant. This forms a region of low concentration. In the area where the implants overlap, a region of high concentration is formed. N-well 113 is the combination of dotted line 504 and solid line 604 from FIG. 5 and FIG. 6.
  • a p-top implant is performed through a mask opening.
  • a heating cycle is performed to diffuse the p-top layer 108 .
  • a field oxide layer is formed over the p-top layer 108 . This is illustrated in FIG. 9.
  • the gate is formed. This is followed by the PHV implant and a drive step. Then, the p-region in the PHV region is formed along with the n-type source and regions. Then a source/drain anneal is completed. All other steps necessary to complete the device are performed.
  • FIG. 1 illustrates the final device.

Abstract

A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

Description

    FIELD OF THE INVENTION
  • The present invention relates to semiconductor MOS devices and more specifically to a high voltage metal oxide device with an enhanced n-well region. [0001]
    • BACKGROUND OF THE INVENTION
  • When designing high voltage metal oxide (MOS) devices two criteria must be kept in mind. First, the device should have a very high breakdown voltage (V[0002] BD). Second, the device, when operating, should have as low an on-resistance (RDSON) as possible. One problem is that techniques and structures that tend to maximize VBD tend to adversely affect RDSON and vice versa.
  • To overcome this problem, different designs have been proposed to form devices with acceptable combinations of V[0003] BD and RDSON. One such family of devices is fabricated according to the reduced surface field (RESURF) principal. These devices utilize an extended drain region (in one embodiment a n-well) to support high off-state voltage (VBD). These devices have a maximum number of charges in the drain area of about 1×1012 cm−2 before avalanche breakdown occurs. This maximum charge sets up the lowest RDSON possible since RDSON is proportional to the charge in the drain region.
  • To help alleviate this problem, some devices utilize a top layer of a conductivity type opposite the extended drain region (in one embodiment a p-type layer) inside the drain region. The top layer allows for a drain region having approximately double the charge than previous designs, which decreases the RDS[0004] ON. The top layer helps to deplete the extended drain when the extended drain is supporting high voltage, thus allowing for high breakdown voltage.
  • One drawback to this approach is that a high drain concentration under the gate region and adjacent to the channel region can lead to premature breakdown when the device is blocking voltage. Thus, what is needed is a drain region that has a high concentration in most areas but provides for lower concentration under a gate region.[0005]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present invention and advantages thereof, reference is now made to the following descriptions, taken in conjunction with the following drawings, in which like reference numerals represent like parts, and in which: [0006]
  • FIG. 1 is a cross-sectional side view of the device showing an enhanced n-well; [0007]
  • FIG. 2 is a cross-sectional side view of the device including multiple p-regions; [0008]
  • FIGS. 3[0009] a, 3 b and 3 c are top views of the device showing different alignments of the p-top layer; and
  • FIGS. 4 through 9 illustrate a method for manufacturing the device. [0010]
    • DETAILED DESCRIPTION OF THE DRAWINGS
  • The present invention relates to high voltage metal oxide devices (MOS devices) that have a high breakdown voltage and low on resistance. While the discussion below concerns n-channel devices, the discussion also pertains to p-channel devices, which may be formed by reversing the conductivity of the described regions and layers. [0011]
  • FIG. 1 illustrates an exemplary n-[0012] channel MOS device 100 showing an embodiment of the present invention. Illustrated is a lightly doped p-type substrate region 101. A N+ source diffusion region 104 is formed at the top of substrate region 101. A P+ diffusion region 102 is formed adjacent to N+ source diffusion region 104. The P+ diffusion region 102 increases the integrity of the source to substrate connection as well as reduces the device's susceptibility to parasitic bipolar effects. Associated with the N+ source region 104 and P+ region 102 is a source electrode 116, which provides electrical contact to the N+ source region 104 and P+ region 102.
  • An insulating layer [0013] 103 (comprising silicon dioxide or some other insulating dielectric material) is formed at the top of the substrate 101. Over the insulating layer is a gate 105, typically comprising silicon. A gate contact 118 is coupled to the gate 105.
  • A [0014] drain diffusion region 106 is formed at the top of substrate 101 away from source region 104 and connected electrically to drain contact 120. Drain contact 120 may comprise a number of conductive metals or metal alloys. An optional diffused P region 114 may be formed in the substrate 101 to enclose P+ region 102 and N+ source region 104. This diffused P region 114 is a lightly doped (high voltage) P-region (PHV) and helps to reduce the device's susceptibility to drain-to-source punch through as well as helps to provide an appropriate threshold voltage. A device including this region is known as a double diffused metal oxide, or DMOS, device. When the source contact and drain contact are on the same surface, the device is a lateral double diffused metal oxide or LDMOS device. A channel region 115 exists at the top of the substrate 101 from the N+ source region 104 to the end of the diffused region 114.
  • An n-[0015] well region 113 comprising a first region of high doping concentration 110 and second region of lower concentration 112 is formed in substrate 101 such that n-well region 113 extends from the surface of substrate 101 adjacent to the channel region 115 and into the substrate 101 and enclosing the drain region 106. N-well 113 is formed via performing a first n-well implant with a fairly light doping and then forming a second n-well implant inside first n-well implant but laterally offset towards the drain by a fixed amount. This process is shown in FIGS. 5 through 9. The second n-well implant has a much higher concentration of dopants. The combination of those two implants produces first region 110, where the concentration of dopants and, therefore, the charge, is very high. Second region 112 is formed from where the two implants do not overlap and the concentration of dopants is based on the doping of first n-well implant and the out diffusion of the second n-well implant.
  • In [0016] first region 110, in one embodiment, the number of charge can approach 2×1012 cm−2. P-top layer 108 is formed inside n-well 113 for charge balancing. P-top layer 108 may be located adjacent to the top of n-well 113 or implanted inside n-well 113. Alternatively, more than one p-top layer or layers 108 may be formed within n-well 113, which is discussed with more detail in FIG. 2. A surface p-top layer 108 allows for downward depletion when voltage is blocked. This, along with the upward depletion from the bottom of n-well 113, allows for a high breakdown voltage. The increased doping in the first n-well region 110 allows for lower on-resistance. A field oxide layer 107 is formed over n-well 113 to protect the n-well 113 from mobile contaminants. P-top layer 108 can be grounded or left floating.
  • A feature of the present invention is [0017] second region 112. Second region 112 is formed where the first n-well implant and the second n-well implant did not overlap. Second region 112 has a doping concentration based on the doping of the first n-well implant and the out diffusion of the second n-well implant. This provides a lighter doping in a region underlying the gate 105. The lighter doping in this region provides several advantages. This lighter doping region increases the depletion extension into the n-well region 113 and adjacent to diffused region 114, which helps prevent premature breakdown due to critical points of the electric field at the surface of the device. One such critical area is by the gate region adjacent to the channel region 115. Lower doping concentration in this area helps to increase the breakdown voltage when the device is blocking voltage (“off state”). Also, when the device is in the “on” state the surface of the light region becomes accumulated [as if a richer n-well is present] which helps to reduce RDSON.
  • FIG. 2 is a cross-sectional side view of the device including multiple p-[0018] regions 202. Illustrated is device 100 with an n-well 113 comprising the first region of high concentration 110 offset from the second region of low concentration 112. Also, illustrated below p-top layer 108 are a plurality of p-regions 202 separated by conductivity channels 204. These p-regions 202 are formed, for example, by high-energy ion implantation. The conductivity channels 204 can each carry a large charge, which allows for a lower on-resistance.
  • FIG. 3[0019] a is a top view of device 100. Illustrated is the source region 104, the adjacent p-region 102, a drain region 106 and p-top layer 108, which, in this embodiment, is one solid p-top layer. P-top layer 108 overlies n-well 113, which, in this illustration overlies the first region 112 of lower concentration and a second region 110 of higher concentration. As discussed in conjunction with FIG. 2, there can be multiple p-regions under the p-top layer 108. P-top layer 108 also is not necessary at the top but can be below the surface of the n-well 113.
  • FIG. 3[0020] b represents the same device 100 with p-top layer 108 comprising multiple “stripes” of p-top material, each one separated by a channel region 302 which is parallel to current flow (current will flow from the source to the drain). FIG. 3c also illustrates n-well 113 having a first region of high dopant concentration 110 and a second region of lower dopant concentration 112. FIG. 3c is similar to FIG. 3b except the “stripes” of p-top material are aligned perpendicular to current flow. Again, n-well 113 is illustrated having a first region of high dopant concentration 110 and a second region of low dopant concentration 112. While “stripes” are shown in FIGS. 3b and 3 c, other arrangements of the p-top layers 108 are possible, including individual islands shaped as circulars, squares or polygons.
  • FIGS. 4 through 9 illustrate steps in an exemplary process to manufacture the present invention. These illustrations are for a half-cell. First, as shown in FIG. 4, [0021] a p substrate 101 is provided. Next, illustrated in FIG. 5, a first n-well implant is performed. In this step dopants are implanted through an opening first mask 502. The first implant is a low dose implant. Dotted line 504 shows the extent of the first n-well implant. Next, illustrated in FIG. 6, a second n-well implant is performed. In this step, dopants are implanted through an opening in a second mask 602. Second mask 602 is offset laterally from first mask 502. The second implant is a higher concentration implant. Solid line 604 shows the extent of the second n-well implant. The order of steps shown in FIGS. 5 and 6 can be interchanged.
  • Next, as illustrated in FIG. 7, a heat cycle is performed to cause first n-well and second n-well to diffuse. Due to the fact the second n-well implant was offset from the first n-well implant, after diffusion an n-[0022] well region 110 with two distinct regions will be formed. In the offset region, the concentration of dopants is primarily due to the first implant, which was a low concentration implant. This forms a region of low concentration. In the area where the implants overlap, a region of high concentration is formed. N-well 113 is the combination of dotted line 504 and solid line 604 from FIG. 5 and FIG. 6.
  • Next, as illustrated in FIG. 8, a p-top implant is performed through a mask opening. A heating cycle is performed to diffuse the p-[0023] top layer 108.
  • Then, a field oxide layer is formed over the p-[0024] top layer 108. This is illustrated in FIG. 9. In the remaining steps, the gate is formed. This is followed by the PHV implant and a drive step. Then, the p-region in the PHV region is formed along with the n-type source and regions. Then a source/drain anneal is completed. All other steps necessary to complete the device are performed. FIG. 1 illustrates the final device.
  • Thus, it is apparent that there has been provided, an improved semiconductor device. It should be understood that various changes, substitutions, and alterations are readily ascertainable and can be made herein without departing from the spirit and scope of the present invention as defined by the following claims. [0025]

Claims (22)

What is claimed:
1. A DMOS device comprising:
a substrate;
a well region of a first conductivity type formed in the substrate having a first area of high dopant concentration and a second area of low dopant concentration; and
a first region of a second conductivity type formed inside the well region.
2. The device of claim 1, wherein the second area underlies a gate region.
3. The device of claim 1, wherein the well region is formed from two separate well implantation steps.
4. The device of claim 1, wherein the device includes a diffused region of a second conductivity type extending from the surface of the substrate and adjacent to the well region.
5. The device of claim 1, wherein the first region of a second conductivity type is formed at the top of the well region and one or more additional regions of a second conductivity type are formed under the first region, each region separated by a conductivity channel.
6. The device of claim 4, wherein a source region is formed within the diffused region.
7. The device of claim 1, further comprising a drain region formed within the well region.
8. A method for manufacturing a semiconductor device comprising:
forming a well region of a first conductivity type in a semiconductor substrate, the well region having a first area of high dopant concentration and a second area of lower dopant concentration; and
forming a region of a second conductivity type in the well region.
9. The method of claim 8, wherein the step of forming a well region further comprises forming the second area under a gate region adjacent to a channel region.
10. The method of claim 8, wherein the step of forming a region of a second conductivity type comprises forming the region at the top of the well region.
11. The method of claim 8, wherein the step of forming a region of a second conductivity type further comprises forming multiple regions of a second conductivity type in the well region each separated by a conductivity channel.
12. The method of claim 8, further comprising the step of forming a diffused region of a second conductivity type having a first surface bordering the substrate surface.
13. The method of claim 8, wherein the step of forming a well region comprises:
performing a first well implant by implanting a low dose of impurities;
performing a second well implant by implanting a high dose of impurities; the second well implant laterally offset from the first well implant; and
performing a heat cycle to diffuse the first well implant and the second well implant.
14. The method of claim 8, further comprising the step of forming a field oxide layer over the well region.
15. A high voltage DMOS device comprising:
a first region of a first conductivity type formed in a substrate, the region comprising:
a first area of high dopant concentration;
a second area of low dopant concentrations, wherein the second area is laterally offset from the first area;
a second region of a second conductivity type formed in the first region;
a drain region formed within the first region;
a third region of the second conductivity type, the third region a lightly doped, high voltage region; and
a source region formed within the third region.
16. The device of claim 15, wherein the first region is formed by a first implant of low dopant concentration followed by a second implant of high dopant concentration, the second implant laterally offset from the first implant.
17. The device of claim 15, further comprising multiple regions of a second conductivity type formed in the first region, each region separated by a conductivity channel.
18. The device of claim 15, wherein the second area underlies a gate region.
19. A DMOS device comprising:
a substrate of a first conductivity type;
a well region formed by implanting a first area of high dopant concentration of a second conductivity type and a second area of low dopant concentration of a second conductivity type into the substrate; and
a first region formed by implanting impurities of a first conductivity type into the well region.
20. The device of claim 19, wherein the second area is formed adjacent to a channel region.
21. The device of claim 19, wherein the first region is formed below a top portion of the well region by implanting impurities using a high energy implantation.
22. The device of claim 19, wherein multiple regions of the first conductivity type are formed by multiple implantation steps, each step implanting impurities at different energy levels.
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