US20020131541A1 - Spread spectrum modulation technique for frequency synthesizers - Google Patents
Spread spectrum modulation technique for frequency synthesizers Download PDFInfo
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- US20020131541A1 US20020131541A1 US10/051,740 US5174002A US2002131541A1 US 20020131541 A1 US20020131541 A1 US 20020131541A1 US 5174002 A US5174002 A US 5174002A US 2002131541 A1 US2002131541 A1 US 2002131541A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B23/00—Generation of oscillations periodically swept over a predetermined frequency range
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Definitions
- This invention relates generally to phase locked loops for frequency synthesizers and more particularly to phase locked loops for frequency synthesizers which require a spread spectrum feature.
- a frequency synthesizer that has a phase lock loop (PLL) uses a reference signal to generate a desired clock at generally higher frequencies. At these high frequencies, the clock causes electro-magnetic interference (EMI) which disturbs proper operation of electronics devices nearby. To prevent disturbance, synthesizers are required to shield and isolate the clock. Depending on the peak amplitude of the clock, the shielding can be a significant additional cost for manufactures.
- PLL phase lock loop
- the spectrum amplitude can be reduced without curtailing logic HIGH and LOW level by spreading the output clock frequency from the nominal frequency with an external reference frequency.
- microprocessor clock frequency is targeted to spread within ⁇ 0.5% from nominal frequency with 30 kHz to 50 kHz signals. Such a spread spectrum clock has been very difficult to develop.
- the present invention provides a spread spectrum modulation technique which uses digital control logic to switch back and forth between two feedback divider ratios so that the PLL spreads output clock frequency between two limits determined by the ratios.
- the spread spectrum control logic can be integrated into any PLL synthesizer.
- the present invention provides a technique which eliminates the need for complex modulation circuits.
- the present invention further provides a technique which eliminates the need for triangle modulation frequency.
- the present invention still further provides a technique which eliminates the need for a constant modulation frequency source.
- the present invention still further provides for the elimination of a portion of the shielding and isolation required for non-spread spectrum high frequency clocks.
- FIG. 1 shows a graph with the basic PLL clock amplitude spectrum
- FIG. 2 shows a graph with the basic PLL clock timing
- FIG. 3 shows a schematic of a typical PLL clock frequency synthesizer
- FIG. 4 is a graph of a spread sprectrum PLL clock amplitude spectrum of the present invention.
- FIG. 5 is a graph of the spread spectrum PLL clock timing diagram of the present invention.
- FIG. 6 is a schematic of the spread spectrum PLL of the present invention.
- FIG. 7 is a graph of the synchronization system of an alternate embodiment of the present invention.
- FIG. 1 PRIOR ART
- PLL phase lock loop
- FIG. 2 PRIOR ART
- a basic PLL clock timing 12 showing the voltage range from V OL to V OH , and the period of 1/F H .
- FIG. 3 PRIOR ART
- the PLL frequency synthesizer 20 has a reference frequency inputted as F REF 22 into a phase detector divider 24 .
- the phase detector divider 24 provides a divided reference frequency F REF — DIV 26 to a phase detector 28 .
- the phase detector 28 provides an up signal 30 U or a down signal 30 D to a charge pump 32 .
- the signals are selectable but generally set with the up signal 30 U and the down signal 30 D being provided depending on the phase and frequency of F REF — DIV , respectively leading and lagging the phase of F VCO — DIV .
- the charge pump 32 controls current, I CP 34 , to a loop filter 36 .
- the loop filter 36 provides a low frequency voltage, V LF 38 , to a voltage control oscillator (VCO) 40 .
- VCO 40 provides the output frequency, F OUT 42 , of the PLL frequency synthesizer 20 .
- the F OUT 42 is fed back through feedback line 44 to a VCO divider 46 which is connected to provide a divided feedback signal which is a divided VCO frequency, F VCO — DIV 48 , to the phase detector 28 .
- the divide factor for the phase detector 28 is M 50 from the phase detector divider 24 and is N 52 from the VCO divider 46 .
- FIG. 4 therein is shown a spread spectrum PLL clock amplitude spectrum 60 of the present invention.
- the peak amplitudes are shown at F H and F L .
- F L is shown for microprocessor applications as being less than ⁇ 0.5% times F H .
- the clock signal is also shown as being substantially below the fundamental AC amplitude of the PLL clock amplitude spectrum 10 .
- FIG. 5 therein is shown a spread spectrum PLL clock timing diagram 62 with the F H pulses being shown at 64 and the F L pulses being shown at 68 .
- the rise to rise intervals are shown as 1/F H and 1/F L , respectively.
- FIG. 6 therein is shown a spread spectrum PLL frequency synthesizer 70 of the present invention. Where the components are the same as in the typical charge pump-based PLL frequency synthesizer 20 , the same numbers are used.
- the outputs of the phase detector 28 which are up and down signals 30 U and 30 D, respectively, are used as inputs to the phase lock detector 72 .
- the output of the phase lock detector 72 is a lock signal 74 which is inputted to control logic 76 .
- the inputs to the control logic 76 include F REF 22 , F REF — DIV 26 , the feedback clock 44 , and the F VCO — DIV 48 .
- the outputs of the control logic 76 are select high/low reference, SEL_H/L_REF 78 , and select high/low VCO, SEL_H/L_VCO 80 .
- the SEL_H/L_REF 78 is provided to a multiplexer, MUX 82 , which has a high phase detector divider value M H 84 and a low value M L 86 .
- the output of the MUX 82 is provided as the phase detector divider value M′ 88 .
- the SEL_H/L_VCO 80 is provided to a multiplexer, MUX 90 , which has high and low VCO divider values N H 92 and N L 94 .
- the output of the MUX 90 is a VCO divider value N′ 96 .
- FIG. 7 therein is shown a graph of the signals where the spread spectrum PLL frequency synthesizer 70 has the divider values switched at the beginning of each count and synchronized with F REF 22 to provide improved spectrum spreading.
- F REF 22 is provided to the phase detector divider 24 where it is divided by the value M 50.
- the F REF — DIV 26 along with F VCO — DIV 48 are inputted to the phase detector 28 where any phase difference causes either an up or down signal 30 U or 30 D to be provided to the charge pump 32 depending on which signal leads.
- F OUT 42 will have the PLL output clock frequency spread out within F H and F L as given by:
- An ideal phase lock detector 72 would generate a binary output, lock signal 74 when the phase differences between the two inputs, UP signal 30 U and the DOWN signal 30 D, are equal to a constant value.
- phase lock detector 72 can be implemented with digital logic gates that reset an integrator, a technique which is insensitive to process, and changes in temperature and voltage. Therefore, a precise lock condition can be detected.
- control logic 76 The main function of the control logic 76 is to switch back and forth between two feedback divider ratios for F H and F L . Since there are two divider ratios, the loop has two lock conditions. Once a locked condition is detected, the control logic switched back to previous ratio so that the clock frequency is spread over the two limits.
- the amount of spread is strictly to be within ⁇ 0.5% from the non-spread frequency. Therefore, the control voltage V LF must move slowly towards the voltage that synthesizes the next frequency limit. In addition, the longer the loop stays in the locked condition, the greater the spectrum energy at F H or F L .
- Equation (3) will not cause abrupt changes in control voltage and the loop slowly tracks the a small step change. This process continues as long as the control logic 76 is enabled.
- FIG. 4 shows an example of control voltage waveform when the control logic 76 is enabled.
- FIG. 7 illustrates the timing diagram of control logic signals.
- the signals from top to bottom are the VCO divider signal, F VCO — DIV 48 , the reference divider signal, F REF — DIV 26 , the lock signal 74 , the select high/low signals, SEL_H/L_REF 78 and SEL_H/L_VCO 80 , and the loop filter voltage, V LF 38 .
- a phase error between the VCO divider signal, F VCO — DIV 48 and the reference divider signal, F REF — DIV 26 is shown by the gray area in the lock signal 74 .
Abstract
A spread spectrum modulation technique uses digital control logic to switch back and forth between two feedback divider ratios so that the PLL spreads output clock frequency between two limits determined by the ratios. The spread spectrum control logic can be integrated into any PLL frequency synthesizer.
Description
- This invention relates generally to phase locked loops for frequency synthesizers and more particularly to phase locked loops for frequency synthesizers which require a spread spectrum feature.
- A frequency synthesizer that has a phase lock loop (PLL) uses a reference signal to generate a desired clock at generally higher frequencies. At these high frequencies, the clock causes electro-magnetic interference (EMI) which disturbs proper operation of electronics devices nearby. To prevent disturbance, synthesizers are required to shield and isolate the clock. Depending on the peak amplitude of the clock, the shielding can be a significant additional cost for manufactures.
- The higher the peak amplitude is, the worse the EMI. Thus, it is desirable to be able to reduce the peak amplitude while maintaining the high frequency. It has been determined that this can be accomplished by spreading the output clock frequency from the nominal frequency where the peak occurs to other frequencies which are just slightly above and below the nominal frequency.
- The spectrum amplitude can be reduced without curtailing logic HIGH and LOW level by spreading the output clock frequency from the nominal frequency with an external reference frequency. In personal computer applications, microprocessor clock frequency is targeted to spread within −0.5% from nominal frequency with 30 kHz to 50 kHz signals. Such a spread spectrum clock has been very difficult to develop.
- There are several ways the spread spectrum clocks have been implemented in the past. Some used a separate divider circuit to generate a constant modulation frequency such as 30 kHz to 50 kHz. Some multiplexed between two clock sources. Others modulated a control voltage, VLF, with a triangle wave. However, such clock sources had sub-optimal reductions in amplitude spectrum. Moreover, the frequency spreading would not be within the desired specification and vary over the process, and with changes in voltage and temperature.
- While there has been some consideration given to developing digital solutions to the frequency spreading requirement, the difficulty of controlling such a digital solution and preventing the PLL from destabilizing has prevented such a solution.
- Consequently, there exists a need for a spread spectrum modulation technique to precisely spread the clock frequency within specific range over the process and with changes in voltage and temperature without use of a constant reference frequency source.
- The present invention provides a spread spectrum modulation technique which uses digital control logic to switch back and forth between two feedback divider ratios so that the PLL spreads output clock frequency between two limits determined by the ratios. The spread spectrum control logic can be integrated into any PLL synthesizer.
- The present invention provides a technique which eliminates the need for complex modulation circuits.
- The present invention further provides a technique which eliminates the need for triangle modulation frequency.
- The present invention still further provides a technique which eliminates the need for a constant modulation frequency source.
- The present invention still further provides for the elimination of a portion of the shielding and isolation required for non-spread spectrum high frequency clocks.
- FIG. 1 (PRIOR ART) shows a graph with the basic PLL clock amplitude spectrum;
- FIG. 2 (PRIOR ART) shows a graph with the basic PLL clock timing;
- FIG. 3 (PRIOR ART) shows a schematic of a typical PLL clock frequency synthesizer;
- FIG. 4 is a graph of a spread sprectrum PLL clock amplitude spectrum of the present invention;
- FIG. 5 is a graph of the spread spectrum PLL clock timing diagram of the present invention;
- FIG. 6 is a schematic of the spread spectrum PLL of the present invention; and
- FIG. 7 is a graph of the synchronization system of an alternate embodiment of the present invention.
- Referring now to FIG. 1 (PRIOR ART), therein is shown a graph of a basic phase lock loop (PLL)
clock amplitude spectrum 10. The peak amplitude of the clock is at FH. The signal has VOL at logic LOW and VOH at logic HIGH. Therefore, the fundamental AC peak amplitude of the clock is approximately half of VOH-VOL in db. - Referring now to FIG. 2 (PRIOR ART), therein is shown a basic
PLL clock timing 12 showing the voltage range from VOL to VOH, and the period of 1/FH. - Referring now to FIG. 3 (PRIOR ART), therein is shown a typical charge-pump based
PLL frequency synthesizer 20. ThePLL frequency synthesizer 20 has a reference frequency inputted as FREF 22 into aphase detector divider 24. Thephase detector divider 24 provides a divided reference frequency FREF— DIV 26 to aphase detector 28. Thephase detector 28 provides an upsignal 30U or adown signal 30D to acharge pump 32. The signals are selectable but generally set with the upsignal 30U and thedown signal 30D being provided depending on the phase and frequency of FREF— DIV, respectively leading and lagging the phase of FVCO— DIV. Thecharge pump 32 controls current, ICP 34, to aloop filter 36. Theloop filter 36 provides a low frequency voltage,V LF 38, to a voltage control oscillator (VCO) 40. The VCO 40 provides the output frequency,F OUT 42, of thePLL frequency synthesizer 20. - The FOUT 42 is fed back through
feedback line 44 to aVCO divider 46 which is connected to provide a divided feedback signal which is a divided VCO frequency,F VCO— DIV 48, to thephase detector 28. The divide factor for thephase detector 28 isM 50 from thephase detector divider 24 and isN 52 from theVCO divider 46. - Referring now to FIG. 4, therein is shown a spread spectrum PLL
clock amplitude spectrum 60 of the present invention. The peak amplitudes are shown at FH and FL. FL is shown for microprocessor applications as being less than −0.5% times FH. The clock signal is also shown as being substantially below the fundamental AC amplitude of the PLLclock amplitude spectrum 10. - Referring now to FIG. 5, therein is shown a spread spectrum PLL clock timing diagram62 with the FH pulses being shown at 64 and the FL pulses being shown at 68. The rise to rise intervals are shown as 1/FH and 1/FL, respectively.
- Referring now to FIG. 6, therein is shown a spread spectrum
PLL frequency synthesizer 70 of the present invention. Where the components are the same as in the typical charge pump-basedPLL frequency synthesizer 20, the same numbers are used. - The outputs of the
phase detector 28, which are up and downsignals phase lock detector 72. The output of thephase lock detector 72 is alock signal 74 which is inputted to controllogic 76. The inputs to thecontrol logic 76 includeF REF 22, FREF— DIV 26, thefeedback clock 44, and theF VCO— DIV 48. The outputs of thecontrol logic 76 are select high/low reference, SEL_H/L_REF 78, and select high/low VCO, SEL_H/L_VCO 80. - The SEL_H/
L_REF 78 is provided to a multiplexer, MUX 82, which has a high phase detectordivider value M H 84 and alow value M L 86. The output of theMUX 82 is provided as the phase detector divider value M′ 88. - The SEL_H/
L_VCO 80 is provided to a multiplexer,MUX 90, which has high and low VCOdivider values N H 92 andN L 94. The output of theMUX 90 is a VCO divider value N′ 96. - Referring now to FIG. 7, therein is shown a graph of the signals where the spread spectrum
PLL frequency synthesizer 70 has the divider values switched at the beginning of each count and synchronized with FREF 22 to provide improved spectrum spreading. - In operation in the prior art
PLL frequency synthesizer 20 of FIG. 3,F REF 22 is provided to thephase detector divider 24 where it is divided by thevalue M 50. TheF REF— DIV 26 along withF VCO— DIV 48 are inputted to thephase detector 28 where any phase difference causes either an up or downsignal charge pump 32 depending on which signal leads. Thephase detector 28 is in its locked position when theF REV— DIV 26 and theF VCO— DIV 48 are exactly the same, theoutput F OUT 42 is as follows: - where
- FOUT Frequency Output of PLL,
- FREF Input Reference Frequency
- N Voltage Controlled Oscillator (VCO) Divider Value
- M Phase Detector Divider Value.
-
- where
- FH Upper Limit or Nominal Clock Frequency
- FL Lower Limit Clock Frequency
- FREF Input Reference Frequency
- NH or NL VCO Divider Value that synthesizes FH or FL
- MH or ML Phase Detector Divider Value that synthesizes FH or FL
- An ideal
phase lock detector 72 would generate a binary output,lock signal 74 when the phase differences between the two inputs, UP signal 30U and theDOWN signal 30D, are equal to a constant value. - In practice, the
phase detector 28 outputs, upsignal 30U and downsignal 30D, force the input frequencies to be equal and the phase error to be constant. In addition, the frequency difference between divider ratios M′ 88 and N′ 96 are relatively close, about 0.5%. Hence, the uses ofphase detector 28 output only require thephase lock detector 72 to be sensitive enough to the deadband. - As would be obvious to those having ordinary skill in the art, the
phase lock detector 72 can be implemented with digital logic gates that reset an integrator, a technique which is insensitive to process, and changes in temperature and voltage. Therefore, a precise lock condition can be detected. - The main function of the
control logic 76 is to switch back and forth between two feedback divider ratios for FH and FL. Since there are two divider ratios, the loop has two lock conditions. Once a locked condition is detected, the control logic switched back to previous ratio so that the clock frequency is spread over the two limits. - In the microprocessor clock specification, the amount of spread is strictly to be within −0.5% from the non-spread frequency. Therefore, the control voltage VLF must move slowly towards the voltage that synthesizes the next frequency limit. In addition, the longer the loop stays in the locked condition, the greater the spectrum energy at FH or FL.
-
- where
- ΔφH→L maximum phase error between REF_DIV and VCO_DIV when the divider values NL is selected.
- ΔφL→H maximum phase error between REF_DIV and VCO_DIV when the divider values NH is selected.
TABLE 1 An Example of Phase Error Calculation Given by Equation (3). REF FOUT PDF PDF Phase Err. (MHz) (MHz) (kHz) (kHz) (sec) N M Non Spread 14.3180 99.8182 409.0909 899.2628 5.438E−9 244 35 H Mode Spread 14.3180 99.3324 894.8863 407.0999 11.955E−9 111 16 L Mode - Since FH and FL are relatively close, equation (3) will not cause abrupt changes in control voltage and the loop slowly tracks the a small step change. This process continues as long as the
control logic 76 is enabled. FIG. 4 shows an example of control voltage waveform when thecontrol logic 76 is enabled. - A further enhancement is done by synchronization. The
lock signal 74 is sampled with the reference divider signal,F REF— DIV 26, so the dividers will always divide MH or ML without exceeding MH. This is simply done by changing the divider values at the beginning of the count and synchronizing to the reference clock signal,F REF 22. A similar concept is applied for switching N divider values. FIG. 7 illustrates the timing diagram of control logic signals. - The signals from top to bottom are the VCO divider signal,
F VCO— DIV 48, the reference divider signal,F REF— DIV 26, thelock signal 74, the select high/low signals, SEL_H/L_REF 78 and SEL_H/L_VCO 80, and the loop filter voltage,V LF 38. A phase error between the VCO divider signal,F VCO— DIV 48 and the reference divider signal,F REF— DIV 26 is shown by the gray area in thelock signal 74. - While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the spirit and scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Claims (19)
1. A phase lock loop frequency synthesizer having a reference frequency divideable by a first value and a feedback frequency divideable by a second value, the synthesizer comprising:
a first system for providing a plurality of first values;
a second system for providing a plurality of second values; and
a control system for determining when to apply said plurality of said first and second values whereby the synthesizer provides a spread spectrum output frequency.
2. The synthesizer as claimed in claim 1 includes a detector for detecting the difference between the divided reference frequency and the divided feedback frequency to provide an indication thereof and wherein:
said control system is responsive to said detector output to determine when to apply said plurality of first and second values.
3. The synthesizer as claimed in claim 2 including:
a lock detector for determining when the divided reference frequency is equal to the divided feedback frequency to provide a lock signal; and
said control system is responsive to said lock signal to change the application of said plurality of first and second values.
4. The synthesizer as claimed in claim 1 wherein said first system includes a multiplexer for applying a high or low value to divide said reference frequency.
5. The synthesizer as claimed in claim 1 wherein said first system includes a multiplexer for applying a high or low value to divide said feedback frequency.
6. A synthesizer as claimed in claim 1 wherein said control system uses said reference frequency and said divided reference frequency to change said plurality of first values.
7. The synthesizer as claimed in claim 1 wherein said control system uses said feedback frequency and said divided feedback frequency to change said application of said second values.
8. The synthesizer as claimed in claim 1 wherein said control system is responsive to said lock signal and said divided reference frequency to change said application of said first value when said signals are synchronized.
9. The synthesizer as claimed in claim 1 wherein said control system is responsive to said lock signal and said divided feedback frequency to change said application of said second value when said signals are synchronized.
10. The synthesizer as claimed in claim 1 wherein the output of said synthesizer is a spread spectrum within a predetermined range.
11. A phase locked loop frequency synthesizer having a reference frequency divideable by a first value and a feedback frequency divideable by a second value, both of which a provided to a detector for providing signals in response to phase differences in the divided reference and feedback frequencies, the synthesizer comprising:
a first system for providing a high and a low of the first value;
a second system for providing a high and a low of the second value;
a lock detector for detecting the signals from the detector and providing a lock signal when the phases of the divided reference and feedback frequencies are the same;
control logic responsive to said lock signal to cause said first and second systems to provide change between said high and low of the first and second values whereby the synthesizer provides a spread spectrum output frequency within a predetermined spectrum.
12. The synthesizer as claimed in claim 11 wherein the detector for providing signals provides up or down signals in response to the divided reference frequency leading or lagging the divided feedback frequency wherein:
said control logic is responsive to said up or down signals to cause said first and second systems to provide both high or both low first and second values.
13. The synthesizer as claimed in claim 12 wherein:
said control logic is responsive to said lock signal to cause said first and second systems to change from both high or both low first and second values to both low or both high first and second values.
14. The synthesizer as claimed in claim 11 wherein said first system includes a multiplexer for applying a high or low first value to divide said reference frequency.
15. The synthesizer as claimed in claim 11 wherein said first system includes a multiplexer for applying a high or low second value to divide said feedback frequency.
16. The synthesizer as claimed in claim 11 wherein said control system is responsive to said lock signal and said divided reference frequency to change said application of said first value when said signals are in phase.
17. The synthesizer as claimed in claim 11 wherein said control system is responsive to said lock signal and said divided feedback frequency to change said application of said second value when said signals are in phase.
18. The synthesizer as claimed in claim 11 wherein the output frequency of the synthesizer is a spread spectrum within a predetermined range.
19. The synthesizer as claimed in claim 11 wherein the output frequency of the synthesizer is a spread spectrum with the lower frequency 0.5% lower than the higher frequency.
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KR100541548B1 (en) * | 2003-09-08 | 2006-01-11 | 삼성전자주식회사 | Spread spectrum clock generator and method thereof |
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US7676012B1 (en) * | 2004-04-22 | 2010-03-09 | Pulsecore Semiconductor Corp. | Spread spectrum controllable delay clock buffer with zero cycle slip |
US7635997B1 (en) * | 2005-06-29 | 2009-12-22 | Xilinx, Inc. | Circuit for and method of changing a frequency in a circuit |
US7711328B1 (en) | 2005-06-29 | 2010-05-04 | Xilinx, Inc. | Method of and circuit for sampling a frequency difference in an integrated circuit |
TWI282218B (en) * | 2005-07-01 | 2007-06-01 | Realtek Semiconductor Corp | Method of generating spread spectrum and/or over-clock and its circuit thereof |
US7417510B2 (en) * | 2006-09-28 | 2008-08-26 | Silicon Laboratories Inc. | Direct digital interpolative synthesis |
US7764134B2 (en) * | 2007-06-14 | 2010-07-27 | Silicon Laboratories Inc. | Fractional divider |
US8248175B2 (en) | 2010-12-30 | 2012-08-21 | Silicon Laboratories Inc. | Oscillator with external voltage control and interpolative divider in the output path |
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US5631920A (en) * | 1993-11-29 | 1997-05-20 | Lexmark International, Inc. | Spread spectrum clock generator |
US5610955A (en) * | 1995-11-28 | 1997-03-11 | Microclock, Inc. | Circuit for generating a spread spectrum clock |
US6046646A (en) * | 1997-06-13 | 2000-04-04 | Lo; Pedro W. | Modulation of a phase locked loop for spreading the spectrum of an output clock signal |
-
1998
- 1998-09-08 US US09/149,770 patent/US6351485B1/en not_active Expired - Lifetime
-
2002
- 2002-01-16 US US10/051,740 patent/US20020131541A1/en not_active Abandoned
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US20040047440A1 (en) * | 2002-09-10 | 2004-03-11 | Broadcom Corporation | Phase lock loop with cycle drop and add circuitry |
US7088797B2 (en) * | 2002-09-10 | 2006-08-08 | Broadcom Corporation | Phase lock loop with cycle drop and add circuitry |
US20080004707A1 (en) * | 2003-10-23 | 2008-01-03 | Cragg Andrew H | Prosthetic nucleus apparatus and method |
US20070014556A1 (en) * | 2005-07-15 | 2007-01-18 | Truls Persson | Communications devices including integrated digital cameras operating at different frequencies and related methods |
US20070257718A1 (en) * | 2006-04-19 | 2007-11-08 | Anders Ruuswik | Spectrum spreaders including tunable filters and related devices and methods |
US7498871B2 (en) | 2006-04-19 | 2009-03-03 | Sony Ericsson Mobile Communications Ab | Spectrum spreaders including tunable filters and related devices and methods |
EP2391036A1 (en) | 2006-04-19 | 2011-11-30 | Sony Ericsson Mobile Communications AB | Spectrum spreaders including tunable filters and related devices and methods |
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US6351485B1 (en) | 2002-02-26 |
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