US20020097061A1 - Apparatus for probing digital signals within printed circuit boards - Google Patents
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- US20020097061A1 US20020097061A1 US09/731,762 US73176200A US2002097061A1 US 20020097061 A1 US20020097061 A1 US 20020097061A1 US 73176200 A US73176200 A US 73176200A US 2002097061 A1 US2002097061 A1 US 2002097061A1
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
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Abstract
Description
- This invention relates generally to probing digital signals and more specifically to probing digital signals within Printed Circuit Boards (PCBs).
- PCBs comprise a number of microelectronic components that are interconnected in order to perform a particular function or set of functions. Examples of components that could be integrated within a PCB include memory devices, Application Specific Integrated Circuits (ASICs) and processing devices such as Digital Signal Processors (DSPs). The components within a PCB communicate with each other via signal traces from a plurality of drivers to a plurality of receivers. As defined herein below, a driver is an apparatus which outputs a signal while a receiver is an apparatus that receives a signal. It should be understood that normally a microelectronic component within a PCB would comprise one or more drivers along with one or more receivers.
- One critical aspect of a PCB design procedure is the testing of the functionality and connectivity of the various signals being transmitted from one microelectronic component to another. The testing of individual signals within the PCB can allow the designer to ensure that the components are operating properly and that all interconnections between specific drivers and receivers are correct. Further, in the case that components are not operating properly, the testing of the signals within the PCB can allow a designer to isolate the problems.
- One technique for testing the signals within a PCB, as illustrated in FIG. 1A, is the use of internal testing circuitry within the components. Within FIG. 1A, a
first component 30 comprises functional mode andtest mode circuitry driver 36. Thedriver 36 is coupled, via asignal trace 38 to asecond component 40 that comprises areceiver 42 coupled to thesignal trace 38 anddetector circuitry 44 coupled to thereceiver 42. In this case, thefirst component 30 can operate either in functional mode withfunctional mode circuitry 32 or in test mode withtest mode circuitry 34, thecomponent 30 selecting between the two modes with the use of a test signal that can be dictated by a test engineer. If operating in test mode, thedriver 36 outputs a test sequence as dictated by thetest mode circuitry 34 which is received at thereceiver 42 and monitored with the use of thedetector circuitry 44. The test mode circuitry could include such testing procedures as Design For Test (DFT) and Built In Self Test (BIST). - One problem with using internal testing circuitry within the components to test the operation of the PCB is that it is relatively complicated for the test engineer to modify the test software and/or the test parameters within the
test mode circuitry 34. Further, thistest mode circuitry 34 requires considerable silicon space which increases the costs of the components and hence the overall PCB. Yet further, since thetest mode circuitry 34 is distinct from thefunctional mode circuitry 32, it is not possible for the rest engineer to test the components within operation using this technique. - Another technique for testing the signals within a PCB, as illustrated in FIG. 1B, is the use of probing with a test apparatus. In this case, a
driver 50 within afirst component 52 is coupled, via asignal trace 54, to a receiver 56 within asecond component 58, thesignal trace 54 further being probed relatively close to thereceiver 54 by a test apparatus 60. With the use of probes on thesignal trace 54, the test apparatus 60 receives a version of the signal being transmitted on thesignal trace 54, thus allowing the designer to monitor the signal during the functional mode of operation. Further, this technique does not require any circuitry modifications within the actual components. - Unfortunately, there are a number of problems with this technique for testing the signals within a PCB as depicted in FIG. 1B. For one, the
signal trace 54 behaves as a transmission line and so when a high speed signal traversing thesignal trace 54 is probed with a low capacitance probe from the test apparatus 60, the probe itself is equivalent to a stub which can cause severe signal integrity problems, such as reflections, on thesignal trace 54. Further, the test apparatus 60 being coupled to thesignal trace 54 can result in a significant additional load being added to thesignal trace 54. These problems may result in alterations of the signal traversing thesignal trace 54, thus degrading the signal during testing and not providing accurate results of the signal during normal operating parameters. These problems increase in importance as the signal on thesignal trace 54 increases in speed. - Yet further, the probing of signal traces within a PCB are becoming increasingly difficult, if not impossible. The width of a typical signal trace is decreasing while the distance between signal traces is also decreasing, resulting in an increasingly dense array of signal traces within the PCB that is difficult to probe with currently available couplers. An example of a typical dense array of signal traces is illustrated in FIG. 2 between first and
second components - Another difficulty with the probing of signal traces within current PCB designs is the plurality of layers that comprise a PCB. These layers typically include one or more signalling layers as well as a plurality ground layers that surround the signalling layers. This type of design for the PCB can prevent the test engineer from accessing any of the signals that are routed on signal traces inaccessible to the top or bottom of the PCB. To demonstrate this problem, FIGS. 3A and 3B illustrate a sample layer structure for a portion of a PCB (no components illustrated). Within FIG. 3A, the PCB comprises first and
second signalling layers second ground layers first ground layer 84 in this example is on top of thefirst signalling layer 80 while thesecond ground layer 86 is beneath thesecond signalling layer 82. FIG. 3B illustrates thesignalling layers signalling layers - To overcome the above described problem of signal traces that are too narrow to attach probes, it has been well-known to attach small resistors to signal traces so that the test apparatus couplers are able to tap onto the resistors and hence the signal traces. Unfortunately, this solution does not overcome any of the other problems discussed above with reference to probing the signal traces with a test apparatus. For instance, the use of small resistors does not overcome the problem of degrading the signal within the signal trace or the inaccessibility of some signal traces for the test engineer. Additionally, this solution is not practical in high density databus since it would not be possible to implement a resistor for each of the signal traces.
- Hence, there is a need for a new technique for testing signals traversing signal traces of a PCB. Preferably, this technique would not significantly deteriorate the signal traversing the signal traces and would be able to be implemented within dense arrays of signal traces.
- The present invention is directed to an apparatus and method for probing digital signals within a PCB. In the present invention, a sensor apparatus is implemented adjacent to a signal trace in order to receive crosstalk signalling from the signal trace. This sensor apparatus is coupled to a node that can be probed by a test apparatus so that, in essence, the signal trace itself can be probed. This node, hereinafter being referred to as a probing node, can be implemented on the same layer of the PCB as its corresponding sensor apparatus or on a different layer that is more convenient for probing purposes. Further, the sensor apparatus could be implemented on the same layer within the PCB as its corresponding signal trace or alternatively could be implemented on an adjacent layer that still allows the sensor apparatus to receive crosstalk signalling from the signal trace.
- One important advantage of the present invention is the ability to achieve accurate measurements of signals traversing signal traces within a PCB without significantly affecting the signal integrity of the signals traversing the signal trace; this being especially important in high speed designs. This is done through the use of crosstalk signalling between the signal trace and the sensor apparatus, the sensor apparatus generating weak pulses equivalent to those on the signal trace that can be probed by a test apparatus. Another advantage of some implementations of the present invention is the ability to probe signals that would normally not be able to be probed due to the density of the signal trace array or due to the multiple layer implementation of the PCB.
- In a first broad aspect, the present invention is an arrangement including a primary signal trace, a victim signal trace local to the primary signal trace and a probing node coupled to the victim signal trace. In this aspect, the primary signal trace operates to communicate signals between first and second components, the victim signal trace operates to receive crosstalk signalling from the primary signal trace; and the probing node is adapted for probing by a test apparatus.
- The present invention, according to a second broad aspect, is an arrangement including first and second differential signal traces, at least one victim signal trace local to one of the first and second differential signal traces and at least one probing node coupled to the at least one victim signal trace. According to this aspect, the first and second differential signal traces operate to communicate signals between first and second components, the victim signal trace operates to receive crosstalk signalling from the differential signal trace that is local and the at least one probing node is adapted for probing by a test apparatus.
- In other aspects, the present invention is a Printed Circuit Board (PCB) incorporating one of the arrangements of the first and second aspects. In one case, the PCB comprises a single layer that includes the primary signal trace (the differential signal traces in the second aspect), the victim signal trace and the probing node. In another case, the PCB comprises at least first and second layers, the first layer including the primary signal trace (the differential signal traces in the second aspect) and the victim signal trace and the second layer including the probing node. In this situation, the second layer is one of primary and secondary layers within the PCB and the probing node is coupled to the victim signal trace through a via coupling the first and second layers. In yet a further case, the PCB comprises at least first and second adjacent layers, the first layer including the primary signal trace (the differential signal traces in the second aspect) and the second layer including the victim signal trace. In this aspect, the victim signal trace is approximately located within the second layer at the same location as the primary signal trace (the one of the differential signal traces in the second aspect) is located within the adjacent first layer.
- According to a third broad aspect, the present invention is a method of probing a signal trace that operates to communicate signals between first and second components. The method includes receiving crosstalk signalling from the primary signal trace and routing the crosstalk signalling to a node that is adapted for probing by a test apparatus.
- According to a fourth broad aspect, the present invention is an arrangement including means for communicating signals between first and second components, means for receiving crosstalk signalling from the means for communicating signals, the crosstalk signalling corresponding to the signals being communicated, and means for probing the crosstalk signalling by a test apparatus.
- Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
- The invention will now be described with reference to the following figures, in which:
- FIGS. 1A and 1B illustrate block diagrams of well-known testing techniques within a PCB;
- FIG. 2 illustrates a simple example of a PCB with a dense array of signal traces;
- FIGS. 3A and 3B illustrates an overall view and a more detailed view respectively of a sample multi-layer PCB;
- FIG. 4 illustrates a possible implementation of the present invention within a PCB;
- FIG. 5 illustrates an equivalent circuit for two transmission lines in parallel;
- FIGS. 6A and 6B illustrate possible implementations of the present invention within multi-layer PCBs;
- FIGS. 7A, 7B and7C illustrate possible implementations of the present invention within multi-layer PCBs in which a sensor apparatus is on a separate layer to its corresponding signal trace;
- FIGS. 8A and 9B illustrate alternative embodiments for the sensor apparatus of any one of FIGS. 4, 6A,6B, 7A, 7B and 7C; and
- FIG. 9 illustrates a possible implementation of the present invention within a PCB utilizing differential signals.
- Embodiments of the present invention are directed to probing techniques within PCBs. As will be described herein below, the designs of PCBs according to the present invention utilize sensor apparatus to detect signals traversing signal traces within a PCB and further connect the sensor apparatus to corresponding probing nodes that allow a test apparatus to monitor these detected signals. These designs, in essence, allow a test apparatus, such as a Hewlett Packard (HP) high speed tester, to probe the actual signal traces within the PCB.
- FIG. 4 illustrates a possible implementation of the present invention within a PCB. In this implementation, the PCB comprises a
signalling layer 90 which includes adatabus 92 of four signal traces, one of the signal traces beingsignal trace 94. As depicted within FIG. 4, each of the signal traces of thedatabus 92 has acorresponding sensor apparatus 96 adjacent to it, thesensor apparatus 96 ofsignal trace 94 having a higher scaledview 98 also depicted. As shown in this higher scaledview 98, thesensor apparatus 96 of FIG. 4 comprises avictim signal trace 100 that is in parallel with the signal trace of interest, signaltrace 94 in this case, and anode 102 coupled to thevictim signal trace 100. Thevictim signal trace 100 receives crosstalk signalling from the corresponding signal trace of thedatabus 92, this crosstalk signalling in ideally designed circumstances being a relatively accurate approximation of the digital signals traversing thesignal trace 94. A more detailed description of the crosstalk signalling will be described herein below with reference to FIG. 5. - The
node 102 of FIG. 4 can be utilized in a number of different manners depending upon the circumstances. In one implementation, thenode 102 could be a probing node with which a test apparatus can attach a coupler in order to monitor the signals detected with thevictim signal trace 100, these signals hereinafter being referred to as victim signals. In this case, the PCB of FIG. 4 must not have any further layers implemented with thesignalling layer 90 that cover thenode 102, the dimensions ofnode 102 must be sufficient for a coupler from the test apparatus to be connected and the distance between signal traces of thedatabus 92 must be sufficient to fit the required dimensions of thenodes 102 along with appropriate isolation of thenodes 102 from the other signal traces. In another implementation in which the PCB of FIG. 4 is a multi-layer PCB, thenode 102 could be a via node to which a via couples thesensor apparatus 96 to a probing node on another layer of the PCB as will be described in detail herein below with reference to FIGS. 6A and 6B. This situation is necessary if a test apparatus does not have access tolayer 90 since it is not the primary or secondary layers (i.e. the top or bottom layers). Further, it might be necessary if the distance between the signal traces is not sufficient to implement thenodes 102 as probing nodes. - In the particular implementation illustrated within FIG. 4, the widths of the signal traces of the databus and the victim signal traces100 are 5 mil while the distance between the signal traces of the
databus 92 and their corresponding victim signal traces 100 is also approximately 5 mil. These are approximately the minimum dimensions that are currently achievable within PCBs. - FIG. 5 illustrates an equivalent circuit for portions of two transmission lines in parallel, this circuit representing the coupling relationship between the
signal trace 94 and the correspondingvictim signal trace 100 of FIG. 4. As illustrated in FIG. 5, adriver 110 is coupled to areceiver 112 via afirst transmission line 114 while asecond transmission line 116 is in parallel with thefirst transmission line 114. To represent portions of the first andsecond transmission lines transmission line inductor 118 and a firsttransmission line resistor 120 coupled in series between first andsecond nodes first transmission line 114; a first transmissionline grounding resistor 126 coupled between thesecond node 124 and ground; a secondtransmission line inductor 128 coupled in series with a secondtransmission line resistor 130 between first andsecond nodes second transmission line 116; agrounding resistor 136 coupled between thesecond node 134 and ground; and acrosstalk capacitor 138 coupled between thesecond nodes - As illustrated in FIG. 5, the inductance of the
inductors transmission lines transmission lines resisters transmission lines resisters transmission lines capacitor 138 is represented by CmΔz, where Cm is the mutual capacitance between the twotransmission lines transmission lines inductors - The
second transmission line 116 within FIG. 5 can receive both forward and reverse crosstalk signals from thefirst transmission line 114 while signals are traversing thefirst transmission line 114. Herein below is a description of the mathematical approximations of the voltage levels within thesecond transmission line 116 that result from forward and reverse crosstalk signalling while signals traverse afirst transmission line 114. -
-
- where Z0 is the characteristic impedance. Looking at formulae (1) and (2), it can be seen that the voltage on the
second transmission line 116 as a result of forward crosstalk signalling will be approximately equal to the change in the voltage on thefirst transmission line 114 multiplied by the length of thesecond transmission line 116 and further multiplied by the factor KF that is based upon the mutual inductance and capacitance between thetransmission lines second transmission line 116. - For the reverse crosstalk signals, the resulting voltage on the
second transmission line 116 can be approximated using the following formula: - V R =K R ·V inc (3)
-
- where Tprop is the unit transmission line delay time of propagation of the voltage Vinc on the
first transmission line 114. Looking at formulae (3) and (4), it can be seen that the voltage on thesecond transmission line 116 as a result of reverse crosstalk signalling will be approximately equal to the voltage on thefirst transmission line 114 multiplied by the factor KR that is based upon the mutual inductance and capacitance between thetransmission lines first transmission line 114. It is noted that, the inductance and capacitance levels within the factor KR are additive and this factor KR is directly proportional to the level of combined inductance and capacitance between thetransmission lines first transmission line 114. - Now referring back to the possible implementation of the present invention depicted within FIG. 4, it should be understood that the crosstalk signalling detected at the
victim signal trace 100 due to signals traversing thesignal trace 94 is comparative to the crosstalk signalling detected at thesecond transmission line 116 due to signals traversing thefirst transmission line 114. In ideal cases, the designer would eliminate the forward crosstalk signalling detected on thevictim signal trace 100 by adjusting the mutual inductance and capacitance between thesignal trace 94 and thevictim signal trace 100. With this elimination, the crosstalk signalling detected at thevictim signal trace 100 would be an approximate representation of the signals traversing thesignal trace 94. - There are numerous factors that influence the effectiveness of the
victim signal trace 100 to detect an accurate representation of the signals traversing thesignal trace 94. For one, the length of the victim signal trace and the distance between thesignal trace 94 andvictim signal trace 100 can improve the strength of the reverse crosstalk signalling and hence increase the accuracy of detection for the signals traversing thesignal trace 94. Through the lengthening of thevictim signal trace 100 and the decreasing of space between thesignal trace 94 and thevictim signal trace 100, one could increase the mutual inductance and capacitance between the signal traces 94,100 and therefore allow for stronger reverse crosstalk signalling. It is noted that the increase in strength of the reverse crosstalk signalling due to lengthening thevictim signal trace 100 can be saturated such that the lengthening of thevictim signal trace 100 after a threshold point, does not increase the strength of the reverse crosstalk signalling significantly. Further, it is noted the minimum possible distance between thesignal trace 94 and thevictim signal trace 100 is defined by PCB manufacturers' limitations. Currently, this limitation is approximately 4.5-5 mil. - Other factors that influence the effectiveness of the
victim signal trace 100 to accurately detect signals traversing thesignal trace 94 are the rise time at the edge of digital signals and the strength of the driver that is used to generate the signals traversing thesignal trace 94. Both of these factors are not controlled by the PCB designer, but must be considered when designing the sensor apparatus of the present invention. For instance, a relatively slow rise time at the edge of digital signals may require an increase in the length of thevictim signal trace 100 and/or a decrease in the distance between the signal traces 94, 100 to compensate. Further, the use of a strong voltage driver, such as a CMOS driver, or a weaker current driver, such as an LVDS driver, could force a PCB designer to adjust thesensor apparatus 96 of the present invention accordingly. - Essentially, an increase in the length of the victim signal trace100 a decrease in the distance between the signal traces 94, 100, an increase in the rise time of the signals traversing the
signal trace 94 and an increase in the strength of the driver all will lead to an increase in reverse crosstalk signalling and, hence should lead to an increased accuracy at thevictim signal trace 100 of the signals traversing thesignal trace 94. - Although a possible design of a PCB according to the present invention was described herein above with reference to FIG. 4, the present invention should not be limited to this embodiment. In particular, implementations are possible within multi-layer PCB designs as will be described herein below with reference to FIGS. 6A and 6B; modifications with respect to the location of the
sensor apparatus 96 relative to thesignal trace 94 are possible as will be described herein below with reference to FIGS. 7A through 7C; modifications with respect to the design of thevictim signal trace 100 are possible as will be described with reference to FIGS. 8A and 8B; and further alternative embodiments of the present invention are possible, one of which will be described herein below with reference to FIG. 9 for differential signal designs. - FIG. 6A illustrates a possible implementation of the present invention within a multi-layer PCB. As described above, the
node 102 of the sensor apparatus could be a via node that is coupled through a via to another layer in a multi-layer PCB, the other layer being either the primary or secondary layer of the PCB and further having sufficient space to place a probing node of sufficient dimensions for a test apparatus. As depicted in FIG. 6A, thelayer 90 previously described above withdatabus 92 andsensor apparatus 96 is a signalling layer within a multi-layer PCB that further comprises afirst grounding layer 140 implemented below thelayer 90, asecond grounding layer 142 implemented above thelayer 90 and atest probe layer 144 implemented above thesecond grounding layer 142 as the primary layer for the PCB. As depicted in FIG. 6A, thetest probe layer 144 comprises a plurality oftest probe apparatus 146 that are coupled to thesensor apparatus 96 with vias that run betweenlayers layer 142. Also illustrated in FIG. 6A is a higher scale view 148 of thetest probe apparatus 146, each of thecest probe apparatus 146 comprising a vianode 150 that is coupled to the respective vianode 102 within therespective sensor apparatus 96 and a probingnode 152 that is coupled to the vianode 150. In this embodiment, each of the probingnodes 152 are of sufficient dimensions to allow a test apparatus to probe the node with the use of a coupler. With the implementation of FIG. 6A, victim signals detected at any of the victim signal traces 100 can be monitored by a test apparatus that attaches couplers to the probingnodes 152. - It should be noted that the present invention should not be limited to the multi-layer implementation of FIG. 6A. The layer structure of the PCB could be considerably different from that illustrated in FIG. 6A while still utilizing the present invention. For one, the
test probe layer 144 could be a separate layer utilized exclusively for test probe apparatus or, alternatively, could be a layer utilized for other purposes, such as signalling, but that is accessible to couplers of a test apparatus. Further, additional layers could be added within the PCB and those layers that are depicted could be removed. In one alternative, one or more additional signalling layers could be implemented between the signallinglayer 90 and thetest probe layer 144. In this case, it might not be possible to route the victim signals directly from thesensor apparatus 96 to thetest probe apparatus 146 due to the interference of other signal traces. In this case, it would be necessary to route the victim signals from the sensor apparatus to another signalling layer and across the other signalling layer to a point where the victim signals can be routed to thetest probe layer 144 through vias. In other cases, it might be necessary to do routing on more than one other signalling layer in order to route the victim signals to thetest probe layer 144. - FIG. 6B illustrates another possible implementation of the present invention within a multi-layer PCB. In this implementation, the
test probe apparatus 146 are replaced withtest probe apparatus 160 which, as illustrated in ahigher scale view 162, comprise the vianode 150, thetest probe node 152 and an amplifier/Pulse Recovery (PR) unit 164 coupled between thenodes - FIGS. 7A, 7B and7C illustrate possible implementations of the present invention within multi-layer PCBs in which the
sensor apparatus 96 is on a separate layer to itscorresponding signal trace 94. This might be required in cases in which the distance between signal traces within a databus are not sufficient for the implementing of sensor apparatus between the signal traces. Within FIG. 7A, the PCB comprises thesignalling layer 90 and asensor apparatus layer 170 implemented above thelayer 90. In this case, as depicted within a higher scale view 172 of thesensor apparatus 96 withinlayer 170 and thesignal trace 94, thevictim signal trace 100 is adjacent to thesignal trace 94 within the vertical plane, hereinafter referred to as broadside coupling. Thevictim signal trace 100, similar to the description above for the implementation of FIG. 4, receives crosstalk signalling from thesignal trace 94, this crosstalk signalling allowing thesensor apparatus 96 to generate an approximation of the actual signals traversing through thesignal trace 94. - It should be noted that the
sensor apparatus layer 170 could be a layer exclusively used for sensor apparatus or could alternatively be used for other functions as well. For instance, the implementation of FIG. 7B replaces thesensor apparatus layer 170 with asecond signalling layer 174,layer 174 comprising signal traces 176 along with at least onesensor apparatus 96. In another alternative, the implementation of FIG. 7C replaces thesensor apparatus layer 170 of FIG. 7A with agrounding layer 178. In this case, thesensor apparatus 96, as illustrated within ahigher scale view 182, is surrounded by anisolation region 180 which isolates thesensor apparatus 96 from the ground plane of thegrounding layer 178. - It should be further noted that any of the implementations of FIGS. 7A through 7C could be implemented as described previously with reference to FIG. 4 in which the
node 102 is a probing node or alternatively, as described previously with reference to FIGS. 6A and 6B, in which thenode 102 is a via node which is coupled to a probing apparatus on one of the primary or secondary layers. - FIGS. 8A and 8B illustrate alternative embodiments for the sensor apparatus depicted within the implementations of FIGS. 4, 6A,6B, 7A, 7B and 7C. These two alternative implementations of the sensor apparatus illustrate two possible modifications within the sensor apparatus in order to ensure impedance matching. Impedance matching is advantageous since reflections could be generated on the
victim signal trace 100 if there is impedance mismatching, these reflections being transferred to thecorresponding signal trace 94 and thus deteriorating any signals traversing this signal trace. As depicted in FIG. 8A, the sensor apparatus comprises thevictim signal trace 100 with thenode 102 coupled to one end and atermination device 190 coupled to the other end. As depicted in FIG. 8B, the sensor apparatus comprises thevictim signal trace 100 with afirst termination device 192 coupled to one end and asecond termination device 194 coupled to the other end, thenode 102 further being coupled to thevictim signal trace 100. In the cases depicted in FIGS. 8A and 8B, the termination devices are resistors, though it should be recognized that alternative devices that would result in impedance matching could be utilized. - Although a number of implementation of the present invention have been described herein above, these specific implementations should not limit the scope of the present invention. For example, rather than utilizing single ended signal traces, many current PCBs utilize differential signal traces. The use of differential signal traces becomes increasingly necessary as the speed of the signals increases, though it should be noted that the use of differential signal traces significantly increases the required distance (currently approx. 25 mil) that is used to separate the individual differential signal traces. FIG. 9 illustrates a possible implementation of the present invention within a PCB utilizing differential signals. Within FIG. 9, the PCB comprises a
signalling layer 200 that includes differential signal traces 202, 204. The differential signal traces 202, 204 each have asensor apparatus 96 adjacent to them. This is illustrated in detail within ahigher scale view 206 of thesensor apparatus 96 within FIG. 9. - It should be understood that alternative implementations to the PCB of FIG. 9 are possible. For instance, only a
single sensor apparatus 96 could be used rather than two as described with reference to FIG. 9. This implementation is possible if the common noise from the signal traces 202,204 is within the designer's acceptable range. In the case of twosensor apparatus 96 being utilized as depicted in FIG. 9, the differential sensor apparatus allow the test apparatus to cancel the common noise. Further, alternatives as described with reference to FIGS. 6A, 6B, 7A through 7C, 8A and BB can also be made in circumstances in which differential signal traces are utilized. - There are numerous advantages of the present invention over previous techniques for testing signals within a PCB. For one, the use of implementations of the present invention can reduce the load being added to the signal traces. The present invention does not eliminate the loading on the signal traces that are being probed but can significantly reduce such loading compared to traditional probing techniques in which the couplers of the test apparatus are directly coupled to the signal traces of interest. This reduces within the present invention the decline in signal integrity caused by the probing of signal traces within a PCB compared to previous probing techniques.
- Further, as described above, some implementations of the present invention can be implemented within PCB designs that have an extremely high dense array of signal traces. Yet further, embodiments of the present invention allow for vias that are not exposed on the primary or secondary layers, commonly referred to as micro-vias, to be probed and allow buried signal traces that cannot be traced by traditional methods to be probed.
- Persons skilled in the art will appreciate that there are alternative implementations and modifications possible to use an apparatus similar to that described above to reduce peak power periods within data signals, and that the above implementation is only an illustration of this embodiment of the invention. The scope of the invention, therefore, is only to be limited by the claims appended hereto.
Claims (42)
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US09/731,762 US6445204B1 (en) | 2000-12-08 | 2000-12-08 | Apparatus for probing digital signals within printed circuit boards |
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US20020097061A1 true US20020097061A1 (en) | 2002-07-25 |
US6445204B1 US6445204B1 (en) | 2002-09-03 |
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US09/731,762 Expired - Lifetime US6445204B1 (en) | 2000-12-08 | 2000-12-08 | Apparatus for probing digital signals within printed circuit boards |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20040163058A1 (en) * | 2003-02-19 | 2004-08-19 | Frank Mark D. | System and method for evaluating signal coupling between differential traces in a package design |
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US20130154411A1 (en) * | 2011-12-16 | 2013-06-20 | Continental Automotive Systems, Inc. | Electromagnetic compatibility printed circuit board |
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US5365205A (en) | 1993-05-20 | 1994-11-15 | Northern Telecom Limited | Backplane databus utilizing directional couplers |
US5751152A (en) * | 1996-05-14 | 1998-05-12 | Microtest, Inc. | Method and apparatus for concurrently measuring near end crosstalk at two ends of a cable |
US5764489A (en) * | 1996-07-18 | 1998-06-09 | Compaq Computer Corporation | Apparatus for controlling the impedance of high speed signals on a printed circuit board |
US5983006A (en) * | 1997-12-31 | 1999-11-09 | Intel Corporation | Method for analyzing and efficiently eliminating timing problems induced by cross-coupling between signals |
US6128769A (en) * | 1997-12-31 | 2000-10-03 | Intel Corporation | Method for analyzing and efficiently reducing signal cross-talk noise |
US6243653B1 (en) * | 1998-08-17 | 2001-06-05 | Vlsi Technology, Inc. | Methods and apparatus for extracting parasitic capacitance values from a physical design of an integrated circuit |
US6225816B1 (en) * | 1999-04-08 | 2001-05-01 | Agilent Technologies, Inc. | Split resistor probe and method |
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Cited By (6)
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US20040163058A1 (en) * | 2003-02-19 | 2004-08-19 | Frank Mark D. | System and method for evaluating signal coupling between differential traces in a package design |
US7117464B2 (en) * | 2003-02-19 | 2006-10-03 | Hewlett-Packard Development Company, L.P. | System and method for evaluating signal coupling between differential traces in a package design |
US20060236276A9 (en) * | 2003-02-19 | 2006-10-19 | Frank Mark D | System and method for evaluating signal coupling between differential traces in a package design |
CN1320494C (en) * | 2003-07-25 | 2007-06-06 | 三星电子株式会社 | Touch screen system and control method therefor capable of setting active regions |
US20130154411A1 (en) * | 2011-12-16 | 2013-06-20 | Continental Automotive Systems, Inc. | Electromagnetic compatibility printed circuit board |
US9072183B2 (en) * | 2011-12-16 | 2015-06-30 | Continental Automotive Systems, Inc. | Electromagnetic compatibility printed circuit board |
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