US20020067193A1 - Common bias and differential structure based dll with fast lockup circuit and current range calibration for process variation - Google Patents
Common bias and differential structure based dll with fast lockup circuit and current range calibration for process variation Download PDFInfo
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- US20020067193A1 US20020067193A1 US09/730,890 US73089000A US2002067193A1 US 20020067193 A1 US20020067193 A1 US 20020067193A1 US 73089000 A US73089000 A US 73089000A US 2002067193 A1 US2002067193 A1 US 2002067193A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0898—Details of the current generators the source or sink current values being variable
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Definitions
- the present invention relates generally to delay locked loop (DLL) circuits. More particularly, this invention relates to a DLL circuit which is based on a variable length plurality of differential delay elements, an advanced common biasing technique which tolerates process variations and calibrates current range for operational variances and lock detection for faster processing.
- DLL delay locked loop
- Delay-locked loops are often used in the I/O interfaces of digital integrated circuits in order to hide clock distribution delays and to improve overall system timing.
- the demand has risen for devices capable of high-speed processing.
- the demand for DLL circuits that quickly compensate for electronic noise and capacitive delays has also risen.
- this prior art DLL circuit is a self-biasing configuration which is composed of a phase comparator, charge pump, loop filter, bias generator and a plurality of delay cells.
- devices dependent on a precisely delayed clock signal must delay processing for a standardized time period to insure that the received signal is exact. This processing delay is caused by the fact that most DLL circuits are designed to tolerate the worst case conditions.
- the DLL circuit performance during this worst case condition is the processing delay time set for most devices using the output of this circuit.
- This prior art design uses a constant charge pump current which gives rise to a constant damping factor and a constant loop bandwidth.
- a constant bandwidth can constrain the achievement of a wide operating frequency range and low input tracking jitter. If the frequency is disturbed, the phase error that results from each cycle of the disturbance will accumulate for many cycles until the loop can compensate for the phase error. The error will be accumulated for a number of cycles, which is proportional to the operating frequency divided by the loop bandwidth. Thus the loop bandwidth would have to be positioned as close as possible to the reference frequency bandwidth to minimize the total phase error. The result is that the frequency bandwidth must be conservatively set for stability at the lowest operating frequency with worst case process variations rather than set for optimized jitter performance.
- the self-biased DLL also exhibits much faster locking times only when locking from similar or higher operating frequencies. However, if the self-biased DLL is started at a very low operating frequency, it will exhibit very slow locking times.
- the present invention is a DLL circuit which is based on a common bias technique, comprising a plurality of differential delay elements, a fast lock-up circuit and a self-calibration current range setting circuit. This design provides improved speed in detecting and locking to an incoming signal.
- the invention also extends the DLL operating range, improves DLL jitter performance, provides greater immunity to environmental noise, and improves the power supply rejection ratio (PSRR).
- PSRR power supply rejection ratio
- FIG. 1 is a block diagram of a typical DLL circuit
- FIG. 2 is a block diagram of the circuit in accordance with the preferred embodiment of the present invention.
- FIG. 3A is a logic gate diagram of the lock circuit in accordance with the preferred embodiment of the present invention.
- FIG. 3B is a state diagram of the lock circuit inputs in accordance with the preferred embodiment of the present invention.
- FIG. 3C is a logic table for the lock circuit in accordance with the preferred embodiment of the present invention.
- FIG. 4A is a diagram of the bias generator and a delay element in accordance with the preferred embodiment of the present invention.
- FIG. 4B is a diagram of a representation of the configuration of the delay elements with the switching circuit.
- FIG. 5 is an example of a graph of four I-V curves in accordance with the preferred embodiment of the present invention.
- FIG. 6 is a flow diagram in accordance with the preferred embodiment of the present invention.
- the DLL circuit 10 includes a phase frequency detector (PFD) 11 , a lock circuit 12 , a charge pump 13 , a charge pump control circuit 14 , a loop filter 15 including a capacator C 1 (not shown), a common bias generator 16 , a current range control circuit 17 , a delay cell switching circuit 21 and a plurality of delay cells 20 a . . . 20 n.
- the PFD 11 receives a reference signal F ref from an outside source, a reset signal DLL reset and the DLL output signal F o . Coupled to the PFD 11 are the lock circuit 12 and the charge pump 13 .
- the PFD 11 determines the phase difference between the reference signal F ref and the DLL 10 output signal F o . If the PFD 11 detects a phase difference between the two input signals F ref , F o , the phase error signals U, D are sent to the lock circuit 12 and the charge pump 13 . The duration (pulse width) of these output signals U, D depends on the amount of phase error that is detected by the PFD 11 .
- the lock circuit 12 shown in FIG. 3A, is controlled by the phase error signals U, D output from the PFD 11 . Coupled to the PFD 11 and the current range control circuit 17 , the lock circuit 12 monitors the crossing of the phase of the DLL output signal F o and the phase of the reference signal F ref , as will be disclosed hereinafter.
- the lock circuit 12 comprises a plurality of invertors 3 , a plurality of AND gates 5 , two S-R flip flops 7 and a delay 9 .
- the lock circuit 12 detects the crossing of the phase of the two signals F o , F ref , the lock circuit 12 provides an output Q 3 to the current range control circuit 17 to remain at the present bias current level.
- the output Q 3 of the lock circuit 12 as the DLL circuit 10 attempts to match the phase of the output signal F o with the phase of the reference signal F ref , is illustrated in the logic table of FIG. 3C.
- the error signals U, D are in the neutral state 0, 0. Since the output frequency F o is out of phase with the reference frequency F ref , the error signals U, D go to a state 0, 1 indicating that the loop filter 15 capacitor C 1 must be charged. On the subsequent rising edge of the reference frequency F ref , the error signals U, D go to a state 1, 1. This state causes the PFD 11 to reset and return the error signals U, D to their neutral state 0, 0. This process continues until the phase of the output frequency F o passes the phase of the reference frequency F ref which is indicated by the error signals U, D going to a state 1, 0. This condition will signal the lock circuit 12 to output a logical one (1) to the current range control circuit 17 , indicating that the current range control circuit 17 should maintain the bias current at the present level which will be described in greater detail hereinafter.
- the lock circuit 12 operates to quickly detect the matching of the phases of reference signal F ref and output signal F o . Once this condition is detected, the lock circuit 12 provides the output signal Q 3 to the current range control circuit 17 to remain at the present bias current level, the optimal bias current I bias (shown in FIG. 4A) to be output to the plurality of delay cells 20 a . . . 20 n .
- This lock circuit 12 provides fast signal lock detection so that devices using the DLL 10 output signal F o do not have to delay processing for a longer period of time than necessary, resulting in faster device processing time.
- the error signals U, D from the PFD 11 are also forwarded to the charge pump 13 .
- the charge pump 13 outputs a charge current that charges or discharges the capacitor C 1 of the loop filter 15 to a voltage level V lpf .
- the charge pump 13 receives the error signals U, D, a bias voltage input V bp from the common bias generator 16 , and the logic signals S 1 , S 2 , S 3 from the charge pump control circuit 14 , as will be described in greater detail hereinafter.
- V bp is a reference bias voltage which controls the charge pump 13 output current.
- V lpf is a reference for the common bias generator 16 and the current range control circuit 17 to generate the reference signals which control the amount of delay generated by each delay element 20 a . . . . 20 n .
- the logic signals S 1 , S 2 , S 3 received by the charge pump 13 from the charge pump control circuit 14 are equivalent to 1, 1, 1, respectively. This output allows the charge pump 13 to output a maximum charge current, causing the DLL 10 to have a high frequency response to the error signals U, D.
- the charge pump control circuit 14 receives a logic one (1) signal from H-F ref , which detects the existence of this high frequency reference signal.
- the charge pump control circuit 14 converts a charge control signal CC signal and adjusts the outputs of the three logic signals S 1 , S 2 , S 3 , which in turn adjusts the amount of charge current output by the charge pump 13 .
- the signals S 1 , S 2 , S 3 output from the charge pump control circuit 14 may be equivalent to 1, 1, 0 or 1, 0, 1, respectively, for example.
- the charge control signal CC signal is an outside input signal whose value depends on the device or process for which the DLL 10 output F o is to be used.
- the charge pump control circuit 14 converts the charge control signal CC signal to the logic signals S 1 , S 2 , S 3 . This instructs the charge pump 13 to switch out an internal current source (not shown) when the logic signal S 1 , S 2 , or S 3 associated with the current source is zero (0), thereby dividing the current of the charge pump 13 by a number m (e.g., 3, 6, or 9).
- the use of the charge pump control circuit 14 when a high frequency input signal is detected provides a reduced frequency response to the error signals U, D as the phase of the output signal F o is adjusted to match the phase of the input signal F ref , providing better jitter performance.
- the loop filter 15 which comprises a capacitor C 1 , is coupled to the current range control circuit 17 , the common bias generator 16 , and the charge pump 13 .
- This loop filter 15 receives a charge current generated by the charge pump 13 and an outside input voltage V dd .
- a voltage V lpf is created and output to the current range control circuit 17 and the common bias generator 16 .
- the current range control circuit 17 coupled to the output of the loop filter 15 and the lock circuit 12 , the delay cell switching circuit 21 and the common bias generator 16 , comprises two voltage comparators (not shown) and two (2) single bit outputs R 0 , R 1 .
- the current range control circuit 17 receives the loop filter 15 output voltage V lpf and adjusts the level of the bias current I bias generated in the common bias generator 16 , through the output leads R 0 , R 1 .
- the voltage comparators in the current range control circuit 17 monitor the voltage V lpf against an internal reference voltage V ref which is indicative of the point where a small change in the voltage V lpf causes a large change in the bias current I bias .
- the reference voltage V ref which can be fixed or variable, is illustrated in the I bias I-V curves 60 - 66 of FIG. 5.
- each of these curves 60 - 66 include a nonlinear region where a small increase in the voltage creates a large decrease in the current. This nonlinear region creates a large change in the delay elements 20 a . . . 20 n , causing increased jitter within the DLL circuit 10 . If the DLL circuit 10 is operated past a certain voltage point V ref on the curves and into the nonlinear region, the amount of jitter will increase and the overall performance of the DLL circuit 10 will decrease.
- the PFD 11 , bias generator 16 and lock circuit 12 receive a local reset signal Cal_reset from the current range control circuit 17 which resets the voltage V lpf to zero (0).
- the current range control circuit 17 outputs R 0 , R 1 switch states, adjusting the bias current I bias to a lower level.
- the current range control circuit 17 receives a logic zero (0) signal from the lock circuit 12 and signals the bias generator 16 to switch on all four current sources I 1 , I 2 , I 3 , I 4 , which is indicated by the output 0, 0 for the two output leads R 0 , R 1 , respectively.
- the current range control circuit 17 also resets a delay cell signal DC at the input of a delay cell switching circuit 21 , which sets the number of delay cells to the lowest delay level.
- the current control circuit 17 When the lock circuit 12 detects the crossing of the phase of the reference and output signals F ref , F o , the current control circuit 17 is signaled to lock the common bias generator 16 at the present bias current level, which is the optimal bias current curve for the DLL circuit 10 performance. As disclosed above, when the voltage comparators in the current range control circuit 17 detect that the V lpf is too high, the current range control circuit 17 output leads R 0 , R 1 switch by one (1). For example, after the resetting of the DLL circuit 10 , the output leads R 0 , R 1 are equivalent to 0, 0.
- the output leads R 0 , R 1 switch to 0, 1, respectively, which indicates that the common bias generator 16 should switch off current source I 4 .
- the current range control circuit 17 also outputs an internal reset signal Cal_reset to the PFD 11 , the lock circuit 12 , and the bias generator 16 which resets the voltage V lpf to zero (0).
- the output leads R 0 , R 1 increase by one (1) and another current source (for example 13) is switched off. This process continues until the output leads R 0 , R 1 are equivalent to 1, 1, where the only remaining current source is I 1 .
- the current range control circuit 17 outputs a logic one (1) delay cell signal DC to the delay cell switching circuit 21 , indicating that the maximum number of delay cells 20 a . . . 20 n should be used.
- the reset signal Cal_reset is also output, thereby resetting the aforementioned components and the output leads R 0 , R 1 .
- the current range control circuit 17 again steps through the process described above. Once the current range control circuit 17 reaches the lowest bias current level for the second time, the common bias generator 16 is signaled to lock at the lowest bias current level I 1 .
- the current range control circuit 17 remains at the present bias current level, which is considered the optimal operating point for the process utilizing the DLL 10 output signal Fo.
- the current range control circuit 17 is illustrated utilizing two (2) single bit outputs R 0 , R 1 , a single two bit output may also be utilized. It should also be obvious to those skilled in the art that even though the current invention only utilizes four (4) bias current levels, the current range control circuit 17 can be designed to provide for more or less levels of current control.
- the delay cell 20 a . . . 20 n with a single differential amplifier representing a single differential delay element is shown.
- the number of delay cells 20 a . . . 20 n utilized by the DLL 10 is determined by the delay cell switching circuit 21 .
- the current range control circuit 17 sends a logic zero (0) delay cell signal DC to the delay cell switching circuit 21 , resetting it to the lowest delay cell count.
- the lowest delay cell count is six (6).
- the delay cell switching circuit 21 increases the number of delay cells used by the DLL 10 to its maximum count; which for purposes of the present invention is twenty 20 delay cells.
- the minimum and maximum delay cell counts may be changed depending on the device and process. Additionally, even though the present invention has only two levels of delay cell counts, minimum and maximum, the switching circuit 21 may provide for more levels.
- each of the delay elements 20 a . . . 20 n draw transient power
- the reduced delay cell count allows the DLL 10 to consume less power because fewer delay cells are used.
- the delay cell switching circuit 21 coupled to the current range control circuit 17 provides the DLL circuit 10 with more flexibility and faster locking times.
- the present invention utilizes a single common bias generator 16 , comprising a bias current generator 56 , a bias voltage generator 58 and a differential amplifier 54 .
- the differential amplifier 54 reduces the noise from the power supply.
- the differential amplifier provides improved power supply rejection ratio performance.
- the bias current generator 56 includes four symmetric loads 70 , 72 , 74 , 76 and a switching circuit 57 .
- Each of the symmetric loads 70 , 72 , 74 , 76 which may or may not have the same device width, has as its voltage source V dd and the low pass filter output signal V lpf as its control voltage.
- the four symmetric loads 70 , 72 , 74 , 76 act as current sources I 1 , I 2 , I 3 , I 4 . These current sources I 1 , I 2 , I 3 , I 4 are switched on and off by the switching circuit 57 .
- the outputs R 0 , R 1 from the current range control circuit 17 dictate to the switching circuit 57 which of the current sources should be on and which should be off.
- the bias current I bias is output from the bias current generator 56 to the bias voltage generator 58 .
- the bias voltage generator 58 comprises two n channel transistors 51 , 52 and one p channel transistor 53 .
- the gate voltage of the n channel transistors 51 , 52 is connected to the output of the differential amplifier 54 .
- This differential amplifier 54 works to eliminate the noise generated by power supply voltage V dd .
- the n channel transistors 51 , 52 are configured such that the bias current I bias through transistor 51 is mirrored onto transistor 52 and reflected up to transistor 53 . When the bias current I bias is mirrored in this way, two reference voltages are created.
- the two reference voltages are the bias voltages V bn and V bp , which determine the amount of delay for each delay element 20 a . . . 20 n .
- This configuration also provides the bias current I bias from the common bias generator 16 to each delay element 20 a . . . 20 n .
- This common bias generator 16 and a selectable number of delay cells 20 a . . . 20 n will provide better linearity in the overall delay of the DLL circuit 10 .
- each delay cell 20 a . . . 20 n contains two p channel transistors 21 and 22 and three n channel transistors 23 , 24 , 25 .
- Transistors 23 , 24 act as switches in the delay cell 20 a and determine the actual delay for each element based on the bias current I bias via the voltages V bn and V bp .
- the p channel transistors 21 , 22 act as current sources for the transistors 23 , 24 .
- Transistor 25 acts as a current source as well.
- the p channel transistors 21 , 22 are biased by the voltage V bp . Since the amount of bias current I bias determines the voltage V bp , the delay time changes with V bp .
- Transistors 23 and 24 receive a voltage input V + , and V ⁇ .
- the delay elements 20 a . . . 20 n are configured in such a way that the voltage inputs V + , V ⁇ of the delay elements come from the voltage outputs V o + , V o ⁇ of the preceding delay elements.
- the voltage outputs V o + , V o ⁇ from the last delay element 20 n are coupled to a differential amplifier 22 .
- transistor 22 does not pass through transistor 24 when transistor 24 is “off” (or not conducting).
- transistor 23 when transistor 23 is not conducting, the current provided by transistor 21 does not pass through transistor 23 .
- transistors 23 and 24 are on and off, respectively, the charge on the parasitic capacitors at the input of transistors 23 and 24 on the subsequent delay cell will be affected.
- transistor 23 is turned on, it discharges the parasitic capacitances of the next delay cell and V o ⁇ changes from (V dd ⁇ V ds 21 ) to (0V+V ds 23 +V ds 25 ).
- transistor 22 charges the capacitance of the following delay cell and V o + changes from (0V+V ds 24 +V ds 25 ) to (V dd ⁇ V ds 22 ), the drain to source voltage of transistor 22 at saturation.
- the delay provided by the delay cell is equivalent to the duration between turning on transistor 23 and turning off transistor 24 , and when the voltages V + and V ⁇ are equal.
- V o + and V o ⁇ are the output voltages of each delay cell that provide the input voltages V + , V ⁇ to the next delay cell.
- the DLL circuit 10 receives a reset signal DLL reset from an external source and resets all DLL 10 circuit components (step 700 ). If the reference signal is a high frequency reference signal, the H-F ref signal goes high, activating the charge pump control circuit 14 . The charge pump control circuit 14 then outputs logic signals S 1 , S 2 , S 3 to the charge pump 13 to adjust the current in the charge pump 13 , in accordance with the charge control signal CC signal (step 700 a ). The PFD 11 resets the error signals U, D (step 701 ).
- the current range control circuit 17 receives the reset signal DLL reset from the outside source and sets the bias current level of the common bias generator 16 to the maximum (I 1 +I 2 +I 3 +I 4 ) and sets the delay cell count to its minimum (step 701 a ).
- the charge pump 13 outputs the appropriate charge current (step 703 ), generating a DLL circuit 10 delayed output signal F o .
- the delayed output signal F o is then output to the PFD 11 to be compared to the reference signal F ref (step 704 ). If F o is in phase with F ref the lock circuit 12 signals the current range control circuit 17 to lock at the present current level (step 705 ). Once the bias current level I bias is locked, the DLL circuit 10 is in lock range position (step 706 ) and the procedure terminates.
- the PFD 11 If the two signals F ref , F o are out of phase, the PFD 11 outputs the error signals U, D, whose duration depend on the amount of phase error that is detected between the two signals F ref , F o (step 707 ).
- the charge pump 13 receives the error signals U, D from the PFD 11 and the logic signals S 1 , S 2 , S 3 from the charge pump control circuit 14 and outputs a current, commensurate with those signals, which sources or sinks the loop filter 15 capacitor C 1 (step 708 ).
- the control voltage V lpf is generated (step 709 ).
- the current range control circuit 17 If the loop filter 15 voltage V lpf is greater than V ref and the current range control circuit 17 is not in the minimum range with the delay cell signal DC equal to one (1), the current range control circuit 17 outputs a local reset signal Cal_reset, which resets the voltage V lpf to zero (0) (step 709 a ). The current range control circuit 17 outputs R 0 , R 1 then switch to the next lowest level (step 709 b ).
- the common bias generator 16 outputs the bias current I bias and bias voltages V bp , V bn to the plurality of delay cells 20 a . . . 20 n (step 711 ), which generates the DLL circuit 10 output signal F o (step 704 ).
- This design of the DLL circuit 10 in accordance with the preferred embodiment, will achieve a wide operating frequency range with a short lock in time and good jitter performance over a wide power supply voltage range.
- the differential DLL operating in the biasing current mode, provides a much wider operating frequency range with high common-mode noise immunity.
- the common biasing technique provides the necessary bias with less sensitivity to temperature and process variations. It also provides better power supply rejection ratio and current range calibration regulation when the power supply droops or when process variations change.
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Abstract
Description
- The present invention relates generally to delay locked loop (DLL) circuits. More particularly, this invention relates to a DLL circuit which is based on a variable length plurality of differential delay elements, an advanced common biasing technique which tolerates process variations and calibrates current range for operational variances and lock detection for faster processing.
- Delay-locked loops are often used in the I/O interfaces of digital integrated circuits in order to hide clock distribution delays and to improve overall system timing. In recent years, the demand has risen for devices capable of high-speed processing. As a result, the demand for DLL circuits that quickly compensate for electronic noise and capacitive delays has also risen.
- One type of design used by those skilled in the art to minimize the noise present in the circuit at the required speed is a self-bias signal technique. Referring to FIG. 1, this prior art DLL circuit is a self-biasing configuration which is composed of a phase comparator, charge pump, loop filter, bias generator and a plurality of delay cells. In this configuration, devices dependent on a precisely delayed clock signal must delay processing for a standardized time period to insure that the received signal is exact. This processing delay is caused by the fact that most DLL circuits are designed to tolerate the worst case conditions. The DLL circuit performance during this worst case condition is the processing delay time set for most devices using the output of this circuit.
- This prior art design uses a constant charge pump current which gives rise to a constant damping factor and a constant loop bandwidth. A constant bandwidth can constrain the achievement of a wide operating frequency range and low input tracking jitter. If the frequency is disturbed, the phase error that results from each cycle of the disturbance will accumulate for many cycles until the loop can compensate for the phase error. The error will be accumulated for a number of cycles, which is proportional to the operating frequency divided by the loop bandwidth. Thus the loop bandwidth would have to be positioned as close as possible to the reference frequency bandwidth to minimize the total phase error. The result is that the frequency bandwidth must be conservatively set for stability at the lowest operating frequency with worst case process variations rather than set for optimized jitter performance. The self-biased DLL also exhibits much faster locking times only when locking from similar or higher operating frequencies. However, if the self-biased DLL is started at a very low operating frequency, it will exhibit very slow locking times.
- Accordingly, there is a need for a DLL circuit which provides a fast lock-up circuit, has better jitter performance, tolerates process variations, reduces power consumption, reduces processing delay time and extends the DLL operating frequency range.
- The present invention is a DLL circuit which is based on a common bias technique, comprising a plurality of differential delay elements, a fast lock-up circuit and a self-calibration current range setting circuit. This design provides improved speed in detecting and locking to an incoming signal. The invention also extends the DLL operating range, improves DLL jitter performance, provides greater immunity to environmental noise, and improves the power supply rejection ratio (PSRR).
- FIG. 1 is a block diagram of a typical DLL circuit;
- FIG. 2 is a block diagram of the circuit in accordance with the preferred embodiment of the present invention;
- FIG. 3A is a logic gate diagram of the lock circuit in accordance with the preferred embodiment of the present invention;
- FIG. 3B is a state diagram of the lock circuit inputs in accordance with the preferred embodiment of the present invention;
- FIG. 3C is a logic table for the lock circuit in accordance with the preferred embodiment of the present invention;
- FIG. 4A is a diagram of the bias generator and a delay element in accordance with the preferred embodiment of the present invention;
- FIG. 4B is a diagram of a representation of the configuration of the delay elements with the switching circuit.
- FIG. 5 is an example of a graph of four I-V curves in accordance with the preferred embodiment of the present invention; and
- FIG. 6 is a flow diagram in accordance with the preferred embodiment of the present invention.
- The first embodiment of the present invention will be described with reference to the drawing figures wherein like numerals represent like elements throughout.
- Referring to FIG. 2, a
DLL circuit 10 made in accordance with the present invention is shown. TheDLL circuit 10 includes a phase frequency detector (PFD) 11, alock circuit 12, acharge pump 13, a chargepump control circuit 14, aloop filter 15 including a capacator C1 (not shown), acommon bias generator 16, a currentrange control circuit 17, a delaycell switching circuit 21 and a plurality of delay cells 20 a . . . 20 n. ThePFD 11 receives a reference signal Fref from an outside source, a reset signal DLLreset and the DLL output signal Fo. Coupled to thePFD 11 are thelock circuit 12 and thecharge pump 13. As those skilled in the art should know, thePFD 11 determines the phase difference between the reference signal Fref and theDLL 10 output signal Fo. If thePFD 11 detects a phase difference between the two input signals Fref, Fo, the phase error signals U, D are sent to thelock circuit 12 and thecharge pump 13. The duration (pulse width) of these output signals U, D depends on the amount of phase error that is detected by thePFD 11. - The
lock circuit 12, shown in FIG. 3A, is controlled by the phase error signals U, D output from thePFD 11. Coupled to thePFD 11 and the currentrange control circuit 17, thelock circuit 12 monitors the crossing of the phase of the DLL output signal Fo and the phase of the reference signal Fref, as will be disclosed hereinafter. Thelock circuit 12 comprises a plurality of invertors 3, a plurality ofAND gates 5, two S-R flip flops 7 and adelay 9. When thelock circuit 12 detects the crossing of the phase of the two signals Fo, Fref, thelock circuit 12 provides an output Q3 to the currentrange control circuit 17 to remain at the present bias current level. The output Q3 of thelock circuit 12, as theDLL circuit 10 attempts to match the phase of the output signal Fo with the phase of the reference signal Fref, is illustrated in the logic table of FIG. 3C. - Referring to FIGS. 3B and 3C, as the
DLL circuit 10 comes out of reset, the error signals U, D are in theneutral state state loop filter 15 capacitor C1 must be charged. On the subsequent rising edge of the reference frequency Fref, the error signals U, D go to astate PFD 11 to reset and return the error signals U, D to theirneutral state state lock circuit 12 to output a logical one (1) to the currentrange control circuit 17, indicating that the currentrange control circuit 17 should maintain the bias current at the present level which will be described in greater detail hereinafter. - The
lock circuit 12 operates to quickly detect the matching of the phases of reference signal Fref and output signal Fo. Once this condition is detected, thelock circuit 12 provides the output signal Q3 to the currentrange control circuit 17 to remain at the present bias current level, the optimal bias current Ibias (shown in FIG. 4A) to be output to the plurality ofdelay cells 20 a . . . 20 n. Thislock circuit 12 provides fast signal lock detection so that devices using theDLL 10 output signal Fo do not have to delay processing for a longer period of time than necessary, resulting in faster device processing time. - Referring back to FIG. 2, the error signals U, D from the
PFD 11 are also forwarded to thecharge pump 13. Thecharge pump 13 outputs a charge current that charges or discharges the capacitor C1 of theloop filter 15 to a voltage level Vlpf. Thecharge pump 13 receives the error signals U, D, a bias voltage input Vbp from thecommon bias generator 16, and the logic signals S1, S2, S3 from the chargepump control circuit 14, as will be described in greater detail hereinafter. Vbp is a reference bias voltage which controls thecharge pump 13 output current. It is well known to those skilled in the art that the charging and discharging of theloop filter 15 capacitor C1 creates a voltage change Vlpf across theloop filter 15. As the voltage Vlpf increases, thecharge pump 13 output current decreases. This voltage change Vlpf is a reference for thecommon bias generator 16 and the currentrange control circuit 17 to generate the reference signals which control the amount of delay generated by eachdelay element 20 a . . . . 20 n. - The logic signals S1, S2, S3 received by the
charge pump 13 from the chargepump control circuit 14 are equivalent to 1, 1, 1, respectively. This output allows thecharge pump 13 to output a maximum charge current, causing theDLL 10 to have a high frequency response to the error signals U, D. However, when theDLL circuit 10 receives a high frequency reference signal, such as greater than 300 MHz, the chargepump control circuit 14 receives a logic one (1) signal from H-Fref, which detects the existence of this high frequency reference signal. The chargepump control circuit 14 converts a charge control signal CCsignal and adjusts the outputs of the three logic signals S1, S2, S3, which in turn adjusts the amount of charge current output by thecharge pump 13. When H-Fref equals logic one (1), the signals S1, S2, S3 output from the chargepump control circuit 14 may be equivalent to 1, 1, 0 or 1, 0, 1, respectively, for example. The charge control signal CCsignal is an outside input signal whose value depends on the device or process for which theDLL 10 output Fo is to be used. The chargepump control circuit 14 converts the charge control signal CCsignal to the logic signals S1, S2, S3. This instructs thecharge pump 13 to switch out an internal current source (not shown) when the logic signal S1, S2, or S3 associated with the current source is zero (0), thereby dividing the current of thecharge pump 13 by a number m (e.g., 3, 6, or 9). The use of the chargepump control circuit 14 when a high frequency input signal is detected provides a reduced frequency response to the error signals U, D as the phase of the output signal Fo is adjusted to match the phase of the input signal Fref, providing better jitter performance. - The
loop filter 15, which comprises a capacitor C1, is coupled to the currentrange control circuit 17, thecommon bias generator 16, and thecharge pump 13. Thisloop filter 15 receives a charge current generated by thecharge pump 13 and an outside input voltage Vdd. As a result of the charging or discharging of the capacitor C1, a voltage Vlpf is created and output to the currentrange control circuit 17 and thecommon bias generator 16. - The current
range control circuit 17, coupled to the output of theloop filter 15 and thelock circuit 12, the delaycell switching circuit 21 and thecommon bias generator 16, comprises two voltage comparators (not shown) and two (2) single bit outputs R0, R1. The currentrange control circuit 17 receives theloop filter 15 output voltage Vlpf and adjusts the level of the bias current Ibias generated in thecommon bias generator 16, through the output leads R0, R1. The voltage comparators in the currentrange control circuit 17 monitor the voltage Vlpf against an internal reference voltage Vref which is indicative of the point where a small change in the voltage Vlpf causes a large change in the bias current Ibias. The reference voltage Vref, which can be fixed or variable, is illustrated in the Ibias I-V curves 60-66 of FIG. 5. As those skilled in the art should know, each of these curves 60-66 include a nonlinear region where a small increase in the voltage creates a large decrease in the current. This nonlinear region creates a large change in thedelay elements 20 a . . . 20 n, causing increased jitter within theDLL circuit 10. If theDLL circuit 10 is operated past a certain voltage point Vref on the curves and into the nonlinear region, the amount of jitter will increase and the overall performance of theDLL circuit 10 will decrease. Therefore, when the voltage Vlpf is greater than the reference voltage Vref, thePFD 11,bias generator 16 andlock circuit 12 receive a local reset signal Cal_reset from the currentrange control circuit 17 which resets the voltage Vlpf to zero (0). The currentrange control circuit 17 outputs R0, R1 switch states, adjusting the bias current Ibias to a lower level. - Initially, when the
DLL circuit 10 is reset, the currentrange control circuit 17 receives a logic zero (0) signal from thelock circuit 12 and signals thebias generator 16 to switch on all four current sources I1, I2, I3, I4, which is indicated by theoutput range control circuit 17 also resets a delay cell signal DC at the input of a delaycell switching circuit 21, which sets the number of delay cells to the lowest delay level. When thelock circuit 12 detects the crossing of the phase of the reference and output signals Fref, Fo, thecurrent control circuit 17 is signaled to lock thecommon bias generator 16 at the present bias current level, which is the optimal bias current curve for theDLL circuit 10 performance. As disclosed above, when the voltage comparators in the currentrange control circuit 17 detect that the Vlpf is too high, the currentrange control circuit 17 output leads R0, R1 switch by one (1). For example, after the resetting of theDLL circuit 10, the output leads R0, R1 are equivalent to 0, 0. When the comparator detects the high voltage Vlpf, the output leads R0, R1 switch to 0, 1, respectively, which indicates that thecommon bias generator 16 should switch off current source I4. The currentrange control circuit 17 also outputs an internal reset signal Cal_reset to thePFD 11, thelock circuit 12, and thebias generator 16 which resets the voltage Vlpf to zero (0). Each time the voltage comparators of the currentrange control circuit 17 detect this condition, the output leads R0, R1 increase by one (1) and another current source (for example 13) is switched off. This process continues until the output leads R0, R1 are equivalent to 1, 1, where the only remaining current source is I1. At this point, the currentrange control circuit 17 outputs a logic one (1) delay cell signal DC to the delaycell switching circuit 21, indicating that the maximum number ofdelay cells 20 a . . . 20 n should be used. The reset signal Cal_reset is also output, thereby resetting the aforementioned components and the output leads R0, R1. The currentrange control circuit 17 again steps through the process described above. Once the currentrange control circuit 17 reaches the lowest bias current level for the second time, thecommon bias generator 16 is signaled to lock at the lowest bias current level I1. - If the reference voltage Vref is greater than the
loop filter 15 voltage Vlpf and the lock circuit output is a logic one (1), the currentrange control circuit 17 remains at the present bias current level, which is considered the optimal operating point for the process utilizing theDLL 10 output signal Fo. As those skilled in the art should know, even though the currentrange control circuit 17 is illustrated utilizing two (2) single bit outputs R0, R1, a single two bit output may also be utilized. It should also be obvious to those skilled in the art that even though the current invention only utilizes four (4) bias current levels, the currentrange control circuit 17 can be designed to provide for more or less levels of current control. - Referring to FIG. 4B, the
delay cell 20 a . . . 20 n, with a single differential amplifier representing a single differential delay element is shown. The number ofdelay cells 20 a . . . 20 n utilized by theDLL 10 is determined by the delaycell switching circuit 21. When theDLL 10 is reset, the currentrange control circuit 17 sends a logic zero (0) delay cell signal DC to the delaycell switching circuit 21, resetting it to the lowest delay cell count. For purposes of the preferred embodiment of the present invention, the lowest delay cell count is six (6). When thecontrol circuit 17 sends a logic one (1) delay cell signal DC, the delaycell switching circuit 21 increases the number of delay cells used by theDLL 10 to its maximum count; which for purposes of the present invention is twenty 20 delay cells. The minimum and maximum delay cell counts may be changed depending on the device and process. Additionally, even though the present invention has only two levels of delay cell counts, minimum and maximum, the switchingcircuit 21 may provide for more levels. - Since each of the
delay elements 20 a . . . 20 n draw transient power, the reduced delay cell count allows theDLL 10 to consume less power because fewer delay cells are used. The delaycell switching circuit 21 coupled to the currentrange control circuit 17 provides theDLL circuit 10 with more flexibility and faster locking times. - Referring to FIG. 4A, the present invention utilizes a single
common bias generator 16, comprising a bias current generator 56, abias voltage generator 58 and a differential amplifier 54. The differential amplifier 54 reduces the noise from the power supply. The differential amplifier provides improved power supply rejection ratio performance. The bias current generator 56 includes foursymmetric loads switching circuit 57. Each of thesymmetric loads symmetric loads circuit 57. The outputs R0, R1 from the currentrange control circuit 17 dictate to the switchingcircuit 57 which of the current sources should be on and which should be off. As should be known to those skilled in the art, there are numerous switching circuits which are responsive to a digital input and can be used as described herein. In this manner, the currentrange control circuit 17 provides four discrete levels of bias current Ibias. This allows for better control of theDLL circuit 10 by providing the flexibility of varying the current slope without having to vary the delay cell itself. The bias current Ibias is output from the bias current generator 56 to thebias voltage generator 58. - The
bias voltage generator 58 comprises two n channel transistors 51, 52 and one p channel transistor 53. The gate voltage of the n channel transistors 51, 52 is connected to the output of the differential amplifier 54. This differential amplifier 54 works to eliminate the noise generated by power supply voltage Vdd. The n channel transistors 51, 52 are configured such that the bias current Ibias through transistor 51 is mirrored onto transistor 52 and reflected up to transistor 53. When the bias current Ibias is mirrored in this way, two reference voltages are created. The two reference voltages are the bias voltages Vbn and Vbp, which determine the amount of delay for eachdelay element 20 a . . . 20 n. This configuration also provides the bias current Ibias from thecommon bias generator 16 to eachdelay element 20 a . . . 20 n. Using thiscommon bias generator 16 and a selectable number ofdelay cells 20 a . . . 20 n will provide better linearity in the overall delay of theDLL circuit 10. - Referring still to FIG. 4A, each
delay cell 20 a . . . 20 n contains twop channel transistors delay cell 20 a and determine the actual delay for each element based on the bias current Ibias via the voltages Vbn and Vbp. Thep channel transistors p channel transistors delay elements 20 a . . . 20 n are configured in such a way that the voltage inputs V+, V− of the delay elements come from the voltage outputs Vo +, Vo − of the preceding delay elements. The voltage outputs Vo +, Vo − from thelast delay element 20 n are coupled to adifferential amplifier 22. - The current supplied by
transistor 22 does not pass through transistor 24 when transistor 24 is “off” (or not conducting). Likewise, when transistor 23 is not conducting, the current provided bytransistor 21 does not pass through transistor 23. There are parasitic capacitances at the inputs of transistors 23 and 24 that charge and discharge to affect the voltages V+ and V−, which rise and fall. When transistors 23 and 24 are on and off, respectively, the charge on the parasitic capacitors at the input of transistors 23 and 24 on the subsequent delay cell will be affected. When transistor 23 is turned on, it discharges the parasitic capacitances of the next delay cell and Vo − changes from (Vdd−Vds 21) to (0V+Vds 23+Vds 25). Likewise, when transistor 24 is off,transistor 22 charges the capacitance of the following delay cell and Vo + changes from (0V+Vds 24+Vds 25) to (Vdd−Vds 22), the drain to source voltage oftransistor 22 at saturation. As is well known to those skilled in the art, the delay provided by the delay cell is equivalent to the duration between turning on transistor 23 and turning off transistor 24, and when the voltages V+ and V− are equal. When this point is reached, the transistors in the next delay cell are activated. Vo + and Vo − are the output voltages of each delay cell that provide the input voltages V+, V− to the next delay cell. - The flow diagram in accordance with present invention is illustrated in FIG. 6. The
DLL circuit 10 receives a reset signal DLLreset from an external source and resets allDLL 10 circuit components (step 700). If the reference signal is a high frequency reference signal, the H-Fref signal goes high, activating the chargepump control circuit 14. The chargepump control circuit 14 then outputs logic signals S1, S2, S3 to thecharge pump 13 to adjust the current in thecharge pump 13, in accordance with the charge control signal CCsignal (step 700 a). ThePFD 11 resets the error signals U, D (step 701). The currentrange control circuit 17 receives the reset signal DLLreset from the outside source and sets the bias current level of thecommon bias generator 16 to the maximum (I1+I2+I3+I4) and sets the delay cell count to its minimum (step 701 a). Thecharge pump 13 outputs the appropriate charge current (step 703), generating aDLL circuit 10 delayed output signal Fo. The delayed output signal Fo is then output to thePFD 11 to be compared to the reference signal Fref (step 704). If Fo is in phase with Fref thelock circuit 12 signals the currentrange control circuit 17 to lock at the present current level (step 705). Once the bias current level Ibias is locked, theDLL circuit 10 is in lock range position (step 706) and the procedure terminates. - If the two signals Fref, Fo are out of phase, the
PFD 11 outputs the error signals U, D, whose duration depend on the amount of phase error that is detected between the two signals Fref, Fo (step 707). Thecharge pump 13 receives the error signals U, D from thePFD 11 and the logic signals S1, S2, S3 from the chargepump control circuit 14 and outputs a current, commensurate with those signals, which sources or sinks theloop filter 15 capacitor C1 (step 708). As a result of the charging or discharging of theloop filter 15 capacitor C1, the control voltage Vlpf is generated (step 709). If theloop filter 15 voltage Vlpf is greater than Vref and the currentrange control circuit 17 is not in the minimum range with the delay cell signal DC equal to one (1), the currentrange control circuit 17 outputs a local reset signal Cal_reset, which resets the voltage Vlpf to zero (0) (step 709 a). The currentrange control circuit 17 outputs R0, R1 then switch to the next lowest level (step 709 b). - If the current
range control circuit 17 is at the minimum current level (i.e., R0, R1 is equal to 1,1) and the delay cell signal DC is equal to one (1), thecommon bias generator 16 outputs the bias current Ibias and bias voltages Vbp, Vbn to the plurality ofdelay cells 20 a . . . 20 n (step 711), which generates theDLL circuit 10 output signal Fo (step 704). - If the delay cell signal is equal to zero (0) when the current
range control circuit 17 is at the minimum current level (i.e., R0, R1 is equal to 1,1), the currentrange control circuit 17 signals the switchingcircuit 21 to use the maximum number of delay cells (step 712) (DC=1) and outputs the internal reset signal Cal_reset (712 a). When the delay cell signal DC switches from zero (0) to one (1), the process is started again (step 701). - This design of the
DLL circuit 10, in accordance with the preferred embodiment, will achieve a wide operating frequency range with a short lock in time and good jitter performance over a wide power supply voltage range. The differential DLL, operating in the biasing current mode, provides a much wider operating frequency range with high common-mode noise immunity. The common biasing technique provides the necessary bias with less sensitivity to temperature and process variations. It also provides better power supply rejection ratio and current range calibration regulation when the power supply droops or when process variations change. - While a specific embodiment of the present invention has been shown and described, many modifications and variations can be made by one skilled in the art without departing from the spirit and scope of the invention. The above description serves to illustrate and not limit the particular form in any way.
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US20030214280A1 (en) * | 2002-05-17 | 2003-11-20 | Gauthier Claude R. | Method and apparatus for calibrating a delay locked loop charge pump current |
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