US20020053928A1 - Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output - Google Patents
Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output Download PDFInfo
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- US20020053928A1 US20020053928A1 US09/939,191 US93919101A US2002053928A1 US 20020053928 A1 US20020053928 A1 US 20020053928A1 US 93919101 A US93919101 A US 93919101A US 2002053928 A1 US2002053928 A1 US 2002053928A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
- H03F3/45085—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45392—Indexing scheme relating to differential amplifiers the AAC comprising resistors in the source circuit of the AAC before the common source coupling
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45574—Indexing scheme relating to differential amplifiers the IC comprising four or more input leads connected to four or more AAC-transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45604—Indexing scheme relating to differential amplifiers the IC comprising a input shunting resistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45624—Indexing scheme relating to differential amplifiers the LC comprising balancing means, e.g. trimming means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45641—Indexing scheme relating to differential amplifiers the LC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
Definitions
- the present invention relates in general to communication systems and components, and is particularly directed to a transimpedance circuit, that is configured to transform a pair of differentially sensed input currents into a very precise, single ended output voltage.
- the transimpedance circuit provides a very high degree of common mode rejection, can operate in high or low D.C. voltage and current environments, and consumes very little power.
- the transimpedance circuit of the invention may be used to sense differential tip and ring currents of a subscriber line interface circuit.
- a wide variety of electronic circuit applications require the differential measurement of two (complementary) currents and some prescribed amount of rejection of their common mode components.
- the currents being measured exist in a high D.C. voltage and high D.C. current environment, yet their information content is ultimately to be employed in a low voltage and low current environment, with demanding requirements for accurate amplification and filtering, plus the additional requirement for low idle channel noise.
- various equipments employed by telecommunication service providers employ what are known as ISLIC's (subscriber line interface circuits), to interface (transmit and receive) telecommunication signals with respect to tip and ring leads of a wireline pair.
- the length of the wireline pair to which a SLIC is connected can be expected to vary from installation to installation, may have a very significant length (e.g., on the order of multiple miles), and transports both substantial DC voltages, as well as AC signals (e.g., voice and/or ringing), it has been difficult to realize a SLIC implementation that has ‘universal’ use in both legacy and state of the art installations.
- transimpedance circuits such as, but not limited to those intended for use in telecommunication service providers' wireline equipments (such as SLICs) that may be installed in a wide range of voltage and current environments, are effectively obviated by a new and improved, transimpedance circuit, that is capable of performing a very precise differential input current to single ended output voltage conversion, while enjoying a very high degree of common mode rejection, and reduced power dissipation, thereby making it particularly suited for remote site subscriber installations.
- SLICs telecommunication service providers' wireline equipments
- respective (tip and ring associated) current sense resistors may be installed in the closed loop, negative feedback paths of ‘tip’ and ‘ring’ path current sense amplifiers.
- the currents through the sense resistors may contain a desirable differential current component I DIFF and a common mode undesirable component I COM .
- the current sense amplifiers provide substantial performance in terms of gain and gain-bandwidth product, so that any voltage dropped across the sense resistors appear as a negligibly small component of the voltage between the tip and ring terminals of the SLIC.
- a voltage drop proportional to the current through each of the (tip/ring path) sense resistors is supplied as a differential control voltage to respective differential coupling circuits installed between associated bias current sources and the complementary polarity inputs of an operational amplifier, that provides the single ended output voltage.
- Each bias current source is coupled through an associated pair of bias resistors for the differential coupling circuits.
- the maximum current that can be sensed in each complementary (tip/ring) current flow path of the transimpedance circuit is limited by the product of a maximum bias current supplied by the respective (tip and ring path) bias current sources and the ratio of a pair of transistor emitter bias resistances to the resistance value of the (tip and ring path) sense resistors.
- the input terminals of the operational amplifier are coupled to a linearity compensator circuit, which is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions.
- the linearity compensator circuit has a differential amplifier configuration, coupled to close a negative feedback loop from the single ended output and one of the inputs to the operational amplifier, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input. This balanced coupling configuration forces the corresponding terminals of a pair of load resistors coupled to the input ports of the operational amplifier to the same potential, irrespective of variations in the sensed input currents.
- a first differential compensator portion of the linearity compensator includes a first ‘overhead voltage’ emitter-follower transistor having its collector-emitter path coupled in circuit with a first bias current source.
- This first overhead transistor has its base coupled to receive a reference voltage established by a voltage drop across a resistor coupled to receive a prescribed overhead bias current.
- the emitter output of the first overhead transistor provides base drive to a first emitter-follower configured compensator transistor pair, the current output of which is coupled through a first load resistor to the (+) input of the operational amplifier.
- a second compensator portion of the linearity compensator includes a second overhead voltage emitter-follower transistor having its collector-emitter path coupled in circuit with a second bias current source, and its base coupled through a feedback resistor to the single ended voltage output of the operational amplifier.
- the emitter output of the second overhead transistor provides base drive to a second emitter-follower configured compensator transistor pair, the current output of which is coupled through a second load resistor to the ( ⁇ ) input of the operational amplifier.
- FIG. 1 diagrammatically illustrates a transimpedance circuit in accordance with a non-limiting, but preferred embodiment of the present invention.
- FIG. 2 shows tip and ring path sense amplifiers containing sense resistors for the transimpedance circuit of FIG. 1.
- the transimpedance circuit of the invention will be described in terms of its use in a communication interface device, in particular, as a current-sense, voltage-feed transimpedance circuit for a subscriber line circuit or SLIC. It may be noted, however, that the invention is not limited to this application or type of signaling interface, but may be employed in a variety of signaling environments that contain or are coupled with complementary current paths. In the non-limiting SLIC-associated embodiment described here, the complementary current signal paths correspond to respective ‘tip’ and ‘ring’ paths of a wireline telecommunication circuit.
- a non-limiting, but preferred embodiment of a transimpedance circuit in accordance with the present invention is diagrammatically illustrated as comprising an operational amplifier 10 , having first (+) and second ( ⁇ ) complementary polarity, or differential, inputs 11 and 12 , and a single ended output 13 .
- the amplifier's (+) input 11 may be associated with the tip/ring path of a telecommunication signaling wireline pair, while the ( ⁇ ) input 12 may be associated with the wireline pair's ring/tip path.
- a first sense resistor 21 is coupled between a pair of input nodes IN 1 + and IN 1 ⁇ installed in the signaling path of interest, (e.g., the tip path of a telecommunication wireline pair), and current flow through which is denoted by a current Iin 1 .
- the current Iin 1 flowing through the first sense resistor 21 represents the first (here tip-associated) component of a summation of a desired differential current component (I DIFF ) that is to be transformed into an output voltage V OUT at the output 13 of the amplifier, plus an undesirable common mode or longitudinal current component I COM that is to be effectively rejected as a component in the output voltage produce at output 13 .
- the sense resistor 21 may comprise a relatively small valued resistor (having a resistance value denoted R SENSE1 , which may be on the order of several to several tens of ohms, for example), coupled between the output of a (tip) sense amplifier and its associated tip path output port of a low power receiver channel circuit of a subscriber line interface circuit for interfacing communication signals supplied from a device, such as a modem, with a wireline pair for delivery to a remote circuit, such as a subscriber's telephone.
- the sense resistor 21 may be installed in the closed loop, negative feedback path of a ‘tip’ path sense amplifier 23 , which has its ( ⁇ ) input coupled through an input resistor 24 to the IN 1 ⁇ node and its output coupled to the IN 1 + node.
- the current Iin 1 through the (tip) current sense resistor 21 provides a voltage drop proportional to the tip path current, and which is supplied as a differential control voltage to a first (tip path) differential coupling circuit 30 , that is coupled between a first current source 41 (which is shown reference to a power supply rail VEE) and the complementary polarity inputs 11 , 12 of the operational amplifier 10 .
- the differential coupling circuit 30 may comprise a differentially coupled pair of (NPN) bipolar transistors 50 and 60 .
- NPN differentially coupled pair of bipolar transistors 50 and 60 .
- bipolar components are shown, it is to be understood that the invention is not limited thereto, but also may be implemented using alternative equivalent circuit devices, such as field effect transistors (FETs), for example.
- the maximum current that can be sensed in each complementary (tip/ring) current flow path of the transimpedance circuit is limited by the product of the maximum bias current I DIFF supplied by the respective (tip and ring path) current sources 41 and 42 and the ratio of the value of one of the emitter bias resistances R DIFF to the resistance value R SENSE of the (tip and ring path) sense resistors 21 and 22 .
- the current supplied by the current source 41 is based upon the dynamic range needs of the transimpedance circuit, and as these requirements will vary depending upon the mode of operation of the SLIC, by configuring the current source 41 as a controllable device, power consumption can be minimized.
- the current source 41 For example, during the on-hook, quiescent mode (no circuit operation) of a subscriber's telephone, there is no need to draw any current; consequently during this mode, the output of the current source 41 can be reduced to zero, so that no power is consumed.
- on-hook reduced power signal monitoring such as for the case of a phone having caller-ID class of service, only a very reduced or minimal current is necessary, so that power consumption can be kept relatively small. It is not until the phone is placed in its off-hook voice signaling mode that the full dynamic range properties of the SLIC are required; in this mode the current output of the current source 41 would be controllably increased to its maximum value.
- Transistor 50 of the (tip side) differential coupling circuit 30 has its control terminal or base 51 coupled to the input node IN 1 ⁇ , and its collector 52 coupled to supply a first output voltage V DIFF1 ⁇ to the resistor 99 (having a value denoted R LOAD ⁇ ) coupled to the (+) input 11 of the operational amplifier 10 .
- the emitter bias and thereby the operation of transistor 50 is established by coupling the emitter 53 of transistor 50 through a bias resistor 54 (having a value denoted R DIFF1 ⁇ ) to the first current source 41 , which supplies a first reference current I DIFF1 .
- the current source 41 as a controllable device, the circuit's power consumption can be minimized.
- the other transistor 60 of the differentially coupled pair 50 / 60 has its control terminal/base 61 coupled to the input node IN 1 +, and its collector 62 coupled to supply a second output voltage V DIFF1+ to the resistor 119 (having a value denoted (R LOAD+ ) coupled to the ( ⁇ ) input 12 of operational amplifier 10 .
- the operation of transistor 60 is established by coupling its emitter 63 through bias resistor 64 (having a value denoted R DIFF1+ ) to the first current source 41 .
- a second ‘ring’ sense resistor 22 is coupled between input nodes IN 2 + and IN 2 ⁇ of a second or ring current sense path Iin 2 .
- the ring path sense resistor 22 comprises a relatively small valued resistor (having a resistance value denoted R SENSE2 ), which is very closely matched (within a small fraction of one percent) with the tip sense resistor 21 for the purpose of providing the desired degree of common mode rejection (longitudinal balance) required of a SLIC.
- R SENSE2 resistance value denoted resistance value denoted R SENSE2
- the ring path sense resistor 22 installed in the closed loop negative feedback path of a ‘ring’ side sense amplifier 26 , which has its ( ⁇ ) input coupled through an input resistor 28 to the IN 2 ⁇ node and its output coupled to the IN 2 + node.
- both the tip path sense amplifier 23 and the path ring sense amplifier 26 provide substantial performance in terms of gain and gain-bandwidth product. Therefore, with sense resistors 21 and 22 installed in closed loop paths of their associated tip and ring sense amplifiers 24 and 26 , any voltages dropped across these resistors will appear as a negligibly small component of the voltage between the tip and ring terminals of the SLIC.
- the second differential coupling circuit 35 may comprise a differentially coupled bipolar transistor pair of NPN transistors 55 and 65 .
- Transistor 55 has its base 56 coupled to the input node IN 2 ⁇ , and its collector 57 coupled to supply an output voltage V DIFF2 ⁇ to the (R LOAD ⁇ ) resistor 119 coupled to the (+) input 11 of the operational amplifier 10 .
- Emitter bias for transistor 55 is provided by coupling the emitter 58 through a bias resistor 59 (having a value denoted R DIFF2 ⁇ ) to the second current source 42 , also referenced to the voltage supply rail VEE, and supplying a second reference current I DIFF2 .
- transistor 65 has its control terminal/base 66 coupled to the input node IN 2 +, and its collector 67 coupled to supply an output voltage V DIFF2+ to the (R LOAD+ ) resistor 99 coupled the ( ⁇ ) input 12 of the operational amplifier 10 .
- the operation of the transistor 65 is established by biasing its emitter 68 through bias resistor 69 (having a value denoted R DIFF2+ ) to the second current source 42 .
- the input terminals 11 and 12 of the operational amplifier 10 are further coupled to a differentially configured, linearity compensator circuit 70 , which is coupled in circuit with voltage supply rails VEE and VCC, and is operative to provide sufficient overhead voltages in the presence of worst case voltage swing conditions.
- the linearity compensator circuit 70 has a differential amplifier configuration, which is coupled to close a negative feedback loop from output 13 to the inverting ( ⁇ ) input 12 of the operational amplifier 10 , relative to reference voltage balancing path coupled to the amplifier's non-inverting (+) input 11 .
- this balanced coupling configuration forces the bottom terminals of a pair of load resistors 99 and 119 of the linearity compensator circuit 70 , that are coupled to the input ports 11 and 12 of the operational amplifier 10 , to the same potential, irrespective of variations in the sensed input currents.
- a first (+) differential compensator portion of the linearity compensator 70 comprises a first (PNP) emitter-follower ‘overhead’ transistor 80 having its collector-emitter path coupled in circuit with a first bias current source 85 (referenced to the VCC voltage supply rail) and the supply rail VEE.
- the first bias current source 85 generates a bias current I BIAS1 .
- the first overhead transistor 80 has its control node or base 81 coupled to a reference voltage node 71 .
- the voltage at the reference voltage node 71 is established by a voltage drop across a resistor 75 (having a resistance value ROVHD1 ) relative to a voltage node, such as ground (AGND), as a result of a prescribed overhead current I OVDH1 therethrough as supplied by a current course 76 , referenced to the VCC supply rail.
- the emitter 83 of the first overhead transistor 80 is coupled to the base 91 of an emitter-follower NPN transistor 90 of an emitter-follower configured compensator (COMP ⁇ ) transistor pair 90 / 95 .
- the collector 92 of transistor 90 and the collector 97 of transistor 95 are coupled to the VCC supply rail.
- the emitter 98 of transistor 95 is coupled through the load resistor 99 to the (+) input 11 of the operational amplifier 10 .
- Each of the respective values of load resistors 99 and 119 (denoted R LOAD ⁇ and R LOAD+ ) is the same and may be denoted as R LOAD .
- a second ( ⁇ ) differential compensator portion of the linearity compensator 70 includes a second (PNP) emitter-follower ‘overhead’ transistor 100 having its base 101 coupled to a feedback voltage node 72 .
- Node 72 is coupled through a feedback resistor 77 (having a resistance value R OVHD2 ) to the output node 13 of the operational amplifier 10 .
- a reference current course 78 is coupled to supply an overhead current I OVDH2 to the node 72 and thereby to the feedback resistor 77 .
- Overhead transistor 100 has its emitter-collector current path coupled in circuit with bias current source 105 , referenced to the VCC voltage supply rail, and the supply rail VEE, and being operative to generate a second bias current I BIAS2 .
- the second overhead transistor 100 has its emitter 103 coupled to the base 111 of an emitter-follower NPN transistor 110 of an emitter-follower configured compensator (COMP+) transistor pair 110 / 115 .
- the emitter 113 of transistor 115 is coupled to the base 116 of transistor 110 .
- the collector 112 of transistor 110 and the collector 117 of transistor 115 are coupled to the VCC supply rail.
- the emitter 118 of emitter-follower transistor 115 is coupled through load resistor 119 to the ( ⁇ ) input 12 of operational amplifier 10 .
- the transimpedance circuit of FIG. 1 operates as follows.
- the complementary currents Iin 1 and Iin 2 that are assumed to be flowing in the directions shown through the respective first (tip) and second (ring) sense resistors 21 and 22 may be defined in equations (1) and (2) as:
- Iin 1 I DIFF +I COM (1).
- Iin 2 I DIFF ⁇ I COM (2).
- a load current I RLOAD ⁇ through the load resistor 99 of the (+) leg of linearity compensator 70 effectively corresponds to the sum of the differential currents I RDIFF1 ⁇ and I DIFF2 ⁇ through bias resistors 59 and 54 , respectively.
- ⁇ N is a proportionality constant which, for practical purposes is equal to 1.0 and therefore, will not be delineated in subsequent expressions.
- a load current I RLOAD+ through the ( ⁇ ) compensator leg load resistor 119 effectively corresponds to the sum of the differential currents I RDIFF1+ and I RDIFF2+ through the bias resistors 69 and 64 , respectively.
- V SENSE1 across the first (tip) sense resistor 21 may be expressed as:
- V SENSE2 across the second (ring) sense resistor 22 may be expressed as:
- Iin 1* R SENSE1 +Iin 2 *R SENSE2 ( I RDIFF1+ )*( R DIFF+ )+( I RDIFF2+ )*( R DIFF2+ ) ⁇ ( I RDIFF1 ⁇ )*( R DIFF1 ⁇ ) ⁇ ( I RDIFF2 ⁇ )*( R DIFF2 ⁇ ) ⁇ Vbe 55(DIFF2 ⁇ ) ⁇ Vbe 50(DIFF1 ⁇ ) +Vbe 65(DIFF2+) +Vbe 60(DIFF1+) (9).
- I DIFF2+ I DIFF1+ + ⁇ I 21+
- I DIFF2 ⁇ I DIFF1 ⁇ + ⁇ I 21 ⁇ .
- equation (20) reduces to:
- V OUT ⁇ V OHDem (21).
- the output voltage V OUT produced at the output terminal 13 of the operational amplifier 10 is relatively simply and linearly definable in terms of the sensed current I DIFF and the values of the sense resistors R SENSE .
- V OUT 2* I DIFF *R SENSE (22).
- Equation (22) implies that if either of the two sensed currents Iin 1 or Iin 2 is flowing in a direction opposite to that shown in FIG. 1 and both currents have the same value, the resulting voltage V OUT in equation (22) approaches zero. Namely, by optimizing the match between the resistance value R SENSE of the sense resistors 21 and 22 , and the match between the resistance values R DIFF of the bias resistors 54 , 59 , 64 , 69 , common mode output error is minimized.
Abstract
Description
- The present invention relates in general to communication systems and components, and is particularly directed to a transimpedance circuit, that is configured to transform a pair of differentially sensed input currents into a very precise, single ended output voltage. The transimpedance circuit provides a very high degree of common mode rejection, can operate in high or low D.C. voltage and current environments, and consumes very little power. As a non-limiting example, the transimpedance circuit of the invention may be used to sense differential tip and ring currents of a subscriber line interface circuit.
- A wide variety of electronic circuit applications require the differential measurement of two (complementary) currents and some prescribed amount of rejection of their common mode components. In some applications, the currents being measured exist in a high D.C. voltage and high D.C. current environment, yet their information content is ultimately to be employed in a low voltage and low current environment, with demanding requirements for accurate amplification and filtering, plus the additional requirement for low idle channel noise. As a non-limiting example, various equipments employed by telecommunication service providers employ what are known as ISLIC's (subscriber line interface circuits), to interface (transmit and receive) telecommunication signals with respect to tip and ring leads of a wireline pair. Since the length of the wireline pair to which a SLIC is connected can be expected to vary from installation to installation, may have a very significant length (e.g., on the order of multiple miles), and transports both substantial DC voltages, as well as AC signals (e.g., voice and/or ringing), it has been difficult to realize a SLIC implementation that has ‘universal’ use in both legacy and state of the art installations.
- In accordance with the present invention, shortcomings of conventional transimpedance circuits, such as, but not limited to those intended for use in telecommunication service providers' wireline equipments (such as SLICs) that may be installed in a wide range of voltage and current environments, are effectively obviated by a new and improved, transimpedance circuit, that is capable of performing a very precise differential input current to single ended output voltage conversion, while enjoying a very high degree of common mode rejection, and reduced power dissipation, thereby making it particularly suited for remote site subscriber installations.
- For a SLIC application, respective (tip and ring associated) current sense resistors may be installed in the closed loop, negative feedback paths of ‘tip’ and ‘ring’ path current sense amplifiers. The currents through the sense resistors may contain a desirable differential current component IDIFF and a common mode undesirable component ICOM. The current sense amplifiers provide substantial performance in terms of gain and gain-bandwidth product, so that any voltage dropped across the sense resistors appear as a negligibly small component of the voltage between the tip and ring terminals of the SLIC.
- A voltage drop proportional to the current through each of the (tip/ring path) sense resistors is supplied as a differential control voltage to respective differential coupling circuits installed between associated bias current sources and the complementary polarity inputs of an operational amplifier, that provides the single ended output voltage. Each bias current source is coupled through an associated pair of bias resistors for the differential coupling circuits. As will be described, the maximum current that can be sensed in each complementary (tip/ring) current flow path of the transimpedance circuit is limited by the product of a maximum bias current supplied by the respective (tip and ring path) bias current sources and the ratio of a pair of transistor emitter bias resistances to the resistance value of the (tip and ring path) sense resistors.
- In addition to differentially sensing the complementary (tip and ring) currents flowing through the sense resistors and their associated differential coupling circuits, the input terminals of the operational amplifier are coupled to a linearity compensator circuit, which is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. The linearity compensator circuit has a differential amplifier configuration, coupled to close a negative feedback loop from the single ended output and one of the inputs to the operational amplifier, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input. This balanced coupling configuration forces the corresponding terminals of a pair of load resistors coupled to the input ports of the operational amplifier to the same potential, irrespective of variations in the sensed input currents. For this purpose, a first differential compensator portion of the linearity compensator includes a first ‘overhead voltage’ emitter-follower transistor having its collector-emitter path coupled in circuit with a first bias current source. This first overhead transistor has its base coupled to receive a reference voltage established by a voltage drop across a resistor coupled to receive a prescribed overhead bias current. The emitter output of the first overhead transistor provides base drive to a first emitter-follower configured compensator transistor pair, the current output of which is coupled through a first load resistor to the (+) input of the operational amplifier.
- To close the negative feedback loop of the operational amplifier, a second compensator portion of the linearity compensator includes a second overhead voltage emitter-follower transistor having its collector-emitter path coupled in circuit with a second bias current source, and its base coupled through a feedback resistor to the single ended voltage output of the operational amplifier. The emitter output of the second overhead transistor provides base drive to a second emitter-follower configured compensator transistor pair, the current output of which is coupled through a second load resistor to the (−) input of the operational amplifier.
- By matching the bias resistors for the differential coupling circuits and the load resistors and parameters of the complementary sides of the differentially configured coupling and compensator circuits installed between the sense resistors and the operational amplifier, the single ended output voltage VOUT produced at the output of the operational amplifier is effectively linearly definable in terms of the sensed current IDIFF and the values RSENSE of the sense resistors, as VOUT=2*IDIFF*RSENSE. By optimizing the match between the resistance values of the sense resistors, and the match between the resistance values of the load resistors and the resistance values of the bias resistors common mode output error is minimized.
- FIG. 1 diagrammatically illustrates a transimpedance circuit in accordance with a non-limiting, but preferred embodiment of the present invention; and
- FIG. 2 shows tip and ring path sense amplifiers containing sense resistors for the transimpedance circuit of FIG. 1.
- As described briefly above, for purposes of providing a non-limiting practical example, the transimpedance circuit of the invention will be described in terms of its use in a communication interface device, in particular, as a current-sense, voltage-feed transimpedance circuit for a subscriber line circuit or SLIC. It may be noted, however, that the invention is not limited to this application or type of signaling interface, but may be employed in a variety of signaling environments that contain or are coupled with complementary current paths. In the non-limiting SLIC-associated embodiment described here, the complementary current signal paths correspond to respective ‘tip’ and ‘ring’ paths of a wireline telecommunication circuit.
- Referring now to FIG. 1, a non-limiting, but preferred embodiment of a transimpedance circuit in accordance with the present invention is diagrammatically illustrated as comprising an
operational amplifier 10, having first (+) and second (−) complementary polarity, or differential,inputs 11 and 12, and a single endedoutput 13. For the non-limiting application as a tip and ring current-sensing SLIC interface, the amplifier's (+) input 11 may be associated with the tip/ring path of a telecommunication signaling wireline pair, while the (−)input 12 may be associated with the wireline pair's ring/tip path. - In order to sense current flowing in one of the complementary signaling paths, a
first sense resistor 21 is coupled between a pair of input nodes IN1+ and IN1− installed in the signaling path of interest, (e.g., the tip path of a telecommunication wireline pair), and current flow through which is denoted by a current Iin1. As will be described, the current Iin1 flowing through thefirst sense resistor 21 represents the first (here tip-associated) component of a summation of a desired differential current component (IDIFF) that is to be transformed into an output voltage VOUT at theoutput 13 of the amplifier, plus an undesirable common mode or longitudinal current component ICOM that is to be effectively rejected as a component in the output voltage produce atoutput 13. - The
sense resistor 21 may comprise a relatively small valued resistor (having a resistance value denoted RSENSE1, which may be on the order of several to several tens of ohms, for example), coupled between the output of a (tip) sense amplifier and its associated tip path output port of a low power receiver channel circuit of a subscriber line interface circuit for interfacing communication signals supplied from a device, such as a modem, with a wireline pair for delivery to a remote circuit, such as a subscriber's telephone. For this purpose, as shown in the sensing block circuit diagram of FIG. 2, thesense resistor 21 may be installed in the closed loop, negative feedback path of a ‘tip’path sense amplifier 23, which has its (−) input coupled through aninput resistor 24 to the IN1− node and its output coupled to the IN1+ node. - The current Iin1 through the (tip)
current sense resistor 21 provides a voltage drop proportional to the tip path current, and which is supplied as a differential control voltage to a first (tip path)differential coupling circuit 30, that is coupled between a first current source 41 (which is shown reference to a power supply rail VEE) and thecomplementary polarity inputs 11, 12 of theoperational amplifier 10. In a non-limiting configuration, thedifferential coupling circuit 30 may comprise a differentially coupled pair of (NPN)bipolar transistors - The
current source 41 and an associated pair ofbias resistors differential coupling circuit 30, plus like components of a second (ring path-associated)differential coupling circuit 35, establish the dynamic range of the transimpedance circuit. As will be described, the maximum current that can be sensed in each complementary (tip/ring) current flow path of the transimpedance circuit is limited by the product of the maximum bias current IDIFF supplied by the respective (tip and ring path)current sources sense resistors - Since the current supplied by the
current source 41 is based upon the dynamic range needs of the transimpedance circuit, and as these requirements will vary depending upon the mode of operation of the SLIC, by configuring thecurrent source 41 as a controllable device, power consumption can be minimized. For example, during the on-hook, quiescent mode (no circuit operation) of a subscriber's telephone, there is no need to draw any current; consequently during this mode, the output of thecurrent source 41 can be reduced to zero, so that no power is consumed. For on-hook reduced power signal monitoring, such as for the case of a phone having caller-ID class of service, only a very reduced or minimal current is necessary, so that power consumption can be kept relatively small. It is not until the phone is placed in its off-hook voice signaling mode that the full dynamic range properties of the SLIC are required; in this mode the current output of thecurrent source 41 would be controllably increased to its maximum value. -
Transistor 50 of the (tip side)differential coupling circuit 30 has its control terminal orbase 51 coupled to the input node IN1−, and itscollector 52 coupled to supply a first output voltage VDIFF1− to the resistor 99 (having a value denoted RLOAD−) coupled to the (+) input 11 of theoperational amplifier 10. The emitter bias and thereby the operation oftransistor 50 is established by coupling theemitter 53 oftransistor 50 through a bias resistor 54 (having a value denoted RDIFF1−) to the firstcurrent source 41, which supplies a first reference current IDIFF1. As pointed out above, by configuring thecurrent source 41 as a controllable device, the circuit's power consumption can be minimized. - In like manner, the
other transistor 60 of the differentially coupledpair 50/60 has its control terminal/base 61 coupled to the input node IN1+, and itscollector 62 coupled to supply a second output voltage VDIFF1+ to the resistor 119 (having a value denoted (RLOAD+) coupled to the (−)input 12 ofoperational amplifier 10. Liketransistor 50, the operation oftransistor 60 is established by coupling itsemitter 63 through bias resistor 64 (having a value denoted RDIFF1+) to the firstcurrent source 41. - For the complementary signaling (ring) path, a second ‘ring’
sense resistor 22 is coupled between input nodes IN2+ and IN2− of a second or ring current sense path Iin2. Like the tippath sense resistor 21, the ringpath sense resistor 22 comprises a relatively small valued resistor (having a resistance value denoted RSENSE2), which is very closely matched (within a small fraction of one percent) with thetip sense resistor 21 for the purpose of providing the desired degree of common mode rejection (longitudinal balance) required of a SLIC. As shown in FIG. 2, the ringpath sense resistor 22 installed in the closed loop negative feedback path of a ‘ring’side sense amplifier 26, which has its (−) input coupled through aninput resistor 28 to the IN2− node and its output coupled to the IN2+ node. - Both the tip
path sense amplifier 23 and the pathring sense amplifier 26 provide substantial performance in terms of gain and gain-bandwidth product. Therefore, withsense resistors ring sense amplifiers - The voltage drop across the (ring)
current sense resistor 22 resulting from the current Iin2 flowing therethrough is applied as a differential control voltage to a seconddifferential coupling circuit 35, which is connected in circuit between the secondcurrent source 42 and thecomplementary polarity inputs 11, 12 of theoperational amplifier 10. As shown in FIG. 1, the direction of current flow of current Iin2 is assumed to be opposite to that of current Iin1. These currents contain a desirable differential current component IDIFF and an undesirable common mode current component ICOM to be rejected. - Like the first
differential coupling circuit 30, the seconddifferential coupling circuit 35 may comprise a differentially coupled bipolar transistor pair ofNPN transistors Transistor 55 has itsbase 56 coupled to the input node IN2−, and itscollector 57 coupled to supply an output voltage VDIFF2− to the (RLOAD−)resistor 119 coupled to the (+) input 11 of theoperational amplifier 10. Emitter bias fortransistor 55 is provided by coupling theemitter 58 through a bias resistor 59 (having a value denoted RDIFF2−) to the secondcurrent source 42, also referenced to the voltage supply rail VEE, and supplying a second reference current IDIFF2. In a like manner,transistor 65 has its control terminal/base 66 coupled to the input node IN2+, and itscollector 67 coupled to supply an output voltage VDIFF2+ to the (RLOAD+)resistor 99 coupled the (−)input 12 of theoperational amplifier 10. The operation of thetransistor 65 is established by biasing itsemitter 68 through bias resistor 69 (having a value denoted RDIFF2+) to the secondcurrent source 42. - In addition to differentially sensing the complementary (tip and ring) currents Iin1 and Iin2 flowing through the complementary current paths' sensing
resistors differential coupling circuits input terminals 11 and 12 of theoperational amplifier 10 are further coupled to a differentially configured,linearity compensator circuit 70, which is coupled in circuit with voltage supply rails VEE and VCC, and is operative to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. - The
linearity compensator circuit 70 has a differential amplifier configuration, which is coupled to close a negative feedback loop fromoutput 13 to the inverting (−)input 12 of theoperational amplifier 10, relative to reference voltage balancing path coupled to the amplifier's non-inverting (+) input 11. As will be described, this balanced coupling configuration forces the bottom terminals of a pair ofload resistors linearity compensator circuit 70, that are coupled to theinput ports 11 and 12 of theoperational amplifier 10, to the same potential, irrespective of variations in the sensed input currents. - For this purpose, a first (+) differential compensator portion of the
linearity compensator 70 comprises a first (PNP) emitter-follower ‘overhead’transistor 80 having its collector-emitter path coupled in circuit with a first bias current source 85 (referenced to the VCC voltage supply rail) and the supply rail VEE. The first biascurrent source 85 generates a bias current IBIAS1. The firstoverhead transistor 80 has its control node orbase 81 coupled to areference voltage node 71. The voltage at thereference voltage node 71 is established by a voltage drop across a resistor 75 (having a resistance value ROVHD1) relative to a voltage node, such as ground (AGND), as a result of a prescribed overhead current IOVDH1 therethrough as supplied by acurrent course 76, referenced to the VCC supply rail. - The
emitter 83 of the firstoverhead transistor 80 is coupled to thebase 91 of an emitter-follower NPN transistor 90 of an emitter-follower configured compensator (COMP−)transistor pair 90/95. Thecollector 92 oftransistor 90 and thecollector 97 oftransistor 95 are coupled to the VCC supply rail. Theemitter 98 oftransistor 95 is coupled through theload resistor 99 to the (+) input 11 of theoperational amplifier 10. Each of the respective values ofload resistors 99 and 119 (denoted RLOAD− and RLOAD+) is the same and may be denoted as RLOAD. - To close the negative feedback loop of the
operational amplifier 10, a second (−) differential compensator portion of thelinearity compensator 70 includes a second (PNP) emitter-follower ‘overhead’transistor 100 having itsbase 101 coupled to afeedback voltage node 72.Node 72 is coupled through a feedback resistor 77 (having a resistance value ROVHD2) to theoutput node 13 of theoperational amplifier 10. A referencecurrent course 78 is coupled to supply an overhead current IOVDH2 to thenode 72 and thereby to thefeedback resistor 77.Overhead transistor 100 has its emitter-collector current path coupled in circuit with biascurrent source 105, referenced to the VCC voltage supply rail, and the supply rail VEE, and being operative to generate a second bias current IBIAS2. - The second
overhead transistor 100 has itsemitter 103 coupled to thebase 111 of an emitter-follower NPN transistor 110 of an emitter-follower configured compensator (COMP+)transistor pair 110/115. Theemitter 113 oftransistor 115 is coupled to thebase 116 oftransistor 110. Thecollector 112 oftransistor 110 and thecollector 117 oftransistor 115 are coupled to the VCC supply rail. Theemitter 118 of emitter-follower transistor 115 is coupled throughload resistor 119 to the (−)input 12 ofoperational amplifier 10. - The transimpedance circuit of FIG. 1 operates as follows. As pointed out above, the complementary currents Iin1 and Iin2 that are assumed to be flowing in the directions shown through the respective first (tip) and second (ring)
sense resistors - Iin1=I DIFF +I COM (1).
- Iin2=I DIFF −I COM (2).
- With
linearity compensator 70 coupled in differential configuration betweennodes follower transistors bases 91/111 ofCOMP transistors 90/110. With the base-emitter voltage being denoted as Vbe, this differential overhead voltage may be defined in equation (3) as: - However, a load current IRLOAD− through the
load resistor 99 of the (+) leg oflinearity compensator 70 effectively corresponds to the sum of the differential currents IRDIFF1− and IDIFF2− throughbias resistors - I LOAD99 =I RLOAD−=αN(I RDIFF1− +I RDIFF2−) (4),
- (where αN is a proportionality constant which, for practical purposes is equal to 1.0 and therefore, will not be delineated in subsequent expressions).
- Similarly, a load current IRLOAD+ through the (−) compensator
leg load resistor 119 effectively corresponds to the sum of the differential currents IRDIFF1+ and IRDIFF2+ through thebias resistors - Namely,
- I LOAD119 =I RLOAD+ =I RDIFF+ +I RDIFF2+ (5).
- In addition, the voltage VSENSE1 across the first (tip)
sense resistor 21 may be expressed as: - V SENSE1 =Iin1*R SENSE1 =Vbe 60(DIFF+)+(I RDIFF1+)*(R DIFF1+)−(I RDIFF1−)*(R DIFF1−)−Vbe 50(DIFF1−) (6).
- The voltage VSENSE2 across the second (ring)
sense resistor 22 may be expressed as: -
-
- Adding equations (6) and (7) yields:
- Iin1*R SENSE1 +Iin2*R SENSE2=(I RDIFF1+)*(R DIFF+)+(I RDIFF2+)*(R DIFF2+)−(I RDIFF1−)*( R DIFF1−)−(I RDIFF2−)*( R DIFF2−)−Vbe 55(DIFF2−) −Vbe 50(DIFF1−) +Vbe 65(DIFF2+) +Vbe 60(DIFF1+) (9).
- Subtracting equation (9) from equation (8) yields:
- ΔV OVHDem−(Iin1*R SENSE1 +Iin2*R SENSE2=(I RDIFF1+)*(R LOAD+ −R DIFF1−)+(I RDIFF2+)*(R LOAD+ −R DIFF2−)−(I RDIFF1−)*(R LOAD− −R DIFF1−)+(I RDIFF2−)*(R LOAD− −R DIFF2−)+[(Vbe 110(COMP+) −Vbe 90(COMP−))+[(Vbe 95(DIFF2−)+Vbe 50(DIFF−))]+[(Vbe 115(COMP+) −Vbe 95(COMP−))−[(Vbe65(DIFF2+)+Vbe 60(DIFF1+))] (10).
- This relationship may be alternatively expressed as:
- ΔV OHDem−(Iin1*R SENSE1 +Iin2*R SENSE2)=(I RDIFF1+)*(R LOAD+−RDIFF1−)+(I RDIFF2+)*(R LOAD+ −R DIFF2−)−(I RDIFF1−)*(R LOAD− −R DIFF1−)−(I RDIFF2−)*(R LOAD− −R DIFF2−)+(kT/q)*ln[{(I RDIFF1+ +I RDIFF2+)/(I RDIFF1 −I RDIFF2−)}2*(I RDIFF1− /I RDIFF1+)*(I RDIFF2− /I RDIFF2+)] (11)
- (where k is Boltzman's constant, T is absolute temperature, and q is the electron charge).
- Assuming that all emitter areas of the transistors are identical, and that the betas of
transistors - (kT/q)*ln[{(I RDIFF1+ +I RDIFF2+)/(I RDIFF1+)}*{(I RDIFF1+ +I RDIFF2+)/(I RDIFF2+)}*{(I RDIFF1−)/(I RDIFF1− +I RDIFF2−)}*{(I RDIFF2−)/(I RDIFF1− +I RDIFF2−)}], (12)
- or in expression (13) as:
- (kT/q)*ln[{1+ΔI 21+ /I RDIFF1+)+(¼)*(ΔI 21+ /I RDIFF1+)2}*{1+ΔI 21− /I RDIFF1−}*{1+ΔI 21− /I RDIFF1−)+(¼)*(ΔI 21− /I RDIFF1−)2}−1* {1+ΔI 21+ /I RDIFF1+}−1], (13)
- where IDIFF2+=IDIFF1++ΔI21+, and
- IDIFF2−=IDIFF1−+ΔI21−.
- For any practical conditions encountered in real applications, both quadratic terms found in equation (13) are negligible. This reduces expression (13) to:
- (kT/q)*ln[{1+ΔI 21+ /I RDIFF1+)}*{1+ΔI 21− /I RDIFF1−}*{1+ΔI 21− /I RDIFF1−}) −1*{1+ΔI 21+ /I RDIFF1+}−1], (14)
- which yields
- (kT/q)*ln[1]=0. (15)
- By matching the bias resistors so that RDIFF1+=RDIFF1−=RDIFF2+=RDIFF2−=R LOAD, and substituting in equation (11) yields:
- ΔV OHDem =Iin1*R SENSE1 +Iin2*R SENSE2 (16).
- If RSENSE1=RSENSE1=RSENSE (17), then
- ΔV OHDem=(Iin1+Iin2)*R SENSE (18).
- Substitution of equations (1) and (2) into equation (18) yields:
- ΔV OHDem=2*I DIFF *R SENSE (19),
- which lacks any contribution from the undesirable longitudinal components of equations (1) and (2).
-
- Again by matching circuit parameters, in particular, by making R75=R77; IOVHD1=IOVHD2; IBIAS1=IBIAS2; and using equal geometries for the
overhead transistors 80 and 100 (which is readily accomplished by placing these transistors immediately adjacent to each other using present day semiconductor processing), equation (20) reduces to: - VOUT=ΔVOHDem (21).
- Namely, the output voltage VOUT produced at the
output terminal 13 of theoperational amplifier 10 is relatively simply and linearly definable in terms of the sensed current IDIFF and the values of the sense resistors RSENSE. In particular, - V OUT=2*I DIFF *R SENSE (22).
- It may be noted that reversing the direction of the input currents Iin1 and Iin2 being sensed simply reverses the polarity of the output voltage VOUT supplied at
output terminal 13. - Equation (22) implies that if either of the two sensed currents Iin1 or Iin2 is flowing in a direction opposite to that shown in FIG. 1 and both currents have the same value, the resulting voltage VOUT in equation (22) approaches zero. Namely, by optimizing the match between the resistance value RSENSE of the
sense resistors bias resistors - While I have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art. I therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.
Claims (20)
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US09/686,506 US6292033B1 (en) | 2000-10-11 | 2000-10-11 | Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output |
US09/939,191 US6400187B1 (en) | 2000-10-11 | 2001-08-24 | Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output |
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US09/939,191 Expired - Fee Related US6400187B1 (en) | 2000-10-11 | 2001-08-24 | Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output |
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Cited By (1)
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EP1391985A2 (en) * | 2002-08-23 | 2004-02-25 | Broadcom Corporation | Wideband cmos gain stage |
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US6567521B1 (en) * | 1999-08-17 | 2003-05-20 | Silicon Laboratories, Inc. | Subscriber loop interface circuitry having bifurcated common mode control |
US6829354B1 (en) | 2000-10-11 | 2004-12-07 | Intersil Corporation | Biasing arrangement for optimizing DC feed characteristics for subscriber line interface circuit |
US6873703B1 (en) | 2000-10-11 | 2005-03-29 | Intersil Corporation | Precision, low-power current-sense transmission channel for subscriber line interface circuit, programmable with single ended impedances and capable of exhibiting a voltage sense response |
US6292033B1 (en) * | 2000-10-11 | 2001-09-18 | Intersil Corporation | Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output |
US7215764B2 (en) * | 2001-02-06 | 2007-05-08 | Legerity, Inc. | Current sensing echo cancellation device |
US6784750B2 (en) * | 2002-04-09 | 2004-08-31 | Microsemi Corporation | Transimpedance amplifier with selective DC compensation |
US6803825B2 (en) | 2002-04-09 | 2004-10-12 | Microsemi Corporation | Pseudo-differential transimpedance amplifier |
US7215200B1 (en) * | 2005-04-28 | 2007-05-08 | Linear Technology Corporation | High-linearity differential amplifier with flexible common-mode range |
US7668522B2 (en) * | 2006-06-29 | 2010-02-23 | Itt Manufacturing Enterprises, Inc. | Ultra wide band, differential input/output, high frequency active combiner in an integrated circuit |
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JPS5591219A (en) * | 1978-12-28 | 1980-07-10 | Nippon Gakki Seizo Kk | Amplifier |
DE19504290C1 (en) * | 1995-02-09 | 1996-02-01 | Siemens Ag | Transimpedance amplifier circuit with feedback-coupled voltage amplifier |
DE19518734C1 (en) * | 1995-05-22 | 1996-08-08 | Siemens Ag | Transimpedance amplifier circuit with controlled impedance |
US6292033B1 (en) * | 2000-10-11 | 2001-09-18 | Intersil Corporation | Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output |
-
2000
- 2000-10-11 US US09/686,506 patent/US6292033B1/en not_active Expired - Lifetime
-
2001
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1391985A2 (en) * | 2002-08-23 | 2004-02-25 | Broadcom Corporation | Wideband cmos gain stage |
US20040036534A1 (en) * | 2002-08-23 | 2004-02-26 | Gupta Sandeep Kumar | Wideband CMOS gain stage |
EP1391985A3 (en) * | 2002-08-23 | 2004-07-21 | Broadcom Corporation | Wideband cmos gain stage |
US6927631B2 (en) | 2002-08-23 | 2005-08-09 | Broadcom Corporation | Wideband CMOS gain stage |
US20050258902A1 (en) * | 2002-08-23 | 2005-11-24 | Broadcom Corporation | Wideband CMOS gain stage |
US7205840B2 (en) | 2002-08-23 | 2007-04-17 | Broadcom Corporation | Wideband CMOS gain stage |
US20070188232A1 (en) * | 2002-08-23 | 2007-08-16 | Broadcom Corporation | Wideband CMOS gain stage |
US8138839B2 (en) | 2002-08-23 | 2012-03-20 | Broadcom Corporation | Wideband CMOS gain stage |
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US6292033B1 (en) | 2001-09-18 |
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