US20020021163A1 - Method and circuit for lowering standby current in an integrated circuit - Google Patents
Method and circuit for lowering standby current in an integrated circuit Download PDFInfo
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- US20020021163A1 US20020021163A1 US09/858,246 US85824601A US2002021163A1 US 20020021163 A1 US20020021163 A1 US 20020021163A1 US 85824601 A US85824601 A US 85824601A US 2002021163 A1 US2002021163 A1 US 2002021163A1
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- 238000000034 method Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 158
- 239000004065 semiconductor Substances 0.000 claims abstract description 78
- 230000015654 memory Effects 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 238000009413 insulation Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
Definitions
- the present invention is related generally to semiconductor integrated circuits, and more specifically, to a circuit and method for reducing subthreshold leakage currents of transistors forming an integrated circuit.
- a typical integrated circuit includes numerous transistors formed in a semiconductor substrate and interconnected to perform desired functions.
- the transistors formed in the semiconductor substrate are typically metal oxide semiconductor (“MOS”) transistors having source, drain, and gate regions formed in the semiconductor substrate.
- MOS transistors have a threshold voltage V T corresponding to the gate-source voltage that must be exceeded to turn ON the transistor and allow current flow from the source region to the drain region of the transistor.
- V T threshold voltage
- MOS transistor metal oxide semiconductor
- One way to lower the subthreshold leakage current of a MOS transistor is to increase the threshold voltage V T .
- the threshold voltage V T of a MOS transistor can be increased by increasing the magnitude of the voltage applied to the substrate of the transistor, which is known as the back-bias voltage and is typically designated V bb .
- the back-bias voltage V bb is applied to the substrate for proper operation of the MOS transistor as known in the art.
- the subthreshold leakage current of the MOS transistor can be decreased by a corresponding increase in the back-bias voltage V bb .
- the threshold voltage V T When the threshold voltage V T is increased, however, the switching time of the MOS transistor increases accordingly because an input voltage coupled to the gate of the MOS transistor must now reach the higher threshold voltage V T before the transistor turns ON. In many integrated circuits, such as microprocessors, the threshold voltages V T must be maintained relatively low to decrease the switching time of the transistors. Thus, although the threshold voltage V T can be increased to lower the subthreshold leakage current of the transistor, in many applications the required performance of the integrated circuit will not allow such an increase in the threshold voltage V T .
- An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output.
- An external terminal is adapted to receive an external back-bias voltage.
- a semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit.
- the semiconductor substrate includes at least one transistor formed in the semiconductor substrate. The at least one transistor has a first threshold voltage when the internal back-bias voltage is applied to the semiconductor substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
- FIG. 1 is a block diagram of an integrated circuit formed according to one embodiment of the present invention.
- FIG. 2 is a block diagram of an electronic system including a number of the integrated circuits of FIG. 1.
- FIG. 3 is a block diagram of a semiconductor memory formed according to the present invention.
- FIG. 4 is a block diagram of a computer system including the semiconductor memory of FIG. 3.
- FIG. 1 is a block diagram of an integrated circuit 10 according to one embodiment of the present invention.
- the integrated circuit 10 includes a semiconductor substrate 12 in which a number of MOS transistors 14 are formed, one of which is shown in FIG. 1.
- the semiconductor substrate 12 is a p-type semiconductor.
- the MOS transistor 14 includes an n + source region 16 , and an n + drain region 18 formed in the semiconductor substrate 12 .
- the regions 16 and 18 may be formed through conventional process techniques, such as diffusion or ion implantation of a suitable dopant into the semiconductor substrate 12 .
- the n + source region 16 is spaced apart from the n + drain region 18 and a channel 20 of the MOS transistor 14 defined between these two regions.
- An insulation layer 22 is formed above the channel region 20 on a surface 24 of the semiconductor substrate 12 .
- the insulation layer 22 is an oxide, such as silicon dioxide, and is grown or otherwise deposited on the surface 24 using known process techniques.
- a conductive layer 26 such as a metal or polysilicon layer, is formed on the insulation layer 22 as shown, and forms the gate terminal of the transistor 14 .
- a conductive layer 28 is formed on the surface 24 above the source region 16 to form the source terminal of the MOS transistor 14
- a conductive layer 30 is formed above the drain region 18 to form the drain terminal of the MOS transistor 14 .
- a current flows from the drain region 18 through the channel region 20 to the source region 16 when a sufficient voltage is applied to the gate terminal of the MOS transistor 14 , as understood by one skilled in the art.
- the integrated circuit 10 further includes a substrate voltage pump circuit 32 that develops an internal back-bias voltage V bbint which is applied through a conductive layer 34 to the semiconductor substrate 12 .
- the pump circuit 32 is shown as separate from the substrate 12 , the pump circuit is typically formed in the substrate.
- the design and operation of the substrate voltage pump circuit 32 is conventional, and for the sake of brevity will not be described in further detail.
- the internal back-bias voltage V bbint has a magnitude and polarity which reverse biases the source-substrate junction, represented by a diode 36 , and drain-substrate junction, represented by a diode 38 , during normal operation of the MOS transistor 14 .
- the back-bias voltage V bbint typically has a value of approximately ⁇ 1.2 volts to allow the transistor to pass voltages from 0 volts to a supply voltage V DD on its source and drain terminals while maintaining the diodes 36 and 38 in a reverse bias condition.
- the integrated circuit 10 further includes an external terminal 40 receiving an external back-bias voltage V bbext from an external circuit (not shown in FIG. 1).
- the terminal 40 is coupled through a conductive layer 42 to the semiconductor substrate 12 .
- the external back-bias voltage V bbext has a greater magnitude and the same polarity as the internal back-bias voltage V bbint .
- V bbext when the external back-bias voltage V bbext is applied to the substrate 12 , a greater reverse bias voltage is applied across the source-substrate and drain-substrate junctions 36 and 38 .
- the internal back-bias voltage V bbint may equal the supply voltage V DD and the external back-bias voltage V bbext then has a magnitude greater than V DD .
- the integrated circuit 10 operates in two modes, an active mode and a standby mode.
- the active mode no external back-bias voltage V bbext is applied on the terminal 40 , and the transistors 14 operate such that the integrated circuit 10 performs its desired function.
- the substrate voltage pump circuit 32 applies the internal back-bias voltage V bbint to the substrate 12 .
- the threshold voltage V T of the transistor 14 is a function of the applied reverse bias voltage across the source-substrate junction 36 .
- the transistor 14 has a first threshold voltage V T1 defined by the internal back-bias voltage V bbint .
- the external circuit (not shown in FIG. 1) applies the external back-bias voltage V bbext on the terminal 40 , and this voltage is coupled to the semiconductor substrate 12 through the conductive layer 42 .
- the reverse bias voltage across the source-substrate junction 36 equals the external back-bias voltage V bbext , assuming the source of the transistor 14 is coupled to ground.
- the external circuitry applying the external back-bias voltage V bbext is capable of supplying a sufficient current to drive the substrate 12 to the external back-bias voltage V bbext even though the substrate voltage pump circuit 32 remains coupled to the substrate 12 and may simultaneously attempt to drive the substrate 12 to the internal back-bias voltage V bbint .
- the source-substrate junction 36 is reverse biased by this external back-bias voltage and the transistor 14 has a threshold voltage V T2 which is greater than V T1 .
- V T2 the greater reverse bias voltage applied across the source-substrate junction 36 and corresponding increased threshold voltage V T2 results in the transistor 14 having a lower subthreshold leakage current.
- the operation of the integrated circuit 10 in the standby mode reduces the power consumed by the integrated circuit.
- the transistors 14 When the integrated circuit 10 operates in the active mode, the transistors 14 have the threshold voltage V T1 and operate as they would in a conventional integrated circuit to perform the designed function of the integrated circuit 10 . In standby mode, however, the transistors 14 have the greater threshold voltage V T2 which reduces the subthreshold leakage current of the transistors 14 and results in a corresponding decrease in power consumption by the integrated circuit 10 .
- the standby mode of operation corresponds to a time when the integrated circuit 10 is not required to perform its designed function but remains coupled to its associated power supply. The integrated circuit 10 continues to draw power from the power supply in the standby mode, but the amount of power is significantly reduced by the reduced subthreshold leakage currents of the transistors 14 .
- the external back-bias voltage V bbext is also coupled directly to the substrate voltage pump circuit 32 as indicated by the dashed line 44 .
- the substrate voltage pump circuit 32 turns OFF when the external back-bias voltage V bbext is applied on the terminal 40 .
- the pump circuit may draw additional current in trying to maintain the substrate 12 at the internal back-bias voltage V bbint . In this situation, the additional current drawn by the pump circuit 32 may be greater than the total reduction of subthreshold leakage currents of the transistors 14 , and the pump circuit 32 must be turned OFF to realize additional power savings.
- the substrate voltage pump circuit 32 may include feedback circuitry operable to turn OFF the pump circuit when the internal back-bias voltage V bbint exceeds the desired value by a predetermined amount.
- the substrate voltage pump circuit 32 no direct connection between the pump circuit 32 and external back-bias voltage V bbext is required because the pump circuit turns OFF when the external back-bias voltage V bbext is applied to the substrates 12 , further reducing the power consumption of the integrated circuit 10 in the standby mode.
- Providing the external back-bias voltage V bbext from a circuit external of the integrated circuit 10 enables more efficient generation of the voltage V bbext than if the substrate voltage pump circuit 32 is used to generate this voltage. This is true because the pump circuit 32 typically consumes more current if operated to develop both the voltages V bbint and V bbext as understood by one skilled in the art. Thus, if the pump circuit 32 develops the voltage V bbext the reduced subthreshold leakage currents of the transistors 14 is offset by the increased current consumption of the pump circuit 32 . In contrast, the present invention utilizes the voltage V bbext developed by an external circuit that may include more efficient circuitry for developing the voltage V bbext .
- a single external circuit can provide the voltage V bbext to a number of the integrated circuits 10 , further reducing the overall power consumption of a system including a plurality of the integrated circuits 10 .
- An external circuit operable to efficiently develop the voltage V bbext is conventional and thus, for the sake of brevity, will not be described in further detail.
- FIG. 2 is a block diagram of an electronic system 100 including a number of the integrated circuits 10 of FIG. 1.
- An external circuit 102 detects active and standby conditions of each of the integrated circuits 10 and controls the state of a signal applied on the terminals 40 of the integrated circuits 10 in response to the detected conditions.
- the external circuit 102 detects any of the integrated circuits 10 in the active condition, the external circuit 102 presents a high impedance on each of the external terminals 40 placing all the integrated circuits 10 in the active mode and thereby causing the transistors 14 in each of the integrated circuits 10 to have the first threshold voltage V T .
- the external circuit 102 If the external circuit 102 detects all the integrated circuits 10 are in the standby condition, the external circuit 102 supplies the external back-bias voltage V bbext on the terminals 40 placing the integrated circuits 10 in the standby mode and thereby causing the transistors 14 to have the second threshold voltage V T2 .
- the external circuit 102 may detect active and standby conditions in many different ways as understood by one skilled in the art. For example, if the integrated circuits 10 are memory devices, the external circuit 10 may include transition detection circuitry coupled to an address bus of the memory devices.
- a transition of a signal on any line of the address bus indicates at least one of the memory devices is in the active condition and the external circuit 102 presents a high impedance on the external terminals 40 .
- No transition on any line of the address bus for a predetermined time indicates all of the memory devices are in the standby condition, and the external circuit 102 applies the external back-bias voltage V bbext on the terninals 40 to place the memory devices in the standby mode.
- the external circuit 102 provides separate outputs to each of the respective terminals 40 .
- the external circuit 102 detects active and standby conditions of each of the individual integrated circuits 10 enabling each integrated circuit 10 to be independently placed in the standby or active mode.
- FIG. 3 is a block diagram of a memory device 200 , such as a dynamic random access memory, including the external terminal 40 and substrate voltage pump circuit 32 of FIG. 1.
- the substrate voltage pump circuit 32 applies the back-bias voltage V bbint to address decode circuitry 202 , control circuitry 204 , read/write circuitry 206 , and a memory cell array 208 formed in a semiconductor substrate (not shown in FIG. 3).
- the external terminal 40 is also connected to the elements 202 - 208 to apply the external back-bias voltage V bbext to these elements. More specifically, the external terminal is coupled to the semiconductor substrate in which these elements are formed.
- the address decode circuitry 202 , control circuitry 204 , read/write circuitry 206 , and memory cell array 208 are all conventional and known in the art.
- the address decode circuitry 202 , control circuitry 204 , and read/write circuitry are all coupled to the memory cell array 208 , and further coupled to an address bus, control bus, and data bus, respectively.
- an external circuit such as a memory controller or a processor, applies address, control, and data signals on the respective buses of the memory device 200 .
- the external circuit provides a memory address on the address bus and control signals on the control bus.
- the address decode circuitry 202 provides a decoded memory address to the memory-cell array 208
- the control circuitry 204 provides control signals to the memory-cell array 208 in response to the control signals on the control bus.
- the control signals from the control circuitry 204 control the memory-cell array 208 so that the memory-cell array provides the addressed data to the read/write circuitry 206 , which in turn outputs this data on the data bus for use by the external circuit.
- the external circuitry provides a memory address on the address bus, control signals on the control bus, and data on the data bus.
- the address decode circuitry 202 decodes the memory address on the address bus and provides a decoded address to the memory-cell array 208 .
- the read/write circuitry 206 provides the data on the data bus to the memory-cell array 208 , and this data is stored in the addressed memory cells in the memory-cell array 208 under control of the control circuitry 204 .
- the external circuit When the memory device 200 is active, which includes operation during read cycles, write cycles, and refresh cycles, the external circuit presents a high impedance on the terminal 40 , and the internal back-bias voltage V bbint supplied by the substrate voltage pump circuit 32 determines the threshold voltages V T1 of the transistors comprising the memory device 200 .
- the external circuit In standby mode, such as when the external circuit is not reading data from, writing data to, or refreshing data, the external circuit applies the external back-bias voltage V bbext on the terminal 40 to reduce the power consumption of the memory device 200 by lowering the subthreshold leakage currents of the transistors comprising the memory device as previously described. It should be noted that during standby, data stored in the memory device 200 still needs to be refreshed. Speed is not critical for data refresh when the memory device 200 is not active so the back-bias voltage could be maintained at the standby back-bias voltage V bbext during such a refresh.
- FIG. 3 depicts the present invention in a memory device
- many types of integrated currents may realize significant power savings from the present invention.
- the transistors are typically formed having minimum threshold voltages to decrease their switching time. As previously discussed, such minimum threshold voltages increase the subthreshold leakage currents of the transistors and the present invention may result in significant power reduction when the microprocessor, or portions of the microprocessor, are operating in standby mode.
- FIG. 4 is a block diagram of a computer system 300 which uses the memory device 200 of FIG. 3.
- the computer system 300 includes computer circuitry 302 for performing various computing functions, such as executing specific software to perform specific calculations or tasks.
- the computer system 300 includes one or more input devices 304 , such as a keyboard or a mouse, coupled to the computer circuitry 302 to allow an operator to interface with the computer system.
- the computer system 300 also includes one or more output devices 306 coupled to the computer circuitry 302 , such output devices typically being a printer or a video terminal.
- One or more data storage devices 308 are also typically coupled to the computer circuitry 302 to store data or retrieve data from external storage media (not shown).
- Examples of typical storage devices 308 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).
- the computer circuitry 302 is typically coupled to the memory device 200 through a control bus, a data bus, and an address bus to provide for writing data to and reading data from the memory device.
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Abstract
An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output, and an external terminal adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit. The semiconductor substrate includes at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate. The at least one transistor has a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
Description
- The present invention is related generally to semiconductor integrated circuits, and more specifically, to a circuit and method for reducing subthreshold leakage currents of transistors forming an integrated circuit.
- A typical integrated circuit includes numerous transistors formed in a semiconductor substrate and interconnected to perform desired functions. In many integrated circuits, such as semiconductor memories or microprocessors, the transistors formed in the semiconductor substrate are typically metal oxide semiconductor (“MOS”) transistors having source, drain, and gate regions formed in the semiconductor substrate. Each MOS transistor has a threshold voltage VT corresponding to the gate-source voltage that must be exceeded to turn ON the transistor and allow current flow from the source region to the drain region of the transistor. In an ideal MOS transistor, for gate-to-source voltages less than the threshold voltage VT, no current flows between the source and drain regions. In an actual MOS transistor, however, there is current flow between the source and drain regions when the gate-to-source voltage is less than the threshold voltage VT. This current which flows for gate-to-source voltages less than the threshold voltage VT is known as the subthreshold leakage current of the transistor.
- Due to the subthreshold leakage currents of transistors forming the integrated circuit, a significant amount of power may be consumed by the integrated circuit even when all of the MOS transistors are turned OFF. This is true since millions of transistors may comprise an integrated circuit, and, while the subthreshold leakage current of an individual transistor is negligible, in the aggregate such subthreshold leakage currents can result in significant power consumption.
- One way to lower the subthreshold leakage current of a MOS transistor is to increase the threshold voltage VT. By increasing the threshold voltage VT, a smaller subthreshold leakage current flows for a given gate-to-source voltage. The threshold voltage VT of a MOS transistor can be increased by increasing the magnitude of the voltage applied to the substrate of the transistor, which is known as the back-bias voltage and is typically designated Vbb. The back-bias voltage Vbb is applied to the substrate for proper operation of the MOS transistor as known in the art. Thus, the subthreshold leakage current of the MOS transistor can be decreased by a corresponding increase in the back-bias voltage Vbb. When the threshold voltage VT is increased, however, the switching time of the MOS transistor increases accordingly because an input voltage coupled to the gate of the MOS transistor must now reach the higher threshold voltage VT before the transistor turns ON. In many integrated circuits, such as microprocessors, the threshold voltages VT must be maintained relatively low to decrease the switching time of the transistors. Thus, although the threshold voltage VT can be increased to lower the subthreshold leakage current of the transistor, in many applications the required performance of the integrated circuit will not allow such an increase in the threshold voltage VT.
- There is a need for decreasing the subthreshold leakage current of MOS transistors forming an integrated circuit while at the same time allowing for high speed operation of such transistors.
- An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output. An external terminal is adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit The semiconductor substrate includes at least one transistor formed in the semiconductor substrate. The at least one transistor has a first threshold voltage when the internal back-bias voltage is applied to the semiconductor substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
- FIG. 1 is a block diagram of an integrated circuit formed according to one embodiment of the present invention.
- FIG. 2 is a block diagram of an electronic system including a number of the integrated circuits of FIG. 1.
- FIG. 3 is a block diagram of a semiconductor memory formed according to the present invention.
- FIG. 4 is a block diagram of a computer system including the semiconductor memory of FIG. 3.
- FIG. 1 is a block diagram of an integrated
circuit 10 according to one embodiment of the present invention. The integratedcircuit 10 includes asemiconductor substrate 12 in which a number ofMOS transistors 14 are formed, one of which is shown in FIG. 1. In the illustrated embodiment, thesemiconductor substrate 12 is a p-type semiconductor. One skilled in the art will realize, however, that the present invention is equally applicable to integrated circuits formed in n-type semiconductor substrates. TheMOS transistor 14 includes an n+ source region 16, and an n+ drain region 18 formed in thesemiconductor substrate 12. Theregions semiconductor substrate 12. The n+ source region 16 is spaced apart from the n+ drain region 18 and achannel 20 of theMOS transistor 14 defined between these two regions. Aninsulation layer 22 is formed above thechannel region 20 on asurface 24 of thesemiconductor substrate 12. Typically, theinsulation layer 22 is an oxide, such as silicon dioxide, and is grown or otherwise deposited on thesurface 24 using known process techniques. Aconductive layer 26, such as a metal or polysilicon layer, is formed on theinsulation layer 22 as shown, and forms the gate terminal of thetransistor 14. In the same way, aconductive layer 28 is formed on thesurface 24 above thesource region 16 to form the source terminal of theMOS transistor 14, and aconductive layer 30 is formed above thedrain region 18 to form the drain terminal of theMOS transistor 14. In operation, a current flows from thedrain region 18 through thechannel region 20 to thesource region 16 when a sufficient voltage is applied to the gate terminal of theMOS transistor 14, as understood by one skilled in the art. - The integrated
circuit 10 further includes a substratevoltage pump circuit 32 that develops an internal back-bias voltage Vbbint which is applied through aconductive layer 34 to thesemiconductor substrate 12. Although thepump circuit 32 is shown as separate from thesubstrate 12, the pump circuit is typically formed in the substrate. The design and operation of the substratevoltage pump circuit 32 is conventional, and for the sake of brevity will not be described in further detail. The internal back-bias voltage Vbbint has a magnitude and polarity which reverse biases the source-substrate junction, represented by adiode 36, and drain-substrate junction, represented by adiode 38, during normal operation of theMOS transistor 14. For theMOS transistor 14, the back-bias voltage Vbbint typically has a value of approximately −1.2 volts to allow the transistor to pass voltages from 0 volts to a supply voltage VDD on its source and drain terminals while maintaining thediodes - The integrated
circuit 10 further includes anexternal terminal 40 receiving an external back-bias voltage Vbbext from an external circuit (not shown in FIG. 1). Theterminal 40 is coupled through aconductive layer 42 to thesemiconductor substrate 12. The external back-bias voltage Vbbext has a greater magnitude and the same polarity as the internal back-bias voltage Vbbint. Thus, when the external back-bias voltage Vbbext is applied to thesubstrate 12, a greater reverse bias voltage is applied across the source-substrate and drain-substrate junctions - The
integrated circuit 10 operates in two modes, an active mode and a standby mode. During the active mode, no external back-bias voltage Vbbext is applied on theterminal 40, and thetransistors 14 operate such that theintegrated circuit 10 performs its desired function. In the active mode, the substratevoltage pump circuit 32 applies the internal back-bias voltage Vbbint to thesubstrate 12. As previously described, the threshold voltage VT of thetransistor 14 is a function of the applied reverse bias voltage across the source-substrate junction 36. Thus, during the active mode, thetransistor 14 has a first threshold voltage VT1 defined by the internal back-bias voltage Vbbint. - In the standby mode of operation, the external circuit (not shown in FIG. 1) applies the external back-bias voltage Vbbext on the
terminal 40, and this voltage is coupled to thesemiconductor substrate 12 through theconductive layer 42. When the external back-bias voltage Vbbext is coupled to thesemiconductor substrate 12, the reverse bias voltage across the source-substrate junction 36 equals the external back-bias voltage Vbbext, assuming the source of thetransistor 14 is coupled to ground. The external circuitry applying the external back-bias voltage Vbbext is capable of supplying a sufficient current to drive thesubstrate 12 to the external back-bias voltage Vbbext even though the substratevoltage pump circuit 32 remains coupled to thesubstrate 12 and may simultaneously attempt to drive thesubstrate 12 to the internal back-bias voltage Vbbint. When the external back-bias voltage Vbbext is coupled to thesubstrate 12, the source-substrate junction 36 is reverse biased by this external back-bias voltage and thetransistor 14 has a threshold voltage VT2 which is greater than VT1. As previously described, the greater reverse bias voltage applied across the source-substrate junction 36 and corresponding increased threshold voltage VT2 results in thetransistor 14 having a lower subthreshold leakage current. - The operation of the
integrated circuit 10 in the standby mode reduces the power consumed by the integrated circuit. When theintegrated circuit 10 operates in the active mode, thetransistors 14 have the threshold voltage VT1 and operate as they would in a conventional integrated circuit to perform the designed function of theintegrated circuit 10. In standby mode, however, thetransistors 14 have the greater threshold voltage VT2 which reduces the subthreshold leakage current of thetransistors 14 and results in a corresponding decrease in power consumption by the integratedcircuit 10. The standby mode of operation corresponds to a time when the integratedcircuit 10 is not required to perform its designed function but remains coupled to its associated power supply. The integratedcircuit 10 continues to draw power from the power supply in the standby mode, but the amount of power is significantly reduced by the reduced subthreshold leakage currents of thetransistors 14. - In an alternative embodiment of the integrated
circuit 10 of FIG. 1, the external back-bias voltage Vbbext is also coupled directly to the substratevoltage pump circuit 32 as indicated by thedashed line 44. In this embodiment, the substratevoltage pump circuit 32 turns OFF when the external back-bias voltage Vbbext is applied on theterminal 40. It should be noted that if the substratevoltage pump circuit 32 is not turned OFF, the pump circuit may draw additional current in trying to maintain thesubstrate 12 at the internal back-bias voltage Vbbint. In this situation, the additional current drawn by thepump circuit 32 may be greater than the total reduction of subthreshold leakage currents of thetransistors 14, and thepump circuit 32 must be turned OFF to realize additional power savings. - Typically, the substrate
voltage pump circuit 32 may include feedback circuitry operable to turn OFF the pump circuit when the internal back-bias voltage Vbbint exceeds the desired value by a predetermined amount. For such a substratevoltage pump circuit 32, no direct connection between thepump circuit 32 and external back-bias voltage Vbbext is required because the pump circuit turns OFF when the external back-bias voltage Vbbext is applied to thesubstrates 12, further reducing the power consumption of theintegrated circuit 10 in the standby mode. - Providing the external back-bias voltage Vbbext from a circuit external of the
integrated circuit 10 enables more efficient generation of the voltage Vbbext than if the substratevoltage pump circuit 32 is used to generate this voltage. This is true because thepump circuit 32 typically consumes more current if operated to develop both the voltages Vbbint and Vbbext as understood by one skilled in the art. Thus, if thepump circuit 32 develops the voltage Vbbext the reduced subthreshold leakage currents of thetransistors 14 is offset by the increased current consumption of thepump circuit 32. In contrast, the present invention utilizes the voltage Vbbext developed by an external circuit that may include more efficient circuitry for developing the voltage Vbbext. Furthermore, with the present invention a single external circuit can provide the voltage Vbbext to a number of theintegrated circuits 10, further reducing the overall power consumption of a system including a plurality of theintegrated circuits 10. An external circuit operable to efficiently develop the voltage Vbbext is conventional and thus, for the sake of brevity, will not be described in further detail. - FIG. 2 is a block diagram of an
electronic system 100 including a number of theintegrated circuits 10 of FIG. 1. Anexternal circuit 102 detects active and standby conditions of each of theintegrated circuits 10 and controls the state of a signal applied on theterminals 40 of theintegrated circuits 10 in response to the detected conditions. When theexternal circuit 102 detects any of theintegrated circuits 10 in the active condition, theexternal circuit 102 presents a high impedance on each of theexternal terminals 40 placing all theintegrated circuits 10 in the active mode and thereby causing thetransistors 14 in each of theintegrated circuits 10 to have the first threshold voltage VT. If theexternal circuit 102 detects all theintegrated circuits 10 are in the standby condition, theexternal circuit 102 supplies the external back-bias voltage Vbbext on theterminals 40 placing theintegrated circuits 10 in the standby mode and thereby causing thetransistors 14 to have the second threshold voltage VT2. Depending on function of theintegrated circuits 10, theexternal circuit 102 may detect active and standby conditions in many different ways as understood by one skilled in the art. For example, if theintegrated circuits 10 are memory devices, theexternal circuit 10 may include transition detection circuitry coupled to an address bus of the memory devices. In such a system, a transition of a signal on any line of the address bus indicates at least one of the memory devices is in the active condition and theexternal circuit 102 presents a high impedance on theexternal terminals 40. No transition on any line of the address bus for a predetermined time indicates all of the memory devices are in the standby condition, and theexternal circuit 102 applies the external back-bias voltage Vbbext on theterninals 40 to place the memory devices in the standby mode. - In another embodiment of the
electronic system 100, theexternal circuit 102 provides separate outputs to each of therespective terminals 40. In this embodiment, theexternal circuit 102 detects active and standby conditions of each of the individualintegrated circuits 10 enabling eachintegrated circuit 10 to be independently placed in the standby or active mode. - FIG. 3 is a block diagram of a
memory device 200, such as a dynamic random access memory, including theexternal terminal 40 and substratevoltage pump circuit 32 of FIG. 1. The substratevoltage pump circuit 32 applies the back-bias voltage Vbbint to addressdecode circuitry 202,control circuitry 204, read/write circuitry 206, and amemory cell array 208 formed in a semiconductor substrate (not shown in FIG. 3). Theexternal terminal 40 is also connected to the elements 202-208 to apply the external back-bias voltage Vbbext to these elements. More specifically, the external terminal is coupled to the semiconductor substrate in which these elements are formed. Theaddress decode circuitry 202,control circuitry 204, read/write circuitry 206, andmemory cell array 208 are all conventional and known in the art. Theaddress decode circuitry 202,control circuitry 204, and read/write circuitry are all coupled to thememory cell array 208, and further coupled to an address bus, control bus, and data bus, respectively. - In operation, an external circuit, such as a memory controller or a processor, applies address, control, and data signals on the respective buses of the
memory device 200. During a read cycle, the external circuit provides a memory address on the address bus and control signals on the control bus. In response to the address on the address bus, theaddress decode circuitry 202 provides a decoded memory address to the memory-cell array 208, and thecontrol circuitry 204 provides control signals to the memory-cell array 208 in response to the control signals on the control bus. The control signals from thecontrol circuitry 204 control the memory-cell array 208 so that the memory-cell array provides the addressed data to the read/write circuitry 206, which in turn outputs this data on the data bus for use by the external circuit. During a write cycle, the external circuitry provides a memory address on the address bus, control signals on the control bus, and data on the data bus. Once again, theaddress decode circuitry 202 decodes the memory address on the address bus and provides a decoded address to the memory-cell array 208. The read/write circuitry 206 provides the data on the data bus to the memory-cell array 208, and this data is stored in the addressed memory cells in the memory-cell array 208 under control of thecontrol circuitry 204. - When the
memory device 200 is active, which includes operation during read cycles, write cycles, and refresh cycles, the external circuit presents a high impedance on the terminal 40, and the internal back-bias voltage Vbbint supplied by the substratevoltage pump circuit 32 determines the threshold voltages VT1 of the transistors comprising thememory device 200. In standby mode, such as when the external circuit is not reading data from, writing data to, or refreshing data, the external circuit applies the external back-bias voltage Vbbext on the terminal 40 to reduce the power consumption of thememory device 200 by lowering the subthreshold leakage currents of the transistors comprising the memory device as previously described. It should be noted that during standby, data stored in thememory device 200 still needs to be refreshed. Speed is not critical for data refresh when thememory device 200 is not active so the back-bias voltage could be maintained at the standby back-bias voltage Vbbext during such a refresh. - Although FIG. 3 depicts the present invention in a memory device, many types of integrated currents may realize significant power savings from the present invention. For example, in a microprocessor the transistors are typically formed having minimum threshold voltages to decrease their switching time. As previously discussed, such minimum threshold voltages increase the subthreshold leakage currents of the transistors and the present invention may result in significant power reduction when the microprocessor, or portions of the microprocessor, are operating in standby mode.
- FIG. 4 is a block diagram of a
computer system 300 which uses thememory device 200 of FIG. 3. Thecomputer system 300 includescomputer circuitry 302 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. In addition, thecomputer system 300 includes one ormore input devices 304, such as a keyboard or a mouse, coupled to thecomputer circuitry 302 to allow an operator to interface with the computer system. Typically, thecomputer system 300 also includes one ormore output devices 306 coupled to thecomputer circuitry 302, such output devices typically being a printer or a video terminal. One or moredata storage devices 308 are also typically coupled to thecomputer circuitry 302 to store data or retrieve data from external storage media (not shown). Examples oftypical storage devices 308 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). Thecomputer circuitry 302 is typically coupled to thememory device 200 through a control bus, a data bus, and an address bus to provide for writing data to and reading data from the memory device. - It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the-appended claims.
Exhibit A Appl. No. Atty Dkt # Applicants Filed Title 09/359,925 660073.603D1 Monte Manning July 22, 99 Method and Circuit for Lowering Standby Current in an Integrated Circuit
Claims (33)
1. An integrated circuit, comprising:
a substrate pump circuit developing an internal back-bias voltage on an output;
an external terminal adapted to receive an external back-bias voltage; and
a semiconductor substrate coupled to the external terminal and to the output of the substrate pump circuit, the semiconductor substrate including at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
2. The integrated circuit of claim 1 wherein substrate pump circuit is further coupled to the external terminal and operates in a first mode to develop the internal back-bias voltage when no external back-bias voltage is received on the external terminal, and operates in a second mode to turn off so no internal back-bias voltage is developed on the output when the external back-bias voltage is received on the external terminal.
3. The integrated circuit of claim 1 wherein the semiconductor substrate is a p-type semiconductor substrate.
4. The integrated circuit of claim 1 wherein the internal back-bias voltage has a value of approximately −1.2 volts, and the external back-bias voltage has value less than −1.2 volts.
5. The integrated circuit of claim 1 wherein the substrate pump circuit is formed in the semiconductor substrate.
6. The integrated circuit of claim 1 wherein the at least one transistor is a metal oxide semiconductor (MOS) transistor.
7. An integrated circuit, comprising:
a semiconductor substrate having a first conductivity type;
a plurality of transistors, each transistor including source and drain regions having a second conductivity type formed in the semiconductor substrate;
an external terminal coupled to the semiconductor substrate and adapted to receive an external back-bias voltage having a first magnitude and a polarity to reverse bias the source-substrate and drain-substrate junctions of each transistor; and
a substrate voltage circuit coupled to the semiconductor substrate, the substrate voltage circuit applying to the semiconductor substrate an internal back-bias voltage having a second magnitude and the polarity to reverse bias the source-substrate and drain-substrate junctions of each transistor, the second magnitude being less than the first magnitude.
8. The integrated circuit of claim 7 wherein the substrate voltage circuit applies to the semiconductor substrate the internal back-bias voltage when no external back-bias voltage is received on the external terminal, and turns off so no internal back-bias voltage is applied to the semiconductor substrate when the external back-bias voltage is received on the external terminal.
9. The integrated circuit of claim 7 wherein the first conductivity type is p-type and the second conductivity type is n-type.
10. The integrated circuit of claim 7 wherein the substrate pump circuit is formed in the semiconductor substrate.
11. The integrated circuit of claim 7 , further including at least one transistor having source and drain regions of the first conductivity type formed in a well region of the second conductivity type formed in the substrate, the source-substrate and drain-substrate junctions of the at least one transistor reverse biased by a first back-bias voltage when no external back-bias voltage is received on the external terminal, and the source-substrate and drain-substrate junctions of the at least one transistor reverse biased by second back-bias voltage greater than the first back-bias voltage when the external back-bias voltage is received on the external terminal.
12. A dynamic random access memory, comprising:
an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a control circuit coupled the control bus;
a read/write circuit coupled to the data bus;
a substrate pump circuit developing an internal back-bias voltage on an output;
an external terminal adapted to receive an external back-bias voltage; and
a semiconductor substrate coupled to the external terminal and to the output of the substrate pump circuit, the semiconductor substrate including at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
13. The dynamic random access memory of claim 12 wherein each memory cell comprises:
an access transistor having a gate terminal coupled to an associated word line, a drain terminal coupled to an associated digit line, and a source terminal; and
a capacitor having a first plate coupled to the source terminal, and a second plate coupled to receive a reference voltage.
14. A microprocessor, comprising:
a semiconductor substrate;
computing circuitry including at least one transistor formed in the semiconductor substrate;
a substrate pump circuit having an output coupled to the semiconductor substrate, the substrate pump circuit developing on the output an internal back-bias voltage; and
an external terminal of the microprocessor coupled to the semiconductor substrate, the external terminal adapted to receive an external back-bias voltage, and the at least one transistor having a first threshold voltage when the internal back-bias voltage is applied to the substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
15. The microprocessor of claim 14 wherein the substrate pump circuit is formed in the semiconductor substrate.
16. The microprocessor of claim 14 wherein substrate pump circuit is further coupled to the external terminal and operates in a first mode to develop the internal back-bias voltage when no external back-bias voltage is received on the external terminal, and operable in a second mode to turn off when the external back-bias voltage is received on the external terminal.
17. The microprocessor of claim 14 wherein the semiconductor substrate is a p-type semiconductor substrate.
18. The microprocessor of claim 14 wherein the internal back-bias voltage has a value of approximately -−1.2 volts, and the external back-bias voltage has value less than −1.2 volts.
19. A computer system, comprising:
a data input device;
a data output device; and
computing circuitry coupled to the data input and output devices, and coupled to an external terminal of a dynamic random access memory that includes,
a substrate pump circuit developing an internal back-bias voltage on an output,
the external terminal adapted to receive an external back-bias voltage from the computing circuitry, and
a semiconductor substrate coupled to the external terminal and to the output of the substrate pump circuit, the semiconductor substrate including at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
20. A computer system, comprising:
a data input device;
a data output device;
computing circuitry including,
a substrate pump circuit developing an internal back-bias voltage on an output,
an external terminal adapted to receive an external back-bias voltage, and
a semiconductor substrate coupled to the external terminal and to the output of the substrate pump circuit, the semiconductor substrate including at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal; and
a power supply circuit coupled to the external terminal which develops the external back-bias voltage, the power supply circuit applying the external back- bias voltage when the computing circuitry operates in a standby mode, and the power supply circuit applying no external back-bias voltage when the computing circuitry operates in an active mode.
21. An integrated circuit, comprising:
an external terminal adapted to receive an external back-bias voltage;
a substrate voltage pump circuit developing an internal back-bias voltage on an output coupled to the external terminal, and operable to turn off when the external back-bias voltage is received on the external terminal; and
a semiconductor substrate coupled to the external terminal, the semiconductor substrate including at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
22. The integrated circuit of claim 21 wherein the semiconductor substrate is a p-type semiconductor substrate.
23. The integrated circuit of claim 21 wherein the internal back-bias voltage has a value of approximately −1.2 volts, and the external back-bias voltage has value less than −1.2 volts.
24. The integrated circuit of claim 21 wherein the at least one transistor is a metal oxide semiconductor(MOS) transistor.
25. An integrated circuit, comprising:
a semiconductor substrate having a first conductivity type;
a plurality of transistors, each transistor including source and drain regions having a second conductivity type formed in the semiconductor substrate;
an external terminal coupled to the semiconductor substrate and adapted to receive an external back-bias voltage having a first magnitude and a polarity to reverse bias the source-substrate and drain-substrate junctions of each transistor; and
a substrate voltage pump circuit having an output coupled to the semiconductor substrate and developing on the output an internal back-bias voltage having a second magnitude and the polarity to reverse bias the source-substrate and drain-substrate junctions of each transistor, the second magnitude being less than the first magnitude, and the substrate pump circuit turning off when the voltage on the output is greater than the second magnitude by a predetermined amount.
26. The integrated circuit of claim 25 wherein the first conductivity type is p-type and the second conductivity type is n-type.
27. The integrated circuit of claim 7 , further including at least one transistor having source and drain regions of the first conductivity type formed in a well region of the second conductivity type formed in the substrate, the source-substrate and drain-substrate junctions of the at least one transistor reverse biased by a first back-bias voltage when no external back-bias voltage is received on the external terminal, and the source-substrate and drain-substrate junctions of the at least one transistor reverse biased by second back-bias voltage greater than the first back-bias voltage when the external back-bias voltage is received on the external terminal.
28. An electronic system, comprising:
a plurality of integrated circuits, each integrated circuit including,
an external terminal adapted to receive an external back-bias voltage,
a substrate voltage pump circuit developing an internal back-bias voltage on an output coupled to the external terminal and operable to turn off when the external back-bias voltage is received on the external terminal, and
a semiconductor substrate coupled to the external terminal, the semiconductor substrate including at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal; and
an external circuit having a plurality of outputs coupled respectively to the external terminals of the plurality of integrated circuits, the external circuit developing the external back-bias voltage on the external terminals of all integrated circuits operating in a standby condition, and presenting a high impedance on each of its outputs coupled to the external terminals of integrated circuits operating in an active condition.
29. The electronic system of claim 28 wherein the all of the external terminals are coupled together, and the external circuit develops the external back-bias voltage on all the external terminals when all the integrated circuits are operating in the standby mode, and presents a high impedance on all of the external terminals when any of the integrated circuits is operating in the active mode.
30. A method for reducing power consumption in an integrated circuit having a semiconductor substrate in which at least one transistor is formed, the method comprising the steps of:
applying a first back-bias voltage to the semiconductor substrate, each of the transistors on the semiconductor substrate having an associated first threshold voltage when the first back-bias voltage is applied to the substrate;
receiving an external standby signal; and
applying a second back-bias voltage to the substrate when the external. standby signal is active, the second back-bias voltage having a magnitude and polarity which increases the associated threshold values of the transistors on the semiconductor substrate.
31. The method of claim 30 wherein the step of receiving an external standby signal includes receiving the second back-bias voltage.
32. A method for reducing power consumption in an integrated circuit including an external terminal coupled to a semiconductor substrate in which at least one MOS transistor is formed, the method comprising the steps of:
applying to the semiconductor substrate a first back-bias voltage having a first magnitude and polarity; and
applying to the external terminal a second back-bias voltage having the polarity and a second magnitude greater than the first magnitude.
33. The method of claim 32 , further including the steps of applying the first back-bias voltage when the integrated circuit is operating in an active mode, and applying the second back-bias voltage when the integrated circuit is operating in a standby mode.
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US09/858,246 US6462610B1 (en) | 1998-02-18 | 2001-05-15 | Method and circuit for lowering standby current in an integrated circuit |
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US09/027,111 US6163044A (en) | 1998-02-18 | 1998-02-18 | Method and circuit for lowering standby current in an integrated circuit |
US09/359,925 US6320453B1 (en) | 1998-02-18 | 1999-07-22 | Method and circuit for lowering standby current in an integrated circuit |
US09/858,246 US6462610B1 (en) | 1998-02-18 | 2001-05-15 | Method and circuit for lowering standby current in an integrated circuit |
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US09/359,925 Continuation US6320453B1 (en) | 1998-02-18 | 1999-07-22 | Method and circuit for lowering standby current in an integrated circuit |
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US09/668,043 Expired - Fee Related US6373755B1 (en) | 1998-02-18 | 2000-09-21 | Method and circuit for lowering standby current in an integrated circuit |
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US6320453B1 (en) | 2001-11-20 |
US6373755B1 (en) | 2002-04-16 |
US6462610B1 (en) | 2002-10-08 |
US6163044A (en) | 2000-12-19 |
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