US20020018356A1 - Memory configuration including a plurality of resistive ferroelectric memory cells - Google Patents
Memory configuration including a plurality of resistive ferroelectric memory cells Download PDFInfo
- Publication number
- US20020018356A1 US20020018356A1 US09/767,807 US76780701A US2002018356A1 US 20020018356 A1 US20020018356 A1 US 20020018356A1 US 76780701 A US76780701 A US 76780701A US 2002018356 A1 US2002018356 A1 US 2002018356A1
- Authority
- US
- United States
- Prior art keywords
- resistor
- resistance value
- memory configuration
- electrode
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
Definitions
- the invention relates to a memory configuration which is formed of a plurality of resistive ferroelectric memory cells.
- Each of the memory cells is formed of a selection transistor and a storage capacitor.
- One electrode of the storage capacitor is connected to a fixed cell plate voltage and the other electrode of the storage capacitor is connected to a zone of the storage capacitor that has a first conductivity type.
- the selection transistor and the storage capacitor are provided in or on a semiconductor substrate of a second conductivity type opposite the first conductivity type.
- Ferroelectric memory configurations in which the cell plate voltage is permanently set to half the supply voltage (Vcc/2) of the memory configuration are characterized by rapid memory operations.
- Vcc/2 supply voltage
- the memory cells are refreshed before their contents are destroyed.
- the refresh is carried out by the bit lines of the memory configuration being precharged to half the supply voltage Vcc/2, and the cell nodes being also charged to half the supply voltage Vcc/2 by activating the word lines, with the result that 0 V drops across the storage capacitors.
- a memory configuration including:
- each of the resistive ferroelectric memory cells including a selection transistor and a storage capacitor
- the selection transistor having a given zone of a first conductivity type
- the storage capacitor having a first electrode and a second electrode, the first electrode being supplied with a fixed cell plate voltage, the second electrode being connected to the given zone of the first conductivity type;
- the selection transistor and the storage capacitor respectively being provided in or on the semiconductor body
- the second electrode of the storage capacitor being connected via the resistor to the line.
- the object of the invention is achieved in a memory configuration composed of a plurality of resistive ferroelectric memory cells of the type mentioned above in that the other electrode of the storage capacitor is connected via a resistor to a line which is supplied with the cell plate voltage.
- the resistor has a first resistance value.
- the given zone of the first conductivity type and the semiconductor body form a pn-junction therebetween, and the pn-junction has a reverse resistance with a second resistance value substantially larger than the first resistance value.
- the resistor has a given resistance value
- the given resistance value is set such that memory read operations and memory write operations, in particular read operations from the resistive ferroelectric memory cells and write operations to the resistive ferroelectric memory cells, are substantially uninfluenced by the resistor.
- the resistor in this case is constructed in such a way that its resistance value is substantially lower than the resistance value of the reverse resistance or blocking resistance of the pn-junction between the first zone of the selection transistor and the semiconductor substrate, and in such a way that the read and write operation is influenced by this resistor only to an extremely small degree.
- the significant feature of the invention is therefore that the end of the resistor which faces away from the first zone of the selection transistor is connected to the line supplied with the cell plate voltage.
- This line can preferably be a highly doped zone of the first conductivity type in the surface region of the semiconductor element.
- the resistor there are various possible ways of implementing the resistor: It is, for example, expedient to provide the resistor through the use of a suitable doping underneath the insulating layer, the so-called thick oxide, in the semiconductor element in the region between the first zone of the selection transistor and the line which is preferably formed from a highly doped zone of the first conductivity type and is supplied with the cell plate voltage.
- the resistor is a doped layer provided in the semiconductor body; and an insulating layer is disposed above the doped layer.
- a MOS transistor for the resistor, a reference voltage being applied to the gate of the MOS transistor in such a way that the resistance with the desired properties, for example in the subthreshold current range, is obtained via the channel of the MOS transistor.
- a MOS transistor has a gate to be supplied with an adjustable reference voltage, and the resistor is implemented by the MOS transistor.
- the resistor is formed by the channel region of the MOS transistor.
- the resistance value of the resistor is set by changing the adjustable reference voltage.
- this gate voltage can be set to a value such that the individual electrodes of the storage capacitors, the so-called capacitance nodes, in the memory cells are quickly adjusted to the cell plate voltage.
- the memory configuration according to the invention is a very simple configuration.
- a normal word line decoder can be used with it.
- the capacitance of the word line is not increased either.
- the memory cells of the memory configuration according to the invention require no more space than the cell space of a standard memory cell.
- FIG. 1 is a circuit diagram of a memory cell field of the memory configuration according to the invention.
- FIG. 2 is a schematic sectional view of a first exemplary embodiment of the memory configuration according to the invention.
- FIG. 3 is a schematic plan view of the memory configuration according to FIG. 2;
- FIG. 4 is a schematic sectional view of a second exemplary embodiment of the memory configuration according to the invention.
- FIG. 5 is a schematic plan view of the memory configuration according to FIG. 4;
- FIG. 7 is a schematic plan view of the memory configuration of FIG. 6.
- a fixed cell plate voltage is supplied to one of the electrodes of the storage capacitors Cferro.
- the fixed cell plate voltage is supplied in each case from, for example, a resistor R and a line L formed of a highly doped zone of the first conductivity type in the semiconductor element.
- This highly doped zone can be, in particular, an n ⁇ -type conductive strip-shaped zone.
- the resistor R which is connected between the storage capacitors Cferro and the line L which is supplied with the cell plate voltage VPLATE, must be constructed in such a way that
- the significant feature of the invention is that the terminal of the resistor R which is opposite the ferroelectric storage capacitor Cferro is held at the cell plate voltage VPLATE with the line L, with the result that when the selection transistor T is switched off virtually the same voltage is present at the ferroelectric storage capacitor Cferro, as a result of which a reprogramming of the ferroelectric storage capacitor Cferro is ruled out.
- FIG. 2 shows an n + -type conductive drain zone 1 and an n ⁇ -type conductive source zone 2 in the surface region of a p-type conductive semiconductor body, a word line WL being provided above the channel region between the drain zone 1 and the source zone 2 .
- This word line WL is embedded in an insulating layer composed of, for example, silicon dioxide and/or silicon nitride.
- the drain zone 1 is connected to an electrode SN of a ferroelectric storage capacitor via a plug 3 composed of, for example, polycrystalline silicon, the dielectric of the ferroelectric storage capacitor isolating the electrode SN from a common electrode PL to which the cell plate voltage VPLATE is connected.
- the individual electrodes PL are connected to one another, as is indicated by dotted lines in FIG. 2.
- the source zone 2 is connected via a plug 4 to a bit line AL-BL which is preferably composed of aluminum.
- This plug 4 is, of course, electrically isolated from the electrodes PL.
- Suitable doping concentrations for the resistor R are in the order of magnitude of the substrate doping. To increase the resistance in comparison with the substrate resistance, the doping concentration is less than the substrate doping concentration, and to reduce the resistance the doping concentration is greater than that of the substrate doping.
- FIGS. 4 and 5 show a second exemplary embodiment of the invention, while FIGS. 6 and 7 illustrate a refined embodiment of this exemplary embodiment.
- FIGS. 4 to 7 the same reference symbols as in FIGS. 2 and 3 are used for components which correspond to one another.
- the resistor R is implemented through the use of a MOS transistor 6 to whose gate 7 a gate voltage VR is connected, the gate voltage VR being set in such a way that the resistance R with the desired properties is obtained through the use of the channel of the MOS transistor 6 .
- FIGS. 6 and 7 show a refined embodiment of the exemplary embodiment in FIGS. 4 and 5.
- the resistor R is also implemented through the use of the MOS transistor 6 to which a suitable gate voltage VR is supplied, while the cell plate voltage VPLATE is applied via the n + -type conductive, highly doped zone 5 .
- aggressive layout which permits a particularly compact configuration of the memory configuration and which does not require any additional process steps.
Abstract
Description
- This application is a continuation of copending International Application No. PCT/DE99/00920, filed Mar. 25, 1999, which designated the United States.
- The invention relates to a memory configuration which is formed of a plurality of resistive ferroelectric memory cells. Each of the memory cells is formed of a selection transistor and a storage capacitor. One electrode of the storage capacitor is connected to a fixed cell plate voltage and the other electrode of the storage capacitor is connected to a zone of the storage capacitor that has a first conductivity type. The selection transistor and the storage capacitor are provided in or on a semiconductor substrate of a second conductivity type opposite the first conductivity type.
- Ferroelectric memory configurations in which the cell plate voltage is permanently set to half the supply voltage (Vcc/2) of the memory configuration are characterized by rapid memory operations. However, in these memory configurations, there is the problem of a possible loss of the data stored in the storage capacitors. Because the cell nodes at the storage capacitors are floating as long as the selection transistors are switched off and these cell nodes form parasitic pn-junctions to the semiconductor substrate, unavoidable leakage currents via the pn-junctions cause the cell node voltage to drop to a ground voltage Vss. The other nodes of the ferroelectric storage capacitors remain here at the fixed cell plate voltage Vcc/2. As a result, the contents of the ferroelectric storage capacitors can be corrupted by reprogramming.
- In order to avoid this data loss, in a way similar to DRAMs (Dynamic Random Access Memory Cells) , the memory cells are refreshed before their contents are destroyed. The refresh is carried out by the bit lines of the memory configuration being precharged to half the supply voltage Vcc/2, and the cell nodes being also charged to half the supply voltage Vcc/2 by activating the word lines, with the result that 0 V drops across the storage capacitors.
- Such a refresh is complicated and requires additional operations which should be avoided if possible.
- It is accordingly an object of the invention to provide a memory configuration having a plurality of resistive ferroelectric memory cells which overcomes the above-mentioned disadvantages of the heretofore-known memory configurations of this general type and which is configured in such a way that a leakage current at the cell node can no longer cause a reprogramming of the memory cell, with the result that a refresh of the memory cell can be dispensed with.
- With the foregoing and other objects in view there is provided, in accordance with the invention, a memory configuration, including:
- a plurality of resistive ferroelectric memory cells, each of the resistive ferroelectric memory cells including a selection transistor and a storage capacitor;
- the selection transistor having a given zone of a first conductivity type;
- the storage capacitor having a first electrode and a second electrode, the first electrode being supplied with a fixed cell plate voltage, the second electrode being connected to the given zone of the first conductivity type;
- a semiconductor body of a second conductivity type opposite the first conductivity type;
- the selection transistor and the storage capacitor respectively being provided in or on the semiconductor body;
- a resistor;
- a line formed by a highly doped zone of the first conductivity type, the line being supplied with the cell plate voltage; and
- the second electrode of the storage capacitor being connected via the resistor to the line.
- In other words, the object of the invention is achieved in a memory configuration composed of a plurality of resistive ferroelectric memory cells of the type mentioned above in that the other electrode of the storage capacitor is connected via a resistor to a line which is supplied with the cell plate voltage.
- According to another feature of the invention, the resistor has a first resistance value. The given zone of the first conductivity type and the semiconductor body form a pn-junction therebetween, and the pn-junction has a reverse resistance with a second resistance value substantially larger than the first resistance value.
- According to yet another feature of the invention, the resistor has a given resistance value, the given resistance value is set such that memory read operations and memory write operations, in particular read operations from the resistive ferroelectric memory cells and write operations to the resistive ferroelectric memory cells, are substantially uninfluenced by the resistor.
- The resistor in this case is constructed in such a way that its resistance value is substantially lower than the resistance value of the reverse resistance or blocking resistance of the pn-junction between the first zone of the selection transistor and the semiconductor substrate, and in such a way that the read and write operation is influenced by this resistor only to an extremely small degree.
- This ensures that in the memory configuration according to the invention the resistance causes virtually no disruption to the read and write operation and nevertheless the leakage current of the parasitic pn-junction to the semiconductor substrate is compensated by this resistance and the voltage present on each side of the ferroelectric storage capacitor is approximately the cell plate voltage. Undesired reprogramming of the storage capacitor can thus no longer occur.
- The significant feature of the invention is therefore that the end of the resistor which faces away from the first zone of the selection transistor is connected to the line supplied with the cell plate voltage. This line can preferably be a highly doped zone of the first conductivity type in the surface region of the semiconductor element.
- There are various possible ways of implementing the resistor: It is, for example, expedient to provide the resistor through the use of a suitable doping underneath the insulating layer, the so-called thick oxide, in the semiconductor element in the region between the first zone of the selection transistor and the line which is preferably formed from a highly doped zone of the first conductivity type and is supplied with the cell plate voltage. Therfore, according, a preferred feature of the invention, the resistor is a doped layer provided in the semiconductor body; and an insulating layer is disposed above the doped layer.
- However, it is also possible to use a MOS transistor for the resistor, a reference voltage being applied to the gate of the MOS transistor in such a way that the resistance with the desired properties, for example in the subthreshold current range, is obtained via the channel of the MOS transistor. Thus, according to a preferred feature of the invention, a MOS transistor has a gate to be supplied with an adjustable reference voltage, and the resistor is implemented by the MOS transistor. In particular, the resistor is formed by the channel region of the MOS transistor.
- According to a further feature of the invention, the resistance value of the resistor is set by changing the adjustable reference voltage.
- In addition to a constant gate voltage at the gate of the MOS transistor, after each read and write operation and when the supply voltage at the memory configuration is switched on and off, this gate voltage can be set to a value such that the individual electrodes of the storage capacitors, the so-called capacitance nodes, in the memory cells are quickly adjusted to the cell plate voltage.
- With such a procedure it is advantageous that the capacitance nodes are adjusted to the cell plate voltage immediately after the respective operation. In this process, it is possible to select all the selection transistors, for example when the memory configuration is switched on and off, or else also to select just the selection transistor which is associated with the respective word line and bit line, with the word or bit line decoder using the voltage applied to the gate of the MOS transistor.
- In the memory configuration according to the invention, unintended reprogramming occurring as a result of the leakage current of the parasitic pn-junction to the semiconductor substrate and when the memory configuration is switched on and off is not possible. In the same way, when the supply voltage is switched off, unintended reprogramming cannot take place either.
- In addition, the memory configuration according to the invention is a very simple configuration. In particular, a normal word line decoder can be used with it. The capacitance of the word line is not increased either. There is no need for a plug between the resistor, which is preferably implemented through the use of a doping layer under an insulating layer in the semiconductor element, and the storage capacitor electrode which is supplied with the fixed cell plate voltage, which means that the requirements made of the manufacturing steps are reduced and less space is needed because a contact hole specifically for the plug is not necessary. This means that the memory cells of the memory configuration according to the invention require no more space than the cell space of a standard memory cell. Other features which are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in a memory configuration composed of a plurality of resistive ferroelectric memory cells, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
- FIG. 1 is a circuit diagram of a memory cell field of the memory configuration according to the invention;
- FIG. 2 is a schematic sectional view of a first exemplary embodiment of the memory configuration according to the invention;
- FIG. 3 is a schematic plan view of the memory configuration according to FIG. 2;
- FIG. 4 is a schematic sectional view of a second exemplary embodiment of the memory configuration according to the invention;
- FIG. 5 is a schematic plan view of the memory configuration according to FIG. 4;
- FIG. 6 is a schematic sectional view of a modified embodiment of the memory configuration according to FIG. 4; and
- FIG. 7 is a schematic plan view of the memory configuration of FIG. 6.
- Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, there is shown a memory cell field in a folded bit line architecture with bit lines BLO, bBLO, BL1 and bBL1 having capacitors CB and with word lines WLO, WL1, WL2 and WL3, for single-transistor and single-capacitor (1T1C) memory cells composed of selection transistors T and ferroelectric storage capacitors Cferro.
- A fixed cell plate voltage is supplied to one of the electrodes of the storage capacitors Cferro. According to the invention, the fixed cell plate voltage is supplied in each case from, for example, a resistor R and a line L formed of a highly doped zone of the first conductivity type in the semiconductor element. This highly doped zone can be, in particular, an n−-type conductive strip-shaped zone.
- The resistor R, which is connected between the storage capacitors Cferro and the line L which is supplied with the cell plate voltage VPLATE, must be constructed in such a way that
- (a) the resistance value of this resistor R is substantially lower than the resistance value of the reverse resistance of the pn-junction between the first zone of the selection transistor and the semiconductor substrate, and
- (b) the read and write operation is influenced by the resistor R only to an extremely small degree.
- If these conditions for the resistor R are met, it is ensured that the read and write operation in the individual memory cells remains virtually unaffected by the resistor R, and the leakage current of the parasitic pn-junction to the semiconductor substrate is compensated by the current flowing through the resistor R. As a result, the voltage present on each side of the ferroelectric storage capacitors, that is to say at the two capacitance nodes, is approximately the cell plate voltage. Undesired reprogramming of the storage capacitors can then no longer occur.
- The significant feature of the invention is that the terminal of the resistor R which is opposite the ferroelectric storage capacitor Cferro is held at the cell plate voltage VPLATE with the line L, with the result that when the selection transistor T is switched off virtually the same voltage is present at the ferroelectric storage capacitor Cferro, as a result of which a reprogramming of the ferroelectric storage capacitor Cferro is ruled out.
- There are various ways of implementing the resistor R, and these will be explained in more detail below with reference to FIGS.2 to 7. Basically, there is the possibility of constructing the resistor R through the use of suitable doping under the insulating layer next to the selection transistor (cf. FIGS. 2 and 3) or else of providing a MOS transistor for this resistor, which MOS transistor is set through the use of its gate voltage VR in such a way that a resistance with the desired properties is obtained via the channel of this MOS transistor (cf. FIGS. 4 to 7).
- FIG. 2 shows an n+-type
conductive drain zone 1 and an n−-typeconductive source zone 2 in the surface region of a p-type conductive semiconductor body, a word line WL being provided above the channel region between thedrain zone 1 and thesource zone 2. This word line WL is embedded in an insulating layer composed of, for example, silicon dioxide and/or silicon nitride. Thedrain zone 1 is connected to an electrode SN of a ferroelectric storage capacitor via aplug 3 composed of, for example, polycrystalline silicon, the dielectric of the ferroelectric storage capacitor isolating the electrode SN from a common electrode PL to which the cell plate voltage VPLATE is connected. The individual electrodes PL are connected to one another, as is indicated by dotted lines in FIG. 2. - The
source zone 2 is connected via a plug 4 to a bit line AL-BL which is preferably composed of aluminum. This plug 4 is, of course, electrically isolated from the electrodes PL. - The resistor R is formed by suitable doping underneath the insulating layer or a thick oxide FOX between the
drain zone 1 and a highly doped, n+-type conductive zone 5 via which the cell plate voltage VPLATE is supplied to the terminal of the resistor R which is opposite thedrain zone 1. - Suitable doping concentrations for the resistor R are in the order of magnitude of the substrate doping. To increase the resistance in comparison with the substrate resistance, the doping concentration is less than the substrate doping concentration, and to reduce the resistance the doping concentration is greater than that of the substrate doping.
- FIGS. 4 and 5 show a second exemplary embodiment of the invention, while FIGS. 6 and 7 illustrate a refined embodiment of this exemplary embodiment. In FIGS.4 to 7, the same reference symbols as in FIGS. 2 and 3 are used for components which correspond to one another.
- In the exemplary embodiment in FIGS. 4 and 5, the resistor R is implemented through the use of a
MOS transistor 6 to whose gate 7 a gate voltage VR is connected, the gate voltage VR being set in such a way that the resistance R with the desired properties is obtained through the use of the channel of theMOS transistor 6. - FIGS. 6 and 7 show a refined embodiment of the exemplary embodiment in FIGS. 4 and 5. Here, the resistor R is also implemented through the use of the
MOS transistor 6 to which a suitable gate voltage VR is supplied, while the cell plate voltage VPLATE is applied via the n+-type conductive, highly dopedzone 5. In contrast to the variant in FIGS. 4 and 5, use is made here of a so-called “aggressive layout” which permits a particularly compact configuration of the memory configuration and which does not require any additional process steps.
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19832995A DE19832995C1 (en) | 1998-07-22 | 1998-07-22 | Memory device using resistive ferroelectric memory cells |
DE19832995.4 | 1998-07-22 | ||
PCT/DE1999/000920 WO2000005721A1 (en) | 1998-07-22 | 1999-03-25 | Storage assembly consisting of resistive ferroelectric storage cells |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/000920 Continuation WO2000005721A1 (en) | 1998-07-22 | 1999-03-25 | Storage assembly consisting of resistive ferroelectric storage cells |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020018356A1 true US20020018356A1 (en) | 2002-02-14 |
US6404668B2 US6404668B2 (en) | 2002-06-11 |
Family
ID=7874933
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/767,807 Expired - Fee Related US6404668B2 (en) | 1998-07-22 | 2001-01-22 | Memory configuration including a plurality of resistive ferroelectric memory cells |
Country Status (8)
Country | Link |
---|---|
US (1) | US6404668B2 (en) |
EP (1) | EP1097458B1 (en) |
JP (1) | JP3634751B2 (en) |
KR (1) | KR100399265B1 (en) |
CN (1) | CN1160734C (en) |
DE (2) | DE19832995C1 (en) |
TW (1) | TW436860B (en) |
WO (1) | WO2000005721A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8599598B1 (en) * | 2008-08-06 | 2013-12-03 | Altera Corporation | 3T device based memory circuits and arrays |
US20140092670A1 (en) * | 2012-09-28 | 2014-04-03 | Imec | Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof |
US20160351260A1 (en) * | 2014-01-31 | 2016-12-01 | Hewlett Packard Enterprise Development Lp | Memory cell having resistive and capacitive storage elements |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040119105A1 (en) * | 2002-12-18 | 2004-06-24 | Wilson Dennis Robert | Ferroelectric memory |
US6819583B2 (en) * | 2003-01-15 | 2004-11-16 | Sharp Laboratories Of America, Inc. | Ferroelectric resistor non-volatile memory array |
JP4433918B2 (en) * | 2004-07-15 | 2010-03-17 | コニカミノルタエムジー株式会社 | Image forming method |
JP2006099866A (en) * | 2004-09-29 | 2006-04-13 | Sony Corp | Storage device and semiconductor device |
KR100651728B1 (en) * | 2004-11-10 | 2006-12-06 | 한국전자통신연구원 | Compounds having anchoring group and electronic device including the same and methods for producing the same |
US7180141B2 (en) * | 2004-12-03 | 2007-02-20 | Texas Instruments Incorporated | Ferroelectric capacitor with parallel resistance for ferroelectric memory |
JP4475174B2 (en) * | 2005-06-09 | 2010-06-09 | ソニー株式会社 | Storage device |
CN101409104B (en) * | 2008-07-24 | 2011-05-04 | 复旦大学 | Novel non-volatilization dynamic memory |
US9425995B2 (en) | 2012-04-06 | 2016-08-23 | Ajoho Enterprise Co., Ltd. | Impedance matching device-integrated network signal processing circuit |
US9161435B2 (en) * | 2012-07-09 | 2015-10-13 | Ajoho Enterprise Co., Ltd. | Network signal processing circuit assembly |
US10581423B1 (en) * | 2018-08-17 | 2020-03-03 | Analog Devices Global Unlimited Company | Fault tolerant low leakage switch |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6117127A (en) * | 1984-07-04 | 1986-01-25 | Hitachi Ltd | Driving method of optical switch element |
JPH0693166B2 (en) * | 1984-09-05 | 1994-11-16 | 株式会社日立製作所 | Liquid crystal element |
US5038323A (en) * | 1990-03-06 | 1991-08-06 | The United States Of America As Represented By The Secretary Of The Navy | Non-volatile memory cell with ferroelectric capacitor having logically inactive electrode |
KR950009813B1 (en) * | 1993-01-27 | 1995-08-28 | 삼성전자주식회사 | Semiconductor device and manufacturing method thereof |
JP3020422B2 (en) * | 1994-12-22 | 2000-03-15 | 松下電器産業株式会社 | Semiconductor storage device |
US5598366A (en) * | 1995-08-16 | 1997-01-28 | Ramtron International Corporation | Ferroelectric nonvolatile random access memory utilizing self-bootstrapping plate line segment drivers |
US5959878A (en) * | 1997-09-15 | 1999-09-28 | Celis Semiconductor Corporation | Ferroelectric memory cell with shunted ferroelectric capacitor and method of making same |
US5898609A (en) * | 1998-05-29 | 1999-04-27 | Samsung Electronics Co., Ltd. | Ferroelectric memory having circuit for discharging pyroelectric charges |
KR100298439B1 (en) * | 1998-06-30 | 2001-08-07 | 김영환 | Nonvolatile ferroelectric memory |
-
1998
- 1998-07-22 DE DE19832995A patent/DE19832995C1/en not_active Expired - Fee Related
-
1999
- 1999-03-25 CN CNB998090980A patent/CN1160734C/en not_active Expired - Fee Related
- 1999-03-25 KR KR10-2001-7000959A patent/KR100399265B1/en not_active IP Right Cessation
- 1999-03-25 DE DE59906886T patent/DE59906886D1/en not_active Expired - Fee Related
- 1999-03-25 EP EP99924695A patent/EP1097458B1/en not_active Expired - Lifetime
- 1999-03-25 JP JP2000561620A patent/JP3634751B2/en not_active Expired - Fee Related
- 1999-03-25 WO PCT/DE1999/000920 patent/WO2000005721A1/en active IP Right Grant
- 1999-06-15 TW TW088109986A patent/TW436860B/en not_active IP Right Cessation
-
2001
- 2001-01-22 US US09/767,807 patent/US6404668B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8599598B1 (en) * | 2008-08-06 | 2013-12-03 | Altera Corporation | 3T device based memory circuits and arrays |
US9111641B1 (en) | 2008-08-06 | 2015-08-18 | Altera Corporation | Memory circuit including memory devices, a freeze circuit and a test switch |
US20140092670A1 (en) * | 2012-09-28 | 2014-04-03 | Imec | Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof |
US9159415B2 (en) * | 2012-09-28 | 2015-10-13 | Imec | Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof |
US20160351260A1 (en) * | 2014-01-31 | 2016-12-01 | Hewlett Packard Enterprise Development Lp | Memory cell having resistive and capacitive storage elements |
US9911495B2 (en) * | 2014-01-31 | 2018-03-06 | Hewlett Packard Enterprise Development Lp | Memory cell having resistive and capacitive storage elements |
Also Published As
Publication number | Publication date |
---|---|
TW436860B (en) | 2001-05-28 |
KR100399265B1 (en) | 2003-09-26 |
US6404668B2 (en) | 2002-06-11 |
DE59906886D1 (en) | 2003-10-09 |
WO2000005721A1 (en) | 2000-02-03 |
CN1160734C (en) | 2004-08-04 |
KR20010100773A (en) | 2001-11-14 |
CN1311892A (en) | 2001-09-05 |
EP1097458B1 (en) | 2003-09-03 |
JP2002521780A (en) | 2002-07-16 |
JP3634751B2 (en) | 2005-03-30 |
DE19832995C1 (en) | 1999-11-04 |
EP1097458A1 (en) | 2001-05-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6421269B1 (en) | Low-leakage MOS planar capacitors for use within DRAM storage cells | |
US5689458A (en) | Semiconductor memory device having negative resistance element operated stably with single low power source | |
US6781867B2 (en) | Embedded ROM device using substrate leakage | |
US20060289919A1 (en) | Two-sided surround access transistor for a 4.5F2 DRAM cell | |
US6404668B2 (en) | Memory configuration including a plurality of resistive ferroelectric memory cells | |
US7265412B2 (en) | Semiconductor memory device having memory cells requiring no refresh operation | |
KR100554211B1 (en) | Ferroelectric storage assembly | |
JP3575675B2 (en) | Capacitor loaded memory cell | |
US6646907B2 (en) | Semiconductor memory device | |
US4920513A (en) | Semiconductor memory device using diode-capacitor combination | |
US6627935B2 (en) | Resistive ferroelectric memory cell | |
US6452830B2 (en) | Memory configuration including a plurality of resistive ferroelectric memory cells | |
US6661700B2 (en) | Semiconductor memory device | |
US4597059A (en) | Dynamic semiconductor memory device | |
EP0306198A2 (en) | An active dynamic memory cell | |
KR20030053213A (en) | Semiconductor memory cell and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SIEMENS AKTIENGESELLSCHAFT, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOWARIK, OSKAR;HOFFMANN, KURT;REEL/FRAME:011949/0576;SIGNING DATES FROM 20010316 TO 20010317 |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SIEMENS AKTIENGESELLSCHAFT;REEL/FRAME:024114/0059 Effective date: 19990331 |
|
AS | Assignment |
Owner name: QIMONDA AG,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:024218/0001 Effective date: 20060425 |
|
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Expired due to failure to pay maintenance fee |
Effective date: 20100611 |