US20020016038A1 - Method for manufacturing a floating gate in a flash memory device - Google Patents

Method for manufacturing a floating gate in a flash memory device Download PDF

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US20020016038A1
US20020016038A1 US09/879,645 US87964501A US2002016038A1 US 20020016038 A1 US20020016038 A1 US 20020016038A1 US 87964501 A US87964501 A US 87964501A US 2002016038 A1 US2002016038 A1 US 2002016038A1
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film
psg
flash memory
memory device
floating gate
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Sun Jung
Sang Lee
Jum Kim
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SK Hynix Inc
Intellectual Discovery Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • a method of manufacturing a floating gate in a flash memory device is disclosed. More particularly, a method of manufacturing a floating gate in a flash memory device, which can minimize the size of the device without damaging a polysilicon film and a field oxide film is disclosed.
  • the size of a flash memory device in which a floating gate and a control gate are stacked to form a word line, is determined by the distance between the floating gates formed to be overlapped with a given region on a field oxide film. That is, in order to reduce the size of the device, the distance between the floating gates must be reduced. Though various methods have been proposed, they cause many problems when being applied in a mass production process, and, as a result most of which have not implemented.
  • a tunnel oxide film, a polysilicon film and a first nitride film are sequentially formed on a semiconductor substrate on a given region of which a field oxide film is formed.
  • the first nitride film is patterned by lithography process and etching process using a mask for floating gate.
  • the first nitride film is patterned to be overlapped with a given region of the field oxide film.
  • a spacer is formed at the sidewall of the first nitride film by means of a second nitride film.
  • the polysilicon film and the tunnel oxide film are etched using the nitride film pattern in which the spacer is formed as a mask.
  • the nitride pattern is removed to form a floating gate.
  • the floating gate is formed by the above process, the nitride film and the nitride spacer are removed by means of wet etch process using H 3 PO 4 .
  • the underlying polysilicon film is damaged by the H 2 PO 4 l , which may critically affect the operation of the device.
  • a method of manufacturing a floating gate in a flash memory device which can minimize the distance between floating gates using a relatively large design rule is disclosed.
  • a method of manufacturing a floating gate in a flash memory device which can minimize the distance between floating gates without damaging a polysilicon film and a field oxide film is disclosed.
  • the disclosed method is characterized in that it comprises the steps of forming a tunnel oxide film and a polysilicon film on a semiconductor substrate on a portion of which a field oxide film is formed; forming a first PSG film on the polysilicon film and then patterning the first PSG film; forming a second PSG film on the entire structure and then blanket-etching the second PSG film, thus forming a spacer at the sidewall of the first PSG film pattern; etching the polysilicon film and the tunnel oxide film by means of etching process, using the first PSG film pattern at which the spacer is formed as a mask; and removing the first PSG film pattern and the spacer.
  • FIGS. 1A to 1 C are cross-sectional views illustrating a method of manufacturing a floating gate in a flash memory device according to one disclosed method.
  • FIG. 2 is a graph showing etch ratio depending on the concentration of an oxide film and BOE.
  • FIGS. 1A to 1 C are cross-sectional views for explaining a method of manufacturing a floating gate in a flash memory device.
  • a field oxide film 12 is formed on a given region of a semiconductor substrate 11 .
  • a tunnel oxide film 13 and a polysilicon film 14 are formed on the entire structure.
  • a first PSG film 15 is formed on the polysilicon film 14 .
  • the first PSG film 15 is patterned by means of lithography and etching process using a mask for floating gate.
  • the first PSG film 15 is formed to be overlapped with a given region of the field oxide film 12 .
  • the polysilicon film 14 is formed with a thickness ranging from about 400 ⁇ to about 1000 ⁇ and the first PSG film 15 is formed with a thickness ranging from about 400 ⁇ to about 2500 ⁇ .
  • a second PSG film (not specifically shown in FIG. 1B, see the spacer 16 ) is formed with a thickness ranging from about 400 ⁇ to about 2500 ⁇ on the entire structure including the patterned first PSG film 15 .
  • the second PSG film is etched by means of blanket-etching process to form a spacer 16 at the sidewall of the first PSG film 15 .
  • the polysilicon 14 and the tunnel oxide film 13 are etched using the first PSG film 15 at which the spacer 16 is formed as a mask.
  • the spacer 16 and the first PSG film 15 are removed to form a floating gate.
  • the spacer 16 and the first PSG film 15 both of which are formed by the second PSG film are removed by HF or BOE, wherein it is preferably removed by solution with 50:1 HF or 9:1 BOE.
  • Table 1 and Table 2 show etch ratio depending on etch solutions for various films and FIG. 2 is a graph showing etch ratio depending on the concentration of the oxide film and BOE.
  • the distance between the floating gates can be minimized without damaging a polysilicon film and a field oxide film used in a floating gate. Therefore, it can reduce the size of a device and can thus improve reliability of the device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

There is disclosed a method of manufacturing a floating gate in a flash memory device. In order to minimize the distance between floating gates, the method includes patterning a polysilicon film using a first PSG pattern in which a second PSG spacer is formed on and at the sidewall of the polysilicon film, and removing the first PSG film pattern and the second PSG film spacer using 50:1 HF or 9:1 BOE. Therefore, it can minimize the size of the device without damaging a polysilicon film and a field oxide.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • A method of manufacturing a floating gate in a flash memory device is disclosed. More particularly, a method of manufacturing a floating gate in a flash memory device, which can minimize the size of the device without damaging a polysilicon film and a field oxide film is disclosed. [0002]
  • 2. Description of the Prior Art [0003]
  • The size of a flash memory device, in which a floating gate and a control gate are stacked to form a word line, is determined by the distance between the floating gates formed to be overlapped with a given region on a field oxide film. That is, in order to reduce the size of the device, the distance between the floating gates must be reduced. Though various methods have been proposed, they cause many problems when being applied in a mass production process, and, as a result most of which have not implemented. [0004]
  • As one example, a method by will be explained by which the distance between the floating gates is made less 0.15 μm using a relatively large design rule ranging from 0.35 μm to about 0.25 μm without additional equipment. [0005]
  • A tunnel oxide film, a polysilicon film and a first nitride film are sequentially formed on a semiconductor substrate on a given region of which a field oxide film is formed. Next, the first nitride film is patterned by lithography process and etching process using a mask for floating gate. The first nitride film is patterned to be overlapped with a given region of the field oxide film. Then, a spacer is formed at the sidewall of the first nitride film by means of a second nitride film. Thereafter, the polysilicon film and the tunnel oxide film are etched using the nitride film pattern in which the spacer is formed as a mask. Thus, the nitride pattern is removed to form a floating gate. [0006]
  • If the floating gate is formed by the above process, the nitride film and the nitride spacer are removed by means of wet etch process using H[0007] 3PO4. However, the underlying polysilicon film is damaged by the H2PO4l , which may critically affect the operation of the device.
  • In order to solve this problem, a CVD oxide film is used instead of the nitride film and a CVD oxide film wet etch or dry etch process using BOE or HF is employed. However, another problem is associated with this technique in that the field oxide film is exposed by the etching process is consequently etched. [0008]
    • SUMMARY OF THE DISCLOSURE
  • A method of manufacturing a floating gate in a flash memory device, which can minimize the distance between floating gates using a relatively large design rule is disclosed. [0009]
  • Further, a method of manufacturing a floating gate in a flash memory device, which can minimize the distance between floating gates without damaging a polysilicon film and a field oxide film is disclosed. [0010]
  • The disclosed method is characterized in that it comprises the steps of forming a tunnel oxide film and a polysilicon film on a semiconductor substrate on a portion of which a field oxide film is formed; forming a first PSG film on the polysilicon film and then patterning the first PSG film; forming a second PSG film on the entire structure and then blanket-etching the second PSG film, thus forming a spacer at the sidewall of the first PSG film pattern; etching the polysilicon film and the tunnel oxide film by means of etching process, using the first PSG film pattern at which the spacer is formed as a mask; and removing the first PSG film pattern and the spacer.[0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The aforementioned aspects and other features of the disclosed method will be explained in the following description, taken in conjunction with the accompanying drawings, wherein: [0012]
  • FIGS. 1A to [0013] 1C are cross-sectional views illustrating a method of manufacturing a floating gate in a flash memory device according to one disclosed method; and
  • FIG. 2 is a graph showing etch ratio depending on the concentration of an oxide film and BOE.[0014]
    • DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS
  • The disclosed method will be described in detail by way of a preferred embodiment with reference to accompanying drawings. [0015]
  • FIGS. 1A to [0016] 1C are cross-sectional views for explaining a method of manufacturing a floating gate in a flash memory device. Referring now to FIG. 1A, a field oxide film 12 is formed on a given region of a semiconductor substrate 11. Then, a tunnel oxide film 13 and a polysilicon film 14 are formed on the entire structure. Next, a first PSG film 15 is formed on the polysilicon film 14. Then, the first PSG film 15 is patterned by means of lithography and etching process using a mask for floating gate. The first PSG film 15 is formed to be overlapped with a given region of the field oxide film 12. At this time, the polysilicon film 14 is formed with a thickness ranging from about 400 Å to about 1000 Å and the first PSG film 15 is formed with a thickness ranging from about 400 Å to about 2500 Å.
  • Referring now to FIG. 1B, a second PSG film (not specifically shown in FIG. 1B, see the spacer [0017] 16) is formed with a thickness ranging from about 400 Å to about 2500 Å on the entire structure including the patterned first PSG film 15. The second PSG film is etched by means of blanket-etching process to form a spacer 16 at the sidewall of the first PSG film 15. The polysilicon 14 and the tunnel oxide film 13 are etched using the first PSG film 15 at which the spacer 16 is formed as a mask.
  • Referring now to FIG. 1C, the spacer [0018] 16 and the first PSG film 15 are removed to form a floating gate. At this time, the spacer 16 and the first PSG film 15 both of which are formed by the second PSG film, are removed by HF or BOE, wherein it is preferably removed by solution with 50:1 HF or 9:1 BOE.
  • Table 1 and Table 2 show etch ratio depending on etch solutions for various films and FIG. 2 is a graph showing etch ratio depending on the concentration of the oxide film and BOE. [0019]
    TABLE 1
    ITEM 50 HF 100 HF
    THERMAL FOX 1.0 0.6 100″
    SAC
    LTO AS DEP. 8.0 4.1
    ANNEALED
    MTO AS DEP. 2.5 1.2 780/1.2 torr
    ANNEALED 2.1 N20:SiH4 = 4000:80 sccm
    HTO AS DEP. 2.9 0.5 850/0.8 torr
    ANNEALED 3.1 N20:DCS = 600:60 sccm
    TEOS PETEOS AS DEP. 2.5 1.8 100″
    ANNEALED
    LPTEOS AS DEP. 7.0 3.3 710/0.4 torr
    ANNEALED 3.6 100″ 1.2 100″ TEOS:02 = 120:5 sccm
    BPSG #166 AS DEP. 17.2 8.3 550/03 107 g/cm 2
    ANNEALED 8.3 4.1 TMB:TMP = 16:6 Mol %
    FTPS 8.1 4.2 850/30′ A & F
    #186 AS DEP. 22.4 9.6 550/03 107 g/cm 2
    ANNEALED 9.5 4.7 TMB:TMP = 18:6 Mol %
    FTPS 9.3 4.7 850/30′ A & F
    PSG 03 PSG AS DEP. 66.0 15.4 100″
    ANNEALED 58.4
    OXY PE OXY AS DEP. 1.4 0.5 100″
    NITRIDE ANNEALED
    PEMSOXY AS DEP. 13.9
    ANNEALED
    ANNEAL ENVIRONMENT 850/30′ 850/20′ (850/30′)
  • [0020]
    TABLE 2
    ITEM 9BOE 50BOE 100BOE 300BOE
    THERMAL
    FOX 14.8 3.1 1.5 0.2
    SAC
    LTO
    AS DEP. 52.6 6.6
    ANNEALED
    MTO
    AS DEP. 27.5 4.4 3.8 0.7
    ANNEALED 3.4
    HTO
    AS DEP. 33.4 5.2 5.1 1.2
    ANNEALED 5.0
    TEOS
    PETEOS
    AS DEP. 8.6 4.4
    ANNEALED
    LPTEOS
    AS DEP. 71.6 9.8
    ANNEALED 4.4 100″
    BPSG
    #166
    AS DEP. 7.5 1.5
    ANNEALED 3.8
    FTPS 3.8
    #186
    AS DEP. 7.3 1.5
    ANNEALED 3.9
    FTPS 3.8
    PSG
    O3 PSG
    AS DEP. 214.5 50″ 22.6  50″ 3.4
    ANNEALED 137.8 50″ 15.6  50″
    OXY NITRIDE
    PE OXY
    AS DEP. 30.2 50″ 1.8 0.7 50″
    ANNEALED
    PEMSOXY
    AS DEP. 29.0 50″ 5.8  50″ 1.3 50″
    ANNEALED
    ANNEAL 850/30″ 850/30″
    ENVIRONMENT
  • As shown in Tables 1 and 2, for example, in case of using 50:1 HF, a thermal oxide film is etched by 1 Å per second and the PSG film is etched by 11 Å per second. Therefore, the thermal oxide film and the PSG film has the etch ratio of 66:1, respectively. [0021]
  • Therefore, for example, when a PSG film having the thickness of 1000 Å is removed, the field oxide film is etched or damaged by 15.15 Å. [0022]
  • As mentioned above, according to the present invention, the distance between the floating gates can be minimized without damaging a polysilicon film and a field oxide film used in a floating gate. Therefore, it can reduce the size of a device and can thus improve reliability of the device. [0023]
  • The present invention has been described with reference to a particular embodiment in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof. [0024]
  • It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the present invention. [0025]

Claims (10)

What is claimed:
1. A method of manufacturing a floating gate in a flash memory device, comprising the steps of:
providing a semiconductor substrate that comprises a first portion that is covered with a field oxide film and a second portion that is not covered with the field oxide film;
forming a tunnel oxide film on the portion of the semiconductor substrate that is not covered with the field oxide film;
forming a polysilicon film on the tunnel oxide film and the field oxide film;
forming a first PSG film on the polysilicon film;
patterning the first PSG film to form a sidewall on the first PSG film;
forming a second PSG film on the entire structure;
blanket-etching the second PSG film, thus forming a spacer at the sidewall of the first PSG film;
etching said polysilicon film and said tunnel oxide film by means of etching process, using said first PSG film and the spacer as a mask; and
removing said first PSG film and the spacer.
2. The method of manufacturing a floating gate in a flash memory device according to claim 1, wherein the said polysilicon film is formed with a thickness ranging from about 400 Å to about 1000 Å.
3. The method of manufacturing a floating gate in a flash memory device according to claim 1, wherein said first PSG film is formed with a thickness ranging from about 400 Å to about 2500 Å.
4. The method of manufacturing a floating gate in a flash memory device according to claim 1, wherein said second PSG film is formed with thickness ranging from about 400 Å to about 2500 Å.
5. The method of manufacturing a floating gate in a flash memory device according to claim 1, wherein said first PSG film and said spacer are removed by 50:1 HF or 9:1 BOE.
6. A flash memory device made in accordance with the method of claim 1.
7. A flash memory device made in accordance with the method of claim 2.
8. A flash memory device made in accordance with the method of claim 3.
9. A flash memory device made in accordance with the method of claim 4.
10. A flash memory device made in accordance with the method of claim 5.
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Cited By (1)

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US10580783B2 (en) 2018-03-01 2020-03-03 Sandisk Technologies Llc Multi-tier three-dimensional memory device containing differential etch rate field oxides and method of making the same

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KR100355238B1 (en) * 2000-10-27 2002-10-11 삼성전자 주식회사 Method for fabricating cell of flash memory device
KR100885498B1 (en) 2002-12-31 2009-02-24 동부일렉트로닉스 주식회사 Method for forming a semiconductor device
KR100520684B1 (en) * 2003-11-19 2005-10-11 주식회사 하이닉스반도체 Method of manufacturing flash memory device
KR100514173B1 (en) * 2004-01-15 2005-09-09 삼성전자주식회사 method for manufacturing gate electrode of semiconductor device
KR100824633B1 (en) * 2006-09-06 2008-04-24 동부일렉트로닉스 주식회사 Flash memory device and manufacturing method thereof
KR100816727B1 (en) 2006-09-20 2008-03-27 주식회사 하이닉스반도체 Method for manufacturing flash memory device

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KR100239459B1 (en) * 1996-12-26 2000-01-15 김영환 Semiconductor memory device and manufacturing method thereof
KR100221619B1 (en) * 1996-12-28 1999-09-15 구본준 A fabrication method of flash memory cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10580783B2 (en) 2018-03-01 2020-03-03 Sandisk Technologies Llc Multi-tier three-dimensional memory device containing differential etch rate field oxides and method of making the same

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