US20010046155A1 - Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device - Google Patents
Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device Download PDFInfo
- Publication number
- US20010046155A1 US20010046155A1 US09/916,768 US91676801A US2001046155A1 US 20010046155 A1 US20010046155 A1 US 20010046155A1 US 91676801 A US91676801 A US 91676801A US 2001046155 A1 US2001046155 A1 US 2001046155A1
- Authority
- US
- United States
- Prior art keywords
- memory cell
- transistor
- semiconductor material
- type semiconductor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 83
- 239000003990 capacitor Substances 0.000 title claims description 43
- 238000000034 method Methods 0.000 title claims description 18
- 230000005669 field effect Effects 0.000 claims abstract description 47
- 238000004891 communication Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 34
- 230000006870 function Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000003213 activating effect Effects 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 3
- 238000010276 construction Methods 0.000 claims 1
- 238000012546 transfer Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
Definitions
- the present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuit memory devices.
- CMOS FETs Complimentary metal oxide semiconductor field effect transistors
- CMOS FETs Complimentary metal oxide semiconductor field effect transistors
- Threshold voltage variations of CMOS transistors are beginning to pose impractical limitations on CMOS devices as power supply voltages are reduced.
- a 0.4 V distribution in threshold voltages might be anticipated. With a one volt power supply, this distribution can cause large variations in the speed of a logic circuit, such as those used in integrated memory circuits. For example, a threshold voltage of 0.6 V is required in a DRAM memory cell access transistor to insure low sub-threshold voltage leakage currents. If a threshold voltage distribution of 0.4 volts is experienced, there will be instances where little or no excess voltage above threshold voltage is available. As such, data transfer from a memory cell via such a transistor will be very slow.
- CMOS access transistors do not function well at low voltages and require the use of higher than desirable power supply voltages, currently around two volts in 0.2 micron CMOS technology.
- CMOS technology Various techniques have been proposed to compensate for this in CMOS technology. For example, some form of transistor forward body bias, or specialized circuits to compensate for threshold voltage variations can be used.
- CMOS complementary metal oxide semiconductor
- a memory cell access device which uses a combination of bipolar junction and CMOS transistors as access devices to store and read data on a trench plate trench capacitor.
- one embodiment of the present invention provides a memory cell access device that has two access transistors.
- the first access transistor is an n-channel field effect transistor (FET) that is coupled between a trench plate trench capacitor and a data communication line.
- the second access transistor is an NPN bipolar junction transistor that is coupled between the trench plate trench capacitor and the data communication line.
- the n-channel access transistor and the NPN bipolar junction transistor are connected in parallel, and a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
- a low voltage memory cell access device fabricated as a vertical pillar structure.
- the memory cell access device includes a field effect transistor that is coupled between a trench plate trench capacitor and a data communication line.
- the memory cell access device also includes a bipolar junction transistor that is coupled between the memory cell and the data communication line.
- the field effect transistor and the bipolar junction transistor are connected in parallel, with a base connection of the bipolar junction transistor that is coupled to a body of the field effect transistor.
- a memory device having a low voltage supply comprises a plurality of memory cells, a plurality of data communication bit lines, and a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines.
- Each of the plurality of memory cell access devices comprises a field effect transistor and a bipolar junction transistor. The field effect transistor and the bipolar junction transistor are connected in parallel between a trench plate trench capacitor and a data communication bit line.
- a method of accessing a memory cell includes activating a field effect transistor coupled between a trench plate trench capacitor and a data communication line for writing data to the memory cell, and activating a bipolar junction transistor coupled between the trench plate trench capacitor and a data communication line for reading a charge stored on the memory cell.
- FIG. 1 is a block diagram of an embodiment of a memory device according to the teachings of the present invention.
- FIG. 2 is an embodiment of a portion of an array of memory cells according to the teachings of the present invention.
- FIG. 3A is a schematic diagram that illustrates an embodiment of a memory cell with a vertical access device according to the teachings of the present invention.
- FIG. 3B is a cross sectional view that illustrates an integrated circuit embodiment of the vertical access device of FIG. 3A.
- FIG. 3C is a cross sectional view that illustrates another integrated circuit embodiment of the vertical access device of FIG. 3A.
- wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention.
- substrate is understood to include semiconductor wafers.
- substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon.
- Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
- the term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense.
- the term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate.
- the term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
- a bipolar junction transistor structure can be used as a data read access device and a field effect transistor used as a data write access device, as described herein.
- DRAM dynamic random access memory
- Embodiments of an access device constructed according to the teachings of the present invention are also shown and described. It is understood, however, that these embodiments are provided by way of example and not by way of limitation.
- FIG. 1 is a simplified block diagram of an embodiment of a memory device incorporating access devices constructed according to the teachings of the present invention.
- Memory device 100 includes an array of memory cells 102 , address decoder 104 , row access circuitry 106 , column access circuitry 108 , control circuitry 110 , and Input/Output circuit (I/O) 112 .
- I/O Input/Output circuit
- each cell in array 102 includes an access device with a bipolar junction transistor coupled in parallel with a field effect transistor between a data communication or digit line and a trench plate trench capacitor.
- the access device is used to charge and discharge the trench plate trench capacitor to store and read data from the memory cell.
- the field effect transistor charges the capacitor.
- the bipolar junction transistor reads the charge stored on the capacitor by discharging the capacitor and providing the current to a current sense amplifier.
- the bipolar junction transistor typically conducts a higher current compared to its counterpart field effect transistor.
- the access device provides the advantage of increased speed in reading the data stored in the memory cell by allowing the capacitor to be discharged more quickly.
- Memory device 100 can be coupled to an external microprocessor 114 , or memory controller for memory accessing.
- Memory device 100 receives control signals from the microprocessor 114 , such as WE*, RAS* and CAS* signals.
- Memory device 100 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of FIG. 1 has been simplified to help focus on embodiments of the present invention.
- DRAM dynamic random access memory
- SGRAM synchronous DRAM commonly referred to as SGRAM, SDRAM, SDRAM II, and DDR SDRAM, as well as Synchlink or Rambus DRAMs.
- FIG. 2 an embodiment of a portion of array 102 is provided.
- the simplified schematic diagram illustrates a portion of a column of the array 102 .
- the column is generally defined by a pair of data communication or digit lines 120 and 122 .
- Access devices 124 are located along the digit lines for coupling trench plate trench capacitors 126 to a digit line.
- Access devices 124 include field effect transistor 123 in parallel with bipolar junction transistor 125 .
- the field effect transistors 123 are activated by a word line (W-WL) to write data to a trench plate trench capacitor, which defines a row of the memory array.
- the bipolar junction transistors 125 are activated by a word line (R-WL) to read data from a trench plate trench capacitor.
- Current sense amplifier 128 is provided to detect current signals provided to the digit lines by a bipolar junction transistor during a read operation.
- a clamped bit line sense amplifier as shown, can be used.
- the current from the digit lines are injected to the cross coupled pair of inverters (M 1 /M 3 and M 2 /M 4 ).
- Transistors M 5 and M 6 serve to clamp the digit lines at a fixed voltage, e.g., 0.7 volts.
- the impedance looking into the source of transistors M 1 and M 2 is very low but the current injected here from the data lines serves to upset the cross coupled inverters which provides a high speed large signal output.
- other sense amplifiers can be used that allow a current from a trench plate trench capacitor to be sensed.
- Embodiments of the present invention avoid this access speed problem while maintaining a higher threshold voltage. That is, for access devices 124 in a DRAM circuit a larger threshold voltage value is desired to reduce memory cell leakage and increase retention time in the memory cells. By using the bipolar junction transistor in parallel with the field effect transistor, a larger threshold voltage can be maintained without increasing cell leakage and reducing retention time.
- FIG. 3A illustrates a schematic diagram of a vertical access device 200 having both a bipolar junction transistor 202 and a metal-oxide semiconductor field effect transistor (MOSFET) 204 which can be formed in either bulk or SOI technology.
- Bipolar junction transistor 202 is an NPN transistor having emitter 206 , collector 208 and base 210 .
- Transistor 204 is an n-channel MOSFET having first source/drain region 212 , second source/drain region 214 and gate 216 .
- the access device can be fabricated as a single unit, or as separate transistors.
- FIG. 3B is a bulk silicon embodiment of an access device formed in a single pillar of monocrystalline semiconductor material.
- Access device 300 includes a parallel combination of a bipolar junction transistor and a field effect transistor.
- Access device 300 is coupled to trench plate trench capacitor 301 .
- Access device 300 includes n+ semiconductor layer 304 .
- Layer 304 serves as an emitter for the bipolar junction transistor, a source/drain region for the field effect transistor and a plate of the trench plate trench capacitor.
- P-doped semiconductor layer 306 is fabricated on layer 304 . The vertical doping profile of region 306 is varied, as explained below, to optimize bipolar transistor action.
- n+ semiconductor layer 312 is provided on top of layer 306 .
- Polysilicon region 316 is fabricated to operate as a gate isolated from layer 306 by gate oxide layer 314 .
- a polysilicon base contact 320 is provided opposite gate 316 on oxide layer 319 and in contact with region 306 .
- trench plate trench capacitor 301 includes a polysilicon mesh (POLY) that surrounds a portion of layer 304 . The polysilicon mesh forms a second plate of capacitor 301 .
- POLY polysilicon mesh
- FIG. 3C is an SOI embodiment of an access device 300 constructed according to the teachings of the present invention.
- access device 300 includes n+ semiconductor layer 304 that extends down through a polysilicon mesh (POLY).
- POLY polysilicon mesh
- the polysilicon mesh and layer 304 are formed on insulator layer 303 , e.g., an oxide, or insulating base layer.
- the remaining components of the access device are substantially the same as the access device of FIG. 3B, although fabrication techniques may differ.
- a vertical doping profile of region 306 of the access device is optimized for both bipolar transistor action and biasing the body of the field effect transistor to a value around 0.9 V to forward bias the base emitter junction.
- the doping profile is controlled so that the top portion 310 of layer 306 is more heavily doped p-type than a bottom region 308 . This difference in doping is represented by the designations P and P ⁇ .
- the actual doping levels with respect to other structures or base layers can be varied, and relative doping levels between the top and bottom regions of layer 306 is only represented herein.
- One way to create the difference in the doping profile is to use the effects of the fabrication of emitter 312 .
- the emitter, or top n-type layer 312 is fabricated a relatively higher base doping level near emitter 312 can be created.
- This doping profile is required in a vertical NPN transistor to give field-aided diffusion in the base and a high current gain, ⁇ . If the base doping is around 10 18 /cm 3 , as is common in NPN transistors, then region 310 also serves to make the n-channel vertical MOSFET enhancement mode, which is difficult to achieve by other techniques since implantations for threshold voltage adjustment cannot be conveniently done.
- n-channel field effect transistor 204 of FIG. 3A is used to discharge the capacitor, it is customary to precharge a data communication “bit” line to ⁇ fraction (1/2) ⁇ V DD , or in this illustration 1.5 volts.
- the peak transfer current I D is estimated to be around 40 ⁇ A assuming a Vt of 0.5 volts.
- the charge from the memory cell requires 1.2 nano-seconds to transfer to the bit line through transistor 204 .
- bipolar access transistor 202 is used with a clamped bit line where the bit line is precharged to a lower voltage, such as 0.7 V.
- the peak bipolar current is determined mostly by the base current I B and the variation of current gain, ⁇ , with peak current. Assuming a base current of 4.0 ⁇ A, a peak collector value of 400 ⁇ A is estimated by:
- the memory cell is assumed to store the 70 fC, the charge from the memory cell requires only 0.18 nano-seconds to transfer to the bit line. A substantial decrease in transfer time, therefore, is experienced by using a bipolar access transistor during read operations in the low voltage memory.
- BJT transistor 202 During a write operation the base of BJT transistor 202 is coupled to a low voltage, such as 0.7 volts.
- the body potential in layer 306 therefore, is held at the low level resulting in a MOSFET body bias which increases as the memory is charged due to an elevated bit line potential.
- the threshold voltage of transistor 204 rises to around one volt.
- a bootstrapped voltage as known to those skilled in the art can be used to drive the gate voltage above three volts, such as four volts. This booted voltage is necessary because the supply voltage is limited to three volts, and a second supply is typically not provided.
- the time required for the write operation is not critical and can be much longer than the read response. Thus, the reduced power requirements of the MOSFET are desirable.
- bit lines are clamped to a low voltage (near the base low voltage), in this example 0.7 V.
- the voltage of the bit lines does not change significantly during a read operation, unlike in a memory using a conventional voltage sense amplifier, since here current not voltage is being sensed.
- the read word line goes to a higher voltage, such as 1.4 V, to forward bias the base-emitter junction and turn on the bipolar transistor 202 .
- the bipolar transistor will be strongly forward biased and quickly discharge the charge stored on the memory storage capacitor onto the bit line where it can be sensed as a current.
- the memory cell discharges to about 0.7 V at which point the bipolar transistor saturates and stops functioning.
- the memory cell data state voltage levels are therefore approximately two volts when charged, and 0.7 V when discharged.
- bit line current sense amplifier is about eight times faster than the a bit line differential voltage sense amplifier commonly used in DRAMs. Further, as detailed above, current transfer from a memory cell to a bit line using the bipolar transfer device is about eight times faster than an n-channel MOSFET transfer device. The net result is that the present invention, when used in a low voltage memory device for data read operations, is about eight times faster than commonly used CMOS DRAMs. Further, a vertical access transistor device with a trench plate trench capacitor is only 4 F 2 in area. A DRAM according to the present invention, therefore, is about one-half the area of conventional DRAM's and about eight times faster.
- the bipolar device would be used for reads and the MOSFET device on the other side of the device pillar can most conveniently be used for write operations to store information on the memory capacitor in a conventional manner.
- the present invention can be scaled to lower power supply voltages and smaller dimensions, in which case the use of the bipolar access device becomes yet more advantageous. For one volt power supply voltages, the threshold voltage variations of MOSFETs will become a large fraction of the total voltage available.
- Embodiments of an access device for a memory device have been described which use an n-channel field effect transistor and a bipolar junction transistor coupled in parallel between a trench plate trench capacitor and a data communication line.
- a base connection of the NPN bipolar junction transistor has been described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel field effect transistor.
- the n-channel field effect transistor is used for writing data to a trench plate trench capacitor, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit.
- the access transistors are described as fabricated as a single vertical pillar.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar junction transistor is described as coupled to a body of the n-channel access transistor. During operation the n-channel field effect transistor is used for writing data to a memory cell, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
Description
- This application is related to the following co-pending, commonly assigned applications which are incorporated by reference:
- U.S. application Ser. No. 09/028,249 entitled “VERTICAL BIPOLAR READ ACCESS FOR LOW VOLTAGE MEMORY CELL,”
- U.S. application Ser. No. 08/944,312 entitled “CIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY USING TRENCH PLATE CAPACITOR CELLS WITH BODY BIAS CONTACTS,”
- U.S. application Ser. No. 08/939,732, entitled “CIRCUIT AND METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR AND TRENCH PLATE TRENCH CAPACITOR,”
- U.S. application Ser. No. 08/939,742, entitled “CIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY CELL WITH VERTICAL TRANSISTOR AND TRENCH CAPACITOR,” and
- U.S. application Ser. No. 08/944,890, entitled “CIRCUIT AND METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR AND TRENCH PLATE TRENCH CAPACITOR.”
- The present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuit memory devices.
- Complimentary metal oxide semiconductor field effect transistors (CMOS FETs) are prevalent in integrated circuit technology because they generally demand less power than bipolar transistors. Threshold voltage variations of CMOS transistors, however, are beginning to pose impractical limitations on CMOS devices as power supply voltages are reduced. In a 0.2 micron CMOS technology a 0.4 V distribution in threshold voltages might be anticipated. With a one volt power supply, this distribution can cause large variations in the speed of a logic circuit, such as those used in integrated memory circuits. For example, a threshold voltage of 0.6 V is required in a DRAM memory cell access transistor to insure low sub-threshold voltage leakage currents. If a threshold voltage distribution of 0.4 volts is experienced, there will be instances where little or no excess voltage above threshold voltage is available. As such, data transfer from a memory cell via such a transistor will be very slow.
- A basic problem with CMOS access transistors results from the fact that CMOS devices do not function well at low voltages and require the use of higher than desirable power supply voltages, currently around two volts in 0.2 micron CMOS technology. Various techniques have been proposed to compensate for this in CMOS technology. For example, some form of transistor forward body bias, or specialized circuits to compensate for threshold voltage variations can be used.
- Various types of lateral MOS transistors have been described and utilized in CMOS technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal oxide semiconductor (BiCMOS) technologies.
- For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an access device for use in a low voltage memory device which performs fast read access of memory data.
- The above mentioned problems with integrated circuit memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell access device is described which uses a combination of bipolar junction and CMOS transistors as access devices to store and read data on a trench plate trench capacitor.
- In particular, one embodiment of the present invention provides a memory cell access device that has two access transistors. The first access transistor is an n-channel field effect transistor (FET) that is coupled between a trench plate trench capacitor and a data communication line. The second access transistor is an NPN bipolar junction transistor that is coupled between the trench plate trench capacitor and the data communication line. The n-channel access transistor and the NPN bipolar junction transistor are connected in parallel, and a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
- In another embodiment, a low voltage memory cell access device fabricated as a vertical pillar structure is provided. The memory cell access device includes a field effect transistor that is coupled between a trench plate trench capacitor and a data communication line. The memory cell access device also includes a bipolar junction transistor that is coupled between the memory cell and the data communication line. The field effect transistor and the bipolar junction transistor are connected in parallel, with a base connection of the bipolar junction transistor that is coupled to a body of the field effect transistor.
- In another embodiment, a memory device having a low voltage supply is provided. The memory device comprises a plurality of memory cells, a plurality of data communication bit lines, and a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines. Each of the plurality of memory cell access devices comprises a field effect transistor and a bipolar junction transistor. The field effect transistor and the bipolar junction transistor are connected in parallel between a trench plate trench capacitor and a data communication bit line.
- In another embodiment, a method of accessing a memory cell is provided. The method includes activating a field effect transistor coupled between a trench plate trench capacitor and a data communication line for writing data to the memory cell, and activating a bipolar junction transistor coupled between the trench plate trench capacitor and a data communication line for reading a charge stored on the memory cell.
- FIG. 1 is a block diagram of an embodiment of a memory device according to the teachings of the present invention.
- FIG. 2 is an embodiment of a portion of an array of memory cells according to the teachings of the present invention.
- FIG. 3A is a schematic diagram that illustrates an embodiment of a memory cell with a vertical access device according to the teachings of the present invention.
- FIG. 3B is a cross sectional view that illustrates an integrated circuit embodiment of the vertical access device of FIG. 3A.
- FIG. 3C is a cross sectional view that illustrates another integrated circuit embodiment of the vertical access device of FIG. 3A.
- In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense.
- The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
- Smaller integrated circuit devices combined with the development of vertical integrated circuit structures, make it possible to use bipolar junction transistor action rather than just field effect transistor operation. In fact, a bipolar junction transistor structure can be used as a data read access device and a field effect transistor used as a data write access device, as described herein. Below, an embodiment of the present invention is described in terms of a dynamic random access memory (DRAM) device. Embodiments of an access device constructed according to the teachings of the present invention are also shown and described. It is understood, however, that these embodiments are provided by way of example and not by way of limitation.
- FIG. 1 is a simplified block diagram of an embodiment of a memory device incorporating access devices constructed according to the teachings of the present invention.
Memory device 100 includes an array ofmemory cells 102,address decoder 104,row access circuitry 106,column access circuitry 108,control circuitry 110, and Input/Output circuit (I/O) 112. - In one embodiment, each cell in
array 102 includes an access device with a bipolar junction transistor coupled in parallel with a field effect transistor between a data communication or digit line and a trench plate trench capacitor. The access device is used to charge and discharge the trench plate trench capacitor to store and read data from the memory cell. The field effect transistor charges the capacitor. The bipolar junction transistor reads the charge stored on the capacitor by discharging the capacitor and providing the current to a current sense amplifier. The bipolar junction transistor typically conducts a higher current compared to its counterpart field effect transistor. Thus, the access device provides the advantage of increased speed in reading the data stored in the memory cell by allowing the capacitor to be discharged more quickly. -
Memory device 100 can be coupled to anexternal microprocessor 114, or memory controller for memory accessing.Memory device 100 receives control signals from themicroprocessor 114, such as WE*, RAS* and CAS* signals.Memory device 100 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of FIG. 1 has been simplified to help focus on embodiments of the present invention. - It will be understood that the above description of a DRAM is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a DRAM. Further, the embodiments of the present invention are equally applicable to any size and type of memory circuit and are not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM, SDRAM, SDRAM II, and DDR SDRAM, as well as Synchlink or Rambus DRAMs.
- Referring to FIG. 2, an embodiment of a portion of
array 102 is provided. The simplified schematic diagram illustrates a portion of a column of thearray 102. The column is generally defined by a pair of data communication ordigit lines Access devices 124 are located along the digit lines for coupling trenchplate trench capacitors 126 to a digit line.Access devices 124 includefield effect transistor 123 in parallel withbipolar junction transistor 125. Thefield effect transistors 123 are activated by a word line (W-WL) to write data to a trench plate trench capacitor, which defines a row of the memory array. Thebipolar junction transistors 125 are activated by a word line (R-WL) to read data from a trench plate trench capacitor. -
Current sense amplifier 128 is provided to detect current signals provided to the digit lines by a bipolar junction transistor during a read operation. In one embodiment, a clamped bit line sense amplifier, as shown, can be used. The current from the digit lines are injected to the cross coupled pair of inverters (M1/M3 and M2/M4). Transistors M5 and M6 serve to clamp the digit lines at a fixed voltage, e.g., 0.7 volts. The impedance looking into the source of transistors M1 and M2 is very low but the current injected here from the data lines serves to upset the cross coupled inverters which provides a high speed large signal output. Alternatively, other sense amplifiers can be used that allow a current from a trench plate trench capacitor to be sensed. - As described above, a large variation in a threshold voltage of the field effect access transistors can result in slow data access. This slow access is most troubling in data read operations. Embodiments of the present invention avoid this access speed problem while maintaining a higher threshold voltage. That is, for
access devices 124 in a DRAM circuit a larger threshold voltage value is desired to reduce memory cell leakage and increase retention time in the memory cells. By using the bipolar junction transistor in parallel with the field effect transistor, a larger threshold voltage can be maintained without increasing cell leakage and reducing retention time. - FIG. 3A illustrates a schematic diagram of a
vertical access device 200 having both abipolar junction transistor 202 and a metal-oxide semiconductor field effect transistor (MOSFET) 204 which can be formed in either bulk or SOI technology.Bipolar junction transistor 202 is an NPNtransistor having emitter 206,collector 208 andbase 210.Transistor 204 is an n-channel MOSFET having first source/drain region 212, second source/drain region 214 andgate 216. The access device can be fabricated as a single unit, or as separate transistors. - FIGS. 3B and 3C provide alternative fabricated integrated circuit embodiments of an
access device 300 constructed according to the teachings of the present invention. FIG. 3B is a bulk silicon embodiment of an access device formed in a single pillar of monocrystalline semiconductor material.Access device 300 includes a parallel combination of a bipolar junction transistor and a field effect transistor.Access device 300 is coupled to trenchplate trench capacitor 301.Access device 300 includesn+ semiconductor layer 304.Layer 304 serves as an emitter for the bipolar junction transistor, a source/drain region for the field effect transistor and a plate of the trench plate trench capacitor. P-dopedsemiconductor layer 306 is fabricated onlayer 304. The vertical doping profile ofregion 306 is varied, as explained below, to optimize bipolar transistor action. Ann+ semiconductor layer 312 is provided on top oflayer 306.Polysilicon region 316 is fabricated to operate as a gate isolated fromlayer 306 bygate oxide layer 314. Apolysilicon base contact 320 is providedopposite gate 316 onoxide layer 319 and in contact withregion 306. Further, trenchplate trench capacitor 301 includes a polysilicon mesh (POLY) that surrounds a portion oflayer 304. The polysilicon mesh forms a second plate ofcapacitor 301. - FIG. 3C is an SOI embodiment of an
access device 300 constructed according to the teachings of the present invention. In this embodiment,access device 300 includesn+ semiconductor layer 304 that extends down through a polysilicon mesh (POLY). The polysilicon mesh andlayer 304 are formed oninsulator layer 303, e.g., an oxide, or insulating base layer. The remaining components of the access device are substantially the same as the access device of FIG. 3B, although fabrication techniques may differ. - A vertical doping profile of
region 306 of the access device is optimized for both bipolar transistor action and biasing the body of the field effect transistor to a value around 0.9 V to forward bias the base emitter junction. The doping profile is controlled so that thetop portion 310 oflayer 306 is more heavily doped p-type than abottom region 308. This difference in doping is represented by the designations P and P−. The actual doping levels with respect to other structures or base layers can be varied, and relative doping levels between the top and bottom regions oflayer 306 is only represented herein. - One way to create the difference in the doping profile is to use the effects of the fabrication of
emitter 312. When the emitter, or top n-type layer 312, is fabricated a relatively higher base doping level nearemitter 312 can be created. This doping profile is required in a vertical NPN transistor to give field-aided diffusion in the base and a high current gain, β. If the base doping is around 1018/cm3, as is common in NPN transistors, thenregion 310 also serves to make the n-channel vertical MOSFET enhancement mode, which is difficult to achieve by other techniques since implantations for threshold voltage adjustment cannot be conveniently done. - The following comparison further illustrates the advantage of using a bipolar junction transistor for data read operations in a low voltage memory. If n-channel
field effect transistor 204 of FIG. 3A is used to discharge the capacitor, it is customary to precharge a data communication “bit” line to {fraction (1/2)} VDD, or in this illustration 1.5 volts. The peak transfer current ID is estimated to be around 40 μA assuming a Vt of 0.5 volts. That is, the drain current is calculated by: - If the memory cell is assumed to store 50 fC, the charge from the memory cell requires 1.2 nano-seconds to transfer to the bit line through
transistor 204. - A faster data transfer is possible if
bipolar access transistor 202 is used with a clamped bit line where the bit line is precharged to a lower voltage, such as 0.7 V. The peak bipolar current is determined mostly by the base current IB and the variation of current gain, β, with peak current. Assuming a base current of 4.0 μA, a peak collector value of 400 μA is estimated by: - I C =βI B where β=100
- If the memory cell is assumed to store the 70 fC, the charge from the memory cell requires only 0.18 nano-seconds to transfer to the bit line. A substantial decrease in transfer time, therefore, is experienced by using a bipolar access transistor during read operations in the low voltage memory.
- During a write operation the base of
BJT transistor 202 is coupled to a low voltage, such as 0.7 volts. The body potential inlayer 306, therefore, is held at the low level resulting in a MOSFET body bias which increases as the memory is charged due to an elevated bit line potential. As a result, the threshold voltage oftransistor 204 rises to around one volt. A bootstrapped voltage as known to those skilled in the art can be used to drive the gate voltage above three volts, such as four volts. This booted voltage is necessary because the supply voltage is limited to three volts, and a second supply is typically not provided. The time required for the write operation is not critical and can be much longer than the read response. Thus, the reduced power requirements of the MOSFET are desirable. - During a read operation the bit lines are clamped to a low voltage (near the base low voltage), in this example 0.7 V. The voltage of the bit lines does not change significantly during a read operation, unlike in a memory using a conventional voltage sense amplifier, since here current not voltage is being sensed. During a read operation, the read word line goes to a higher voltage, such as 1.4 V, to forward bias the base-emitter junction and turn on the
bipolar transistor 202. The bipolar transistor will be strongly forward biased and quickly discharge the charge stored on the memory storage capacitor onto the bit line where it can be sensed as a current. The memory cell discharges to about 0.7 V at which point the bipolar transistor saturates and stops functioning. The memory cell data state voltage levels are therefore approximately two volts when charged, and 0.7 V when discharged. - It is estimated that a bit line current sense amplifier is about eight times faster than the a bit line differential voltage sense amplifier commonly used in DRAMs. Further, as detailed above, current transfer from a memory cell to a bit line using the bipolar transfer device is about eight times faster than an n-channel MOSFET transfer device. The net result is that the present invention, when used in a low voltage memory device for data read operations, is about eight times faster than commonly used CMOS DRAMs. Further, a vertical access transistor device with a trench plate trench capacitor is only 4 F2 in area. A DRAM according to the present invention, therefore, is about one-half the area of conventional DRAM's and about eight times faster.
- In operation, the bipolar device would be used for reads and the MOSFET device on the other side of the device pillar can most conveniently be used for write operations to store information on the memory capacitor in a conventional manner. The present invention can be scaled to lower power supply voltages and smaller dimensions, in which case the use of the bipolar access device becomes yet more advantageous. For one volt power supply voltages, the threshold voltage variations of MOSFETs will become a large fraction of the total voltage available.
- Embodiments of an access device for a memory device have been described which use an n-channel field effect transistor and a bipolar junction transistor coupled in parallel between a trench plate trench capacitor and a data communication line. A base connection of the NPN bipolar junction transistor has been described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel field effect transistor. During operation the n-channel field effect transistor is used for writing data to a trench plate trench capacitor, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention.
Claims (27)
1. A memory cell access device comprising:
an n-channel field effect transistor coupled between a trench plate trench capacitor and a data communication line; and
an NPN bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, such that the n-channel transistor and the NPN bipolar junction transistor are connected in parallel, a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
2. The memory cell access device of , wherein the n-channel field effect transistor and the NPN bipolar junction transistor are fabricated as a single unit.
claim 1
3. The memory cell access device of , wherein the single unit comprises:
claim 2
a first layer of n-type semiconductor material;
a p-type semiconductor material fabricated outwardly from the first layer of n-type semiconductor material;
a gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; and
a second layer of n-type semiconductor material fabricated on top of the p-type semiconductor material, such that the p-type semiconductor material functions as both a body of the n-channel field effect transistor and a base of the NPN bipolar junction transistor.
4. The memory cell access device of , wherein the p-type semiconductor material has a doping profile such that a top portion of the p-type semiconductor material is more heavily doped than a bottom portion of the p-type semiconductor material.
claim 3
5. The memory cell access device of , wherein a portion of the first layer of n-type material functions as one plate of the trench plate trench capacitor.
claim 3
6. The memory cell access device of , wherein the portion of the first layer of n-type material that functions as one plate of the trench capacitor is surrounded by a polysilicon mesh that functions as the second plate of the trench plate trench capacitor.
claim 5
7. The memory cell access device of , wherein the n-channel field effect transistor is used to write date to the memory cell, and the NPN bipolar junction transistor is used to read data from the memory cell.
claim 1
8. A low voltage memory cell access device fabricated as a vertical pillar structure, the memory cell access device comprising:
a field effect transistor coupled between a trench plate trench capacitor and a data communication line; and
a bipolar junction transistor coupled between the trench plate trench capacitor and the data communication line, such that the field effect transistor and the bipolar junction transistor are connected in parallel, a base connection of the bipolar junction transistor is coupled to a body of the field effect transistor.
9. The low voltage memory cell access device of wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
claim 8
10. The low voltage memory cell access device of wherein the field effect transistor and the bipolar junction transistor are fabricated as a common structure comprising:
claim 9
a first layer of n-type semiconductor material;
a p-type semiconductor material fabricated on top of the first layer of n-type semiconductor material;
a gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation;
a second layer of n-type semiconductor material fabricated-outwardly from the p-type semiconductor material, such that the p-type semiconductor material functions as both a body of the n-channel field effect transistor and a base of the NPN bipolar junction transistor; and
a base contact formed adjacent to the p-type semiconductor material on a side opposite the gate.
11. The low voltage memory cell access device of , wherein the first layer of n-type semiconductor material includes a portion that functions as a first plate of the trench plate trench capacitor.
claim 10
12. The low voltage memory cell access device of , and further comprising a first word line coupled to the gate for activating the n-channel transistor, and a second word line coupled to the base contact for activating the NPN bipolar junction transistor.
claim 10
13. The low voltage memory cell access device of , wherein the p-type semiconductor material has a doping profile such that a top portion of the p-type semiconductor material is more heavily doped than a bottom portion of the p-type semiconductor material.
claim 8
14. The low voltage memory cell access device of , wherein the low voltage memory cell access device is fabricated using a silicon-on-insulator (SOI) construction.
claim 8
15. The low voltage memory cell access device of , wherein the low voltage memory cell access device is fabricated in bulk silicon.
claim 8
16. A memory device having a low voltage supply, the memory device comprising:
a plurality of memory cells;
a plurality of data communication bit lines; and
a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines, each of the plurality of memory cell access devices comprising:
a field effect transistor, and
a bipolar junction transistor, such that the field effect transistor and the bipolar junction access transistor are connected in parallel between a trench plate trench capacitor and a data communication bit line.
17. The memory device of , wherein each memory cell access device includes a field effect transistor and a bipolar junction transistor that share a common pillar of semiconductor material.
claim 16
18. The memory device of wherein the memory device is a dynamic random access memory (DRAM).
claim 16
19. The memory device of wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
claim 16
20. The memory device of further comprising a plurality of current sense amplifiers coupled to the plurality of data communication bit lines for sensing data stored on the plurality of memory cells.
claim 16
21. A method of accessing a memory cell, the method comprising the steps of:
activating a field effect transistor coupled between a trench plate trench capacitor of the memory cell and a data communication line for writing data to the memory cell; and
activating a bipolar junction transistor coupled between the trench plate trench capacitor of the memory cell and a data communication line for reading a charge stored on the memory cell.
22. The method of wherein the field effect transistor is an n-channel transistor and the bipolar junction transistor is an NPN transistor.
claim 21
23. The method of wherein a body of the n-channel transistor is coupled to a base of the NPN transistor.
claim 22
24. The method of wherein a gate voltage of the field effect transistor varies between zero and three volts.
claim 23
25. The method of wherein a base voltage of the NPN access transistor varies between 0.7 and approximately 1.4 volts.
claim 23
26. The method of wherein the field effect transistor and the bipolar junction access transistor are fabricated in a common vertical pillar structure.
claim 23
27. The method of wherein the common vertical pillar structure comprises:
claim 26
a first layer of n-type semiconductor material;
a p-type semiconductor material fabricated on top of the first layer of n-type semiconductor material;
a gate fabricated adjacent to the p-type semiconductor material and electrically separated by a layer of gate insulation; and
a second layer of n-type semiconductor material fabricated outwardly from the p-type semiconductor material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/916,768 US6434041B2 (en) | 1998-04-14 | 2001-07-27 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/060,048 US6043527A (en) | 1998-04-14 | 1998-04-14 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/498,433 US6381168B2 (en) | 1998-04-14 | 2000-02-04 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/916,768 US6434041B2 (en) | 1998-04-14 | 2001-07-27 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/498,433 Division US6381168B2 (en) | 1998-04-14 | 2000-02-04 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010046155A1 true US20010046155A1 (en) | 2001-11-29 |
US6434041B2 US6434041B2 (en) | 2002-08-13 |
Family
ID=22026999
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/060,048 Expired - Fee Related US6043527A (en) | 1998-04-14 | 1998-04-14 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/498,433 Expired - Fee Related US6381168B2 (en) | 1998-04-14 | 2000-02-04 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/916,759 Expired - Fee Related US6429065B2 (en) | 1998-04-14 | 2001-07-27 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/916,769 Expired - Fee Related US6418050B2 (en) | 1998-04-14 | 2001-07-27 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/916,768 Expired - Fee Related US6434041B2 (en) | 1998-04-14 | 2001-07-27 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/060,048 Expired - Fee Related US6043527A (en) | 1998-04-14 | 1998-04-14 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/498,433 Expired - Fee Related US6381168B2 (en) | 1998-04-14 | 2000-02-04 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/916,759 Expired - Fee Related US6429065B2 (en) | 1998-04-14 | 2001-07-27 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US09/916,769 Expired - Fee Related US6418050B2 (en) | 1998-04-14 | 2001-07-27 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
Country Status (1)
Country | Link |
---|---|
US (5) | US6043527A (en) |
Families Citing this family (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6191470B1 (en) | 1997-07-08 | 2001-02-20 | Micron Technology, Inc. | Semiconductor-on-insulator memory cell with buried word and body lines |
US6066869A (en) * | 1997-10-06 | 2000-05-23 | Micron Technology, Inc. | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
US5907170A (en) | 1997-10-06 | 1999-05-25 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US6528837B2 (en) * | 1997-10-06 | 2003-03-04 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US6025225A (en) * | 1998-01-22 | 2000-02-15 | Micron Technology, Inc. | Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same |
US6246083B1 (en) * | 1998-02-24 | 2001-06-12 | Micron Technology, Inc. | Vertical gain cell and array for a dynamic random access memory |
US6304483B1 (en) * | 1998-02-24 | 2001-10-16 | Micron Technology, Inc. | Circuits and methods for a static random access memory using vertical transistors |
US6448615B1 (en) | 1998-02-26 | 2002-09-10 | Micron Technology, Inc. | Methods, structures, and circuits for transistors with gate-to-body capacitive coupling |
US6124729A (en) | 1998-02-27 | 2000-09-26 | Micron Technology, Inc. | Field programmable logic arrays with vertical transistors |
US5991225A (en) * | 1998-02-27 | 1999-11-23 | Micron Technology, Inc. | Programmable memory address decode array with vertical transistors |
US6075272A (en) * | 1998-03-30 | 2000-06-13 | Micron Technology, Inc. | Structure for gated lateral bipolar transistors |
US6043527A (en) | 1998-04-14 | 2000-03-28 | Micron Technology, Inc. | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US6208164B1 (en) | 1998-08-04 | 2001-03-27 | Micron Technology, Inc. | Programmable logic array with vertical transistors |
DE19914496A1 (en) * | 1999-03-30 | 2000-10-05 | Siemens Ag | Memory cell structure, especially for a DRAM, has a contact within a substrate for connecting a capacitor and a MOS transistor on opposite substrate surfaces |
US6477079B2 (en) * | 1999-05-18 | 2002-11-05 | Kabushiki Kaisha Toshiba | Voltage generator for semiconductor device |
DE10009346B4 (en) * | 2000-02-28 | 2011-06-16 | Qimonda Ag | Integrated read / write circuit for evaluating at least one bitline in a DRAM memory |
US6721221B2 (en) * | 2001-06-08 | 2004-04-13 | Micron Technology, Inc. | Sense amplifier and architecture for open digit arrays |
US6828615B2 (en) | 2001-08-30 | 2004-12-07 | Promos Technologies, Inc. | Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices |
US6566190B2 (en) * | 2001-08-30 | 2003-05-20 | Promos Technologies, Inc. | Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices |
US8026161B2 (en) | 2001-08-30 | 2011-09-27 | Micron Technology, Inc. | Highly reliable amorphous high-K gate oxide ZrO2 |
US6900122B2 (en) * | 2001-12-20 | 2005-05-31 | Micron Technology, Inc. | Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics |
US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
US7221017B2 (en) * | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide-conductor nanolaminates |
US7221586B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
US7205598B2 (en) * | 2002-08-29 | 2007-04-17 | Micron Technology, Inc. | Random access memory device utilizing a vertically oriented select transistor |
US6888769B2 (en) * | 2002-08-29 | 2005-05-03 | Micron Technology, Inc. | Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage |
US6936512B2 (en) * | 2002-09-27 | 2005-08-30 | International Business Machines Corporation | Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric |
DE60217120T2 (en) * | 2002-10-08 | 2007-10-25 | Stmicroelectronics S.R.L., Agrate Brianza | A cell assembly having a select bipolar transistor therein and a method of fabricating the same |
DE60218685T2 (en) * | 2002-10-08 | 2007-11-15 | Stmicroelectronics S.R.L., Agrate Brianza | Cell array fabrication process with bipolar select transistors and associated cell array |
US6645808B1 (en) * | 2002-10-15 | 2003-11-11 | Mosel Vitelic, Inc. | Method and device for providing double cell density in SDRAM and in DDR SDRAM |
US7135369B2 (en) | 2003-03-31 | 2006-11-14 | Micron Technology, Inc. | Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9 |
JP2005116969A (en) * | 2003-10-10 | 2005-04-28 | Toshiba Corp | Semiconductor device and its manufacturing method |
US7081421B2 (en) | 2004-08-26 | 2006-07-25 | Micron Technology, Inc. | Lanthanide oxide dielectric layer |
US7494939B2 (en) | 2004-08-31 | 2009-02-24 | Micron Technology, Inc. | Methods for forming a lanthanum-metal oxide dielectric layer |
EP1640994B1 (en) * | 2004-09-22 | 2010-04-07 | STMicroelectronics Srl | A memory device with unipolar and bipolar selectors |
US20060125030A1 (en) * | 2004-12-13 | 2006-06-15 | Micron Technology, Inc. | Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics |
US7560395B2 (en) | 2005-01-05 | 2009-07-14 | Micron Technology, Inc. | Atomic layer deposited hafnium tantalum oxide dielectrics |
US7374964B2 (en) | 2005-02-10 | 2008-05-20 | Micron Technology, Inc. | Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics |
JP2006260742A (en) * | 2005-02-15 | 2006-09-28 | Sanyo Electric Co Ltd | Memory |
US7662729B2 (en) | 2005-04-28 | 2010-02-16 | Micron Technology, Inc. | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7230868B2 (en) * | 2005-07-28 | 2007-06-12 | Texas Instruments Incorporated | Stable source-coupled sense amplifier |
US7410910B2 (en) | 2005-08-31 | 2008-08-12 | Micron Technology, Inc. | Lanthanum aluminum oxynitride dielectric films |
US8071476B2 (en) * | 2005-08-31 | 2011-12-06 | Micron Technology, Inc. | Cobalt titanium oxide dielectric films |
US7642588B2 (en) * | 2005-10-26 | 2010-01-05 | International Business Machines Corporation | Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same |
US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
US8194451B2 (en) | 2007-11-29 | 2012-06-05 | Zeno Semiconductor, Inc. | Memory cells, memory cell arrays, methods of using and methods of making |
US7759237B2 (en) | 2007-06-28 | 2010-07-20 | Micron Technology, Inc. | Method of forming lutetium and lanthanum dielectric structures |
US10403361B2 (en) | 2007-11-29 | 2019-09-03 | Zeno Semiconductor, Inc. | Memory cells, memory cell arrays, methods of using and methods of making |
US7943997B2 (en) * | 2008-04-17 | 2011-05-17 | International Business Machines Corporation | Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s) |
US20090305470A1 (en) * | 2008-06-10 | 2009-12-10 | International Business Machines Corporation | Isolating back gates of fully depleted soi devices |
US7772647B2 (en) * | 2008-06-10 | 2010-08-10 | International Business Machines Corporation | Structure and design structure having isolated back gates for fully depleted SOI devices |
JP2010034191A (en) * | 2008-07-28 | 2010-02-12 | Toshiba Corp | Semiconductor memory device and manufacturing method thereof |
US7936580B2 (en) | 2008-10-20 | 2011-05-03 | Seagate Technology Llc | MRAM diode array and access method |
US9030867B2 (en) * | 2008-10-20 | 2015-05-12 | Seagate Technology Llc | Bipolar CMOS select device for resistive sense memory |
US7936583B2 (en) | 2008-10-30 | 2011-05-03 | Seagate Technology Llc | Variable resistive memory punchthrough access method |
US7825478B2 (en) | 2008-11-07 | 2010-11-02 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US8178864B2 (en) * | 2008-11-18 | 2012-05-15 | Seagate Technology Llc | Asymmetric barrier diode |
US8933536B2 (en) * | 2009-01-22 | 2015-01-13 | Macronix International Co., Ltd. | Polysilicon pillar bipolar transistor with self-aligned memory element |
US8159856B2 (en) * | 2009-07-07 | 2012-04-17 | Seagate Technology Llc | Bipolar select device for resistive sense memory |
US8158964B2 (en) | 2009-07-13 | 2012-04-17 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
KR101576296B1 (en) * | 2009-12-11 | 2015-12-10 | 주식회사 동부하이텍 | Capcitor for semiconductor device and manufacturing method of capacitor for semiconductor device |
US9059319B2 (en) * | 2010-01-25 | 2015-06-16 | International Business Machines Corporation | Embedded dynamic random access memory device and method |
KR101105712B1 (en) | 2010-12-13 | 2012-01-17 | 서울대학교산학협력단 | Memory cell structure of capacitorless dram |
US8648426B2 (en) | 2010-12-17 | 2014-02-11 | Seagate Technology Llc | Tunneling transistors |
US9117499B2 (en) | 2012-10-25 | 2015-08-25 | Elwha Llc | Bipolar logic gates on MOS-based memory chips |
US8929133B2 (en) * | 2012-12-02 | 2015-01-06 | International Business Machines Corporation | Complementary SOI lateral bipolar for SRAM in a CMOS platform |
US9336860B1 (en) | 2015-05-20 | 2016-05-10 | International Business Machines Corporation | Complementary bipolar SRAM |
US10115438B2 (en) | 2016-08-31 | 2018-10-30 | Micron Technology, Inc. | Sense amplifier constructions |
WO2018044458A1 (en) | 2016-08-31 | 2018-03-08 | Micron Technology, Inc. | Memory arrays |
CN109155310B (en) | 2016-08-31 | 2023-03-31 | 美光科技公司 | Memory cell and memory array |
WO2018044454A1 (en) | 2016-08-31 | 2018-03-08 | Micron Technology, Inc. | Memory cells and memory arrays |
US10355002B2 (en) | 2016-08-31 | 2019-07-16 | Micron Technology, Inc. | Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry |
US10153281B2 (en) | 2016-08-31 | 2018-12-11 | Micron Technology, Inc. | Memory cells and memory arrays |
KR20180130581A (en) | 2016-08-31 | 2018-12-07 | 마이크론 테크놀로지, 인크 | Memory cells and memory arrays |
US11211384B2 (en) | 2017-01-12 | 2021-12-28 | Micron Technology, Inc. | Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry |
EP3676835A4 (en) | 2017-08-29 | 2020-08-19 | Micron Technology, Inc. | Memory circuitry |
JP7155985B2 (en) * | 2018-12-13 | 2022-10-19 | トヨタ自動車株式会社 | Vehicle and passenger transportation system |
JP7338157B2 (en) * | 2019-01-21 | 2023-09-05 | スズキ株式会社 | vehicle controller |
US11018188B2 (en) * | 2019-06-03 | 2021-05-25 | International Business Machines Corporation | Three-dimensional stackable multi-layer cross-point memory with bipolar junction transistor selectors |
US10984874B1 (en) * | 2019-11-13 | 2021-04-20 | Sandisk Technologies Llc | Differential dbus scheme for low-latency random read for NAND memories |
CN113013167A (en) * | 2021-03-08 | 2021-06-22 | 电子科技大学 | Novel DRAM structure and implementation method |
Family Cites Families (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2111979A1 (en) | 1970-03-13 | 1971-10-21 | Hitachi Ltd | Field effect semiconductor device |
US3806741A (en) | 1972-05-17 | 1974-04-23 | Standard Microsyst Smc | Self-biasing technique for mos substrate voltage |
US3931617A (en) * | 1974-10-07 | 1976-01-06 | Signetics Corporation | Collector-up dynamic memory cell |
US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
US4252579A (en) | 1979-05-07 | 1981-02-24 | International Business Machines Corporation | Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition |
US4604162A (en) * | 1983-06-13 | 1986-08-05 | Ncr Corporation | Formation and planarization of silicon-on-insulator structures |
US5208657A (en) * | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US4766569A (en) * | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US5102817A (en) * | 1985-03-21 | 1992-04-07 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US4673962A (en) * | 1985-03-21 | 1987-06-16 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US4677589A (en) * | 1985-07-26 | 1987-06-30 | Advanced Micro Devices, Inc. | Dynamic random access memory cell having a charge amplifier |
US4663831A (en) * | 1985-10-08 | 1987-05-12 | Motorola, Inc. | Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers |
JPS6366963A (en) * | 1986-09-08 | 1988-03-25 | Nippon Telegr & Teleph Corp <Ntt> | Groove-buried semiconductor device and manufacture thereof |
US5017504A (en) * | 1986-12-01 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Vertical type MOS transistor and method of formation thereof |
JPS63198323A (en) * | 1987-02-13 | 1988-08-17 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
JP2735193B2 (en) | 1987-08-25 | 1998-04-02 | 株式会社東芝 | Nonvolatile semiconductor device and method of manufacturing the same |
JPH01125858A (en) * | 1987-11-10 | 1989-05-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
EP0333426B1 (en) * | 1988-03-15 | 1996-07-10 | Kabushiki Kaisha Toshiba | Dynamic RAM |
JPH07105477B2 (en) * | 1988-05-28 | 1995-11-13 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
US4958318A (en) * | 1988-07-08 | 1990-09-18 | Eliyahou Harari | Sidewall capacitor DRAM cell |
US4920065A (en) * | 1988-10-31 | 1990-04-24 | International Business Machines Corporation | Method of making ultra dense dram cells |
US5327380B1 (en) * | 1988-10-31 | 1999-09-07 | Texas Instruments Inc | Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
US5021355A (en) * | 1989-05-22 | 1991-06-04 | International Business Machines Corporation | Method of fabricating cross-point lightly-doped drain-source trench transistor |
US5028977A (en) * | 1989-06-16 | 1991-07-02 | Massachusetts Institute Of Technology | Merged bipolar and insulated gate transistors |
US5316962A (en) * | 1989-08-15 | 1994-05-31 | Matsushita Electric Industrial Co., Ltd. | Method of producing a semiconductor device having trench capacitors and vertical switching transistors |
US5006909A (en) * | 1989-10-30 | 1991-04-09 | Motorola, Inc. | Dram with a vertical capacitor and transistor |
JPH0821689B2 (en) * | 1990-02-26 | 1996-03-04 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
JPH04212450A (en) * | 1990-04-11 | 1992-08-04 | Mitsubishi Electric Corp | Semiconductor storage device and its manufacture |
JPH0414868A (en) * | 1990-05-09 | 1992-01-20 | Hitachi Ltd | Semiconductor memory and manufacture thereof |
US4987089A (en) * | 1990-07-23 | 1991-01-22 | Micron Technology, Inc. | BiCMOS process and process for forming bipolar transistors on wafers also containing FETs |
US5140388A (en) | 1991-03-22 | 1992-08-18 | Hewlett-Packard Company | Vertical metal-oxide semiconductor devices |
JPH05129554A (en) * | 1991-07-01 | 1993-05-25 | Toshiba Corp | Dynamic semiconductor memory device |
US5223081A (en) * | 1991-07-03 | 1993-06-29 | Doan Trung T | Method for roughening a silicon or polysilicon surface for a semiconductor substrate |
US5110752A (en) * | 1991-07-10 | 1992-05-05 | Industrial Technology Research Institute | Roughened polysilicon surface capacitor electrode plate for high denity dram |
KR940007640B1 (en) * | 1991-07-31 | 1994-08-22 | 삼성전자 주식회사 | Data transimitting circuit having common input/output line |
US5202278A (en) * | 1991-09-10 | 1993-04-13 | Micron Technology, Inc. | Method of forming a capacitor in semiconductor wafer processing |
KR940006679B1 (en) * | 1991-09-26 | 1994-07-25 | 현대전자산업 주식회사 | Dram cell having a vertical transistor and fabricating method thereof |
US5177028A (en) * | 1991-10-22 | 1993-01-05 | Micron Technology, Inc. | Trench isolation method having a double polysilicon gate formed on mesas |
US5128831A (en) | 1991-10-31 | 1992-07-07 | Micron Technology, Inc. | High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias |
TW289168B (en) * | 1991-12-16 | 1996-10-21 | Philips Nv | |
US5156987A (en) * | 1991-12-18 | 1992-10-20 | Micron Technology, Inc. | High performance thin film transistor (TFT) by solid phase epitaxial regrowth |
US5926412A (en) * | 1992-02-09 | 1999-07-20 | Raytheon Company | Ferroelectric memory structure |
JP3224215B2 (en) | 1992-03-25 | 2001-10-29 | 株式会社半導体エネルギー研究所 | Method for manufacturing thin-film insulated gate semiconductor device |
US5365477A (en) * | 1992-06-16 | 1994-11-15 | The United States Of America As Represented By The Secretary Of The Navy | Dynamic random access memory device |
US5528062A (en) * | 1992-06-17 | 1996-06-18 | International Business Machines Corporation | High-density DRAM structure on soi |
US5292676A (en) | 1992-07-29 | 1994-03-08 | Micron Semiconductor, Inc. | Self-aligned low resistance buried contact process |
US5320880A (en) * | 1992-10-20 | 1994-06-14 | Micron Technology, Inc. | Method of providing a silicon film having a roughened outer surface |
US5266514A (en) * | 1992-12-21 | 1993-11-30 | Industrial Technology Research Institute | Method for producing a roughened surface capacitor |
US5422499A (en) * | 1993-02-22 | 1995-06-06 | Micron Semiconductor, Inc. | Sixteen megabit static random access memory (SRAM) cell |
US5409563A (en) | 1993-02-26 | 1995-04-25 | Micron Technology, Inc. | Method for etching high aspect ratio features |
JPH06268173A (en) | 1993-03-15 | 1994-09-22 | Toshiba Corp | Semiconductor memory device |
US5306659A (en) * | 1993-03-29 | 1994-04-26 | International Business Machines Corporation | Reach-through isolation etching method for silicon-on-insulator devices |
US5438009A (en) * | 1993-04-02 | 1995-08-01 | United Microelectronics Corporation | Method of fabrication of MOSFET device with buried bit line |
US5616934A (en) * | 1993-05-12 | 1997-04-01 | Micron Technology, Inc. | Fully planarized thin film transistor (TFT) and process to fabricate same |
JPH07130871A (en) * | 1993-06-28 | 1995-05-19 | Toshiba Corp | Semiconductor memory device |
US5385854A (en) | 1993-07-15 | 1995-01-31 | Micron Semiconductor, Inc. | Method of forming a self-aligned low density drain inverted thin film transistor |
US5392245A (en) * | 1993-08-13 | 1995-02-21 | Micron Technology, Inc. | Redundancy elements using thin film transistors (TFTs) |
JP2605594B2 (en) * | 1993-09-03 | 1997-04-30 | 日本電気株式会社 | Method for manufacturing semiconductor device |
GB9319070D0 (en) * | 1993-09-15 | 1993-11-03 | Ncr Int Inc | Stencil having improved wear-resistance and quality consistency and method of manufacturing the same |
US5382540A (en) * | 1993-09-20 | 1995-01-17 | Motorola, Inc. | Process for forming an electrically programmable read-only memory cell |
US5393704A (en) * | 1993-12-13 | 1995-02-28 | United Microelectronics Corporation | Self-aligned trenched contact (satc) process |
US5362665A (en) * | 1994-02-14 | 1994-11-08 | Industrial Technology Research Institute | Method of making vertical DRAM cross point memory cell |
US5492853A (en) * | 1994-03-11 | 1996-02-20 | Micron Semiconductor, Inc. | Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device |
US5451889A (en) | 1994-03-14 | 1995-09-19 | Motorola, Inc. | CMOS output driver which can tolerate an output voltage greater than the supply voltage without latchup or increased leakage current |
KR960016773B1 (en) * | 1994-03-28 | 1996-12-20 | Samsung Electronics Co Ltd | Buried bit line and cylindrical gate cell and forming method thereof |
JP3282915B2 (en) | 1994-03-31 | 2002-05-20 | 富士通株式会社 | DC / DC converter and method of controlling back gate voltage of NMOS transistor |
US5460988A (en) * | 1994-04-25 | 1995-10-24 | United Microelectronics Corporation | Process for high density flash EPROM cell |
US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
US5495441A (en) * | 1994-05-18 | 1996-02-27 | United Microelectronics Corporation | Split-gate flash memory cell |
US5432739A (en) * | 1994-06-17 | 1995-07-11 | Philips Electronics North America Corporation | Non-volatile sidewall memory cell method of fabricating same |
US5440158A (en) * | 1994-07-05 | 1995-08-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Electrically programmable memory device with improved dual floating gates |
JP3325396B2 (en) * | 1994-08-19 | 2002-09-17 | 株式会社東芝 | Semiconductor integrated circuit |
US5705415A (en) * | 1994-10-04 | 1998-01-06 | Motorola, Inc. | Process for forming an electrically programmable read-only memory cell |
US5593912A (en) * | 1994-10-06 | 1997-01-14 | International Business Machines Corporation | SOI trench DRAM cell for 256 MB DRAM and beyond |
US5508542A (en) * | 1994-10-28 | 1996-04-16 | International Business Machines Corporation | Porous silicon trench and capacitor structures |
JP3549602B2 (en) * | 1995-01-12 | 2004-08-04 | 株式会社ルネサステクノロジ | Semiconductor storage device |
US5497017A (en) * | 1995-01-26 | 1996-03-05 | Micron Technology, Inc. | Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors |
JPH08274612A (en) | 1995-03-31 | 1996-10-18 | Nec Corp | Semiconductor device |
US5641691A (en) * | 1995-04-03 | 1997-06-24 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating complementary vertical bipolar junction transistors in silicon-on-sapphire |
KR0165398B1 (en) | 1995-05-26 | 1998-12-15 | 윤종용 | Vertical transistor manufacturing method |
US5508219A (en) * | 1995-06-05 | 1996-04-16 | International Business Machines Corporation | SOI DRAM with field-shield isolation and body contact |
US5641545A (en) | 1995-06-07 | 1997-06-24 | Micron Technology, Inc. | Method to deposit highly conformal CVD films |
JP2937817B2 (en) | 1995-08-01 | 1999-08-23 | 松下電子工業株式会社 | Method of forming oxide film on semiconductor substrate surface and method of manufacturing MOS semiconductor device |
US5640342A (en) * | 1995-11-20 | 1997-06-17 | Micron Technology, Inc. | Structure for cross coupled thin film transistors and static random access memory cell |
US5998263A (en) | 1996-05-16 | 1999-12-07 | Altera Corporation | High-density nonvolatile memory cell |
US5691230A (en) * | 1996-09-04 | 1997-11-25 | Micron Technology, Inc. | Technique for producing small islands of silicon on insulator |
US5821796A (en) | 1996-09-23 | 1998-10-13 | Texas Instruments Incorporated | Circuitry for providing a high impedance state when powering down a single port node |
US5946472A (en) | 1996-10-31 | 1999-08-31 | International Business Machines Corporation | Apparatus and method for performing behavioral modeling in hardware emulation and simulation environments |
US5874760A (en) | 1997-01-22 | 1999-02-23 | International Business Machines Corporation | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation |
US5852375A (en) | 1997-02-07 | 1998-12-22 | Silicon Systems Research Limited | 5v tolerant I/O circuit |
US5832418A (en) | 1997-06-23 | 1998-11-03 | Micron Electronics | Apparatus for testing a controller with random contraints |
US6072209A (en) | 1997-07-08 | 2000-06-06 | Micro Technology, Inc. | Four F2 folded bit line DRAM cell structure having buried bit and word lines |
US5909400A (en) * | 1997-08-22 | 1999-06-01 | International Business Machines Corporation | Three device BICMOS gain cell |
US5907170A (en) * | 1997-10-06 | 1999-05-25 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US6066869A (en) | 1997-10-06 | 2000-05-23 | Micron Technology, Inc. | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
US6255708B1 (en) | 1997-10-10 | 2001-07-03 | Rengarajan Sudharsanan | Semiconductor P-I-N detector |
US5872032A (en) | 1997-11-03 | 1999-02-16 | Vanguard International Semiconductor Corporation | Fabrication method for a DRAM cell with bipolar charge amplification |
US6181196B1 (en) * | 1997-12-18 | 2001-01-30 | Texas Instruments Incorporated | Accurate bandgap circuit for a CMOS process without NPN devices |
US6025225A (en) | 1998-01-22 | 2000-02-15 | Micron Technology, Inc. | Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same |
US5991225A (en) | 1998-02-27 | 1999-11-23 | Micron Technology, Inc. | Programmable memory address decode array with vertical transistors |
US6043527A (en) | 1998-04-14 | 2000-03-28 | Micron Technology, Inc. | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
US6181121B1 (en) * | 1999-03-04 | 2001-01-30 | Cypress Semiconductor Corp. | Low supply voltage BICMOS self-biased bandgap reference using a current summing architecture |
US6172535B1 (en) * | 1999-11-04 | 2001-01-09 | Analog Devices, Inc. | High-speed analog comparator structures and methods |
US6323719B1 (en) * | 2000-05-08 | 2001-11-27 | National Science Council | Pseudo bipolar junction transistor |
-
1998
- 1998-04-14 US US09/060,048 patent/US6043527A/en not_active Expired - Fee Related
-
2000
- 2000-02-04 US US09/498,433 patent/US6381168B2/en not_active Expired - Fee Related
-
2001
- 2001-07-27 US US09/916,759 patent/US6429065B2/en not_active Expired - Fee Related
- 2001-07-27 US US09/916,769 patent/US6418050B2/en not_active Expired - Fee Related
- 2001-07-27 US US09/916,768 patent/US6434041B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6429065B2 (en) | 2002-08-06 |
US20010053088A1 (en) | 2001-12-20 |
US20010038551A1 (en) | 2001-11-08 |
US6434041B2 (en) | 2002-08-13 |
US20010046154A1 (en) | 2001-11-29 |
US6381168B2 (en) | 2002-04-30 |
US6043527A (en) | 2000-03-28 |
US6418050B2 (en) | 2002-07-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6429065B2 (en) | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device | |
US6317357B1 (en) | Vertical bipolar read access for low voltage memory cell | |
US6424016B1 (en) | SOI DRAM having P-doped polysilicon gate for a memory pass transistor | |
US5732014A (en) | Merged transistor structure for gain memory cell | |
US5148393A (en) | Mos dynamic semiconductor memory cell | |
US6111778A (en) | Body contacted dynamic memory | |
US6097242A (en) | Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits | |
US6385159B2 (en) | Semiconductor memory device including an SOI substrate | |
US6560142B1 (en) | Capacitorless DRAM gain cell | |
US6940761B2 (en) | Merged MOS-bipolar capacitor memory cell | |
US5998820A (en) | Fabrication method and structure for a DRAM cell with bipolar charge amplification | |
JP3128262B2 (en) | Semiconductor integrated circuit device | |
KR0156233B1 (en) | Arrangement with self-amplifying dynamic mos transistor storage cells | |
US4395723A (en) | Floating substrate dynamic RAM cell with lower punch-through means | |
US6549451B2 (en) | Memory cell having reduced leakage current | |
IE52954B1 (en) | Control of a signal voltage for a semiconductor device | |
KR910009452B1 (en) | Active dynamic memory cell | |
EP0061859B1 (en) | Semiconductor memory device | |
JPS6243278B2 (en) | ||
JP2001148387A (en) | Element with low voltage high amplification storage function | |
JPH1098161A (en) | Semiconductor storage device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20100813 |