US20010040467A1 - Method and apparatus for reducing soft errors in dynamic circuits - Google Patents
Method and apparatus for reducing soft errors in dynamic circuits Download PDFInfo
- Publication number
- US20010040467A1 US20010040467A1 US09/909,104 US90910401A US2001040467A1 US 20010040467 A1 US20010040467 A1 US 20010040467A1 US 90910401 A US90910401 A US 90910401A US 2001040467 A1 US2001040467 A1 US 2001040467A1
- Authority
- US
- United States
- Prior art keywords
- circuit
- keeper
- dynamic
- output node
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
Definitions
- An embodiment of the present invention relates to the field of integrated circuits and, more particularly, to reducing soft errors in integrated circuits that include dynamic circuits.
- Dynamic circuits such as domino circuits, for example, are widely used in high-speed integrated circuit designs. This is because dynamic circuits typically provide area and speed advantages over corresponding static complementary metal oxide semiconductor (CMOS) circuits.
- CMOS complementary metal oxide semiconductor
- a soft error is a transient, single event upset that changes the state of a circuit node or other internal storage element.
- Soft errors may, for example, be caused by alpha particles or cosmic rays impinging on the integrated circuit device.
- Alpha particles are charged particles that may originate from the decay of trace impurities in integrated circuit packaging materials, for example.
- Cosmic rays may include heavy ions and protons that, either directly or indirectly, may have an ionization effect within the integrated circuit device semiconductor material. In either case, the charged particles from these sources may change the charge at an integrated circuit node such that the node actually transitions to an opposite logical state.
- the critical charge (Qcrit) at a node is an indication of the susceptibility of the node to such soft errors.
- Qcrit is the minimum charge beyond which operation of a circuit will be affected.
- the node may erroneously transition from a logical one state to a logical zero state, for example.
- Error detection and/or correction circuitry identifies circuit errors such that resulting issues may be mitigated while correction circuitry may compensate for the error.
- Such approaches while preventing some circuit failures, can involve significant additional circuitry that takes up valuable semiconductor real estate. Additionally, such approaches may not be viable for dynamic circuits in speed critical paths, for example.
- DRAM dynamic random access memory
- gate oxide thicknesses are decreased to store additional charge. This approach, however, may lead to an increase in other types of failures due to increased defects in the thinner gate oxide.
- a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected.
- a keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
- FIG. 1 is a schematic diagram of a dynamic circuit in accordance with one embodiment.
- FIG. 2 is a schematic diagram of a dynamic circuit in accordance with an alternative embodiment.
- FIG. 1 is a schematic diagram of a dynamic circuit 100 in accordance with one embodiment.
- the dynamic circuit 100 includes a dynamic logic gate 105 , a keeper circuit 110 , and an interface inverter 115 (or another type of interface gate such as a complex gate).
- the dynamic logic gate 105 for the example shown in FIG. 1 is a three-input domino NAND gate, however, other types of dynamic logic gates, including other types of domino gates, may also benefit from various embodiments of the invention.
- the dynamic logic gate 105 includes data inputs A, B and C and a clock input CLK.
- Output data from the dynamic logic gate 105 is provided at an output node 120 , which may also be referred to as a precharge node.
- the output/precharge node 120 may be precharged to a predetermined level (a logical high level in this example) and during an evaluate phase, an output value may be read at the node 120 .
- the keeper circuit 110 includes a first inverter 125 having an input coupled to the output node 120 and an output coupled to a feedback node 130 . Also coupled to the feedback node 130 is an input of a second inverter including a p-channel metal oxide semiconductor (PMOS) keeper device 135 and an n-channel MOS (NMOS) keeper device 140 . An output of the second inverter is coupled to the output node 120 .
- PMOS metal oxide semiconductor
- NMOS n-channel MOS
- the keeper circuit 110 operates to maintain a voltage level at the output node 120 .
- the keeper circuit 110 supplies charge to compensate for loss of charge at the output node 120 due to various leakage paths and capacitive coupling of the output node 120 to other signal paths.
- the keeper circuit 110 of FIG. 1 is a full keeper (i.e. it is switchable to maintain the output node 120 at either a logical high or a logical low level).
- a half keeper circuit that only maintains the output node at one level (either high or low) may be used in place of the full keeper 110 .
- the interface inverter 115 for the exemplary circuit shown in FIG. 1 is a gate that provides an interface to subsequent logic (not shown).
- the interface inverter 115 may be provided, for example, so that a domino circuit coupled to the dynamic circuit 100 is in a precharge phase while the dynamic circuit 100 is in an evaluate phase to ensure proper operation of the coupled circuits.
- the interface inverter 115 may be a high-skewed gate for one embodiment such that transitions in a particular direction are favored.
- the dynamic circuit 100 provides a logical output value from the logic gate 105 at the output node 120 .
- Subsequent logic (not shown) coupled to the dynamic circuit at the node 145 , for example, may use the logical output value at the node 120 as an input.
- a soft error at the node 120 could cause incorrect data to be supplied to the subsequent logic.
- a hardening capacitor 150 is coupled to the keeper circuit 1 10 at the feedback node 130 .
- the hardening capacitor 150 operates to slow down a feedback path within the keeper circuit 110 such that the gate 135 is on longer to maintain charge at the node 120 .
- a critical charge (Qcrit) at the node 120 is effectively increased such that the node 120 is less prone to soft errors.
- Qcrit critical charge
- the above-mentioned feedback path or loop is indicated by the dotted line 155 and includes the inverter 125 and the PMOS keeper device 135 . If the node 120 is at a logical low level, the feedback path through the keeper circuit would, instead, include the inverter 125 and the NMOS keeper device 140 as indicated by the dotted line 160 . Because the dynamic logic gate 105 is a domino gate for the example shown in FIG. 1, and domino gates more typically exhibit soft errors that cause an erroneous transition from a logic high level to a logic low level, the examples described herein are focused on this type of error.
- the hardening capacitor 150 may also be used, however, to harden dynamic circuits against soft errors that cause erroneous low to high transitions.
- Qcrit at the output node 120 can be increased to harden the dynamic circuit 100 against soft errors without increasing the signal delay from the CLK and data (A,B,C) inputs to the node 145 .
- These clock and data signal output paths determine the speed of the dynamic circuit 100 with respect to surrounding logic.
- the increase in Qcrit for this approach depends on several factors including the capacitance of the hardening capacitor 150 , the sizes of the keeper devices 135 and/or 140 , and the equivalent capacitance at the output node 120 .
- the hardening capacitor 150 is a 5.6 ⁇ m by 0.4 ⁇ m gate capacitance.
- other types of capacitors and/or different capacitance values may be used.
- the larger the capacitance provided by the hardening capacitor 150 the larger the increase in Qcrit.
- an integrated circuit designer may balance a desired increase in Qcrit versus a resultant reduction in slope of signals at the feedback node 130 caused by the addition of the hardening capacitor 150 . If the slope at the feedback node 130 becomes too gradual, the time to turn on or turn off the keeper devices 135 and/or 140 becomes too long such that the performance of the circuit 100 may be adversely affected. Other factors such as the particular process being used, the area penalty that can be tolerated, etc. may also be considered.
- one of the keeper device 135 or 140 may be sized to further fight charge loss at the output node 120 .
- the PMOS keeper device 135 may be sized to increase its pull-up strength.
- the NMOS keeper device 140 may be sized to increase its pull-down strength.
- both pull-up and pull-down keeper devices may be sized in the above-described manner.
- the hardening capacitor 150 coupled to the keeper circuit feedback node 130 in conjunction with sizing of one or more of the keepers 135 and/or 140 can significantly improve Qcrit at the output node 120 with limited performance loss.
- Increasing the strength of one or more of the keepers 135 and/or 140 increases delay in the path between the CLK input and the node 145 and the path between the data inputs A, B and C and the node 145 .
- the extent to which the keeper(s) 135 and/or 140 are resized will depend, at least in part, on the delay that can be tolerated in the clock and/or data output paths (i.e. CLK to node 145 and inputs A, B and C to node 145 ).
- the PMOS keeper 135 may, for example, be resized from 0.56/0.6 ⁇ m (width/channel length) to 0.76/0.4 ⁇ m to provide increased pull-up strength and a higher Qcrit at the output node 120 to harden the circuit 100 against erroneous high to low transitions. It will be appreciated that the above dimensions are exemplary and that different dimensions for the PMOS keeper device 135 may be used depending upon tolerable delay and additional factors such as the particular circuit in which the keeper is included, the desired Qcrit at the output node 120 , space considerations, etc. Similar considerations may be taken into account in sizing the NMOS keeper device 140 .
- a keeper device in the half keeper may be sized in a similar manner to improve Qcrit at the output node 120 .
- the inverter 125 in the feedback loop(s) 155 and 160 may be sized to reduce its driving strength. For example, where the widths of the devices in the inverter 125 are not at a minimum width for the process used to fabricate the circuit 100 , this width may be reduced. Where the widths of the devices in the inverter 125 are at the minimum width for the process, the channel length of the devices can be increased. Either approach results in reduced driving strength of the inverter 125 . By reducing the driving strength of the inverter 125 , the feedback path(s) 155 and/or 160 in the keeper circuit 110 are slowed down such that Qcrit at the node 120 is increased as described above.
- Reducing the driving strength of the inverter 125 by increasing its channel length may increase the overall loading capacitance at the output node 120 to a certain extent. For some embodiments, it may be possible to compensate for this effect by reducing the size of the inverter 115 . Where this additional loading capacitance is not compensated for, a slight delay penalty may be introduced into the clock and data output paths. Available area and tolerance for delay balanced against a desired increase in Qcrit may be considered when determining sizing of the inverter 125 .
- FIG. 2 is a schematic diagram showing a dynamic circuit 200 of another embodiment.
- the dynamic circuit 200 like the circuit 100 includes a dynamic logic gate 205 , a keeper circuit 210 , an interface inverter 215 (or another type of interface gate such as a complex gate), and an output node 220 .
- the dynamic logic gate 205 is also a three-input domino NAND gate in this example, but may be any type of dynamic logic gate.
- the keeper circuit 210 is configured to increase Qcrit at the output node 220 without the addition of a hardening capacitor.
- an inverter 225 in the feedback loop(s) of the keeper circuit 210 is sized to reduce its driving strength as described above in reference to the inverter 125 of FIG. 1.
- reducing the driving strength of the inverter 225 by increasing its channel length can increase the loading capacitance at the output node 220 .
- This increased loading capacitance may introduce a small delay in a clock output path from a CLK signal to a node 245 and a data output path from data inputs A, B and C to the node 245 . It may be possible, for some embodiments, to compensate for this delay by adjusting the sizing of the interface inverter 215 .
- one or more keeper devices 235 and/or 240 in the keeper circuit are sized to increase Qcrit in the manner described above in reference to the keeper devices 135 and/or 140 of FIG. 1. Similar to the keeper device 135 and 140 , this sizing may also increase the delay in the clock and data output paths. This increased delay may be taken into account when determining the desired size of the keeper device(s) 235 and/or 240 .
- decreasing the driving strength of the inverter 225 operates to delay the feedback loop(s) 255 and/or 260 through the keeper circuit 210 .
- Delaying the feedback loop(s) in the keeper circuit 210 fights against changes in charge at the output node 220 such that Qcrit at the node 220 is increased.
- Increasing the strength of the either or both of the keeper devices 235 and/or 240 also serves to fight against changes in charge to increase Qcrit at the output node 220 . This increase in Qcrit in accordance with the above-described embodiments is provided while incurring relatively small delays in the clock and data output paths.
- Various embodiments may be used to harden dynamic circuits by increasing Qcrit while introducing little, if any delay penalty. This increase in Qcrit can further be accomplished without adding additional processing steps. Increases in area that may result from circuits in accordance with various embodiments may be balanced by an integrated circuit designer against desired increases in Qcrit.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
Description
- 1. Field
- An embodiment of the present invention relates to the field of integrated circuits and, more particularly, to reducing soft errors in integrated circuits that include dynamic circuits.
- 2. Discussion of Related Art
- Dynamic circuits, such as domino circuits, for example, are widely used in high-speed integrated circuit designs. This is because dynamic circuits typically provide area and speed advantages over corresponding static complementary metal oxide semiconductor (CMOS) circuits.
- Dynamic circuits, however, are more vulnerable to soft errors as compared to their static counterparts. A soft error is a transient, single event upset that changes the state of a circuit node or other internal storage element. Soft errors may, for example, be caused by alpha particles or cosmic rays impinging on the integrated circuit device.
- Alpha particles are charged particles that may originate from the decay of trace impurities in integrated circuit packaging materials, for example. Cosmic rays may include heavy ions and protons that, either directly or indirectly, may have an ionization effect within the integrated circuit device semiconductor material. In either case, the charged particles from these sources may change the charge at an integrated circuit node such that the node actually transitions to an opposite logical state.
- The critical charge (Qcrit) at a node is an indication of the susceptibility of the node to such soft errors. Qcrit is the minimum charge beyond which operation of a circuit will be affected. Thus, if an ion strike causes charge collected at a node to exceed Qcrit, the node may erroneously transition from a logical one state to a logical zero state, for example.
- As integrated circuit fabrication technologies continue to scale down into the submicron region, less charge is stored on integrated circuit nodes and thus, less energy is needed to change the state of a node. For this reason, integrated circuit devices are becoming increasingly susceptible to soft error failures.
- One approach to addressing this issue has been to add error detection and/or correction circuitry to integrated circuit designs. This approach may be used in memory design, for example. Error detection and/or correction circuitry identifies circuit errors such that resulting issues may be mitigated while correction circuitry may compensate for the error. Such approaches, while preventing some circuit failures, can involve significant additional circuitry that takes up valuable semiconductor real estate. Additionally, such approaches may not be viable for dynamic circuits in speed critical paths, for example.
- Other approaches may involve processing changes. For some dynamic random access memory (DRAM) cells, for example, gate oxide thicknesses are decreased to store additional charge. This approach, however, may lead to an increase in other types of failures due to increased defects in the thinner gate oxide.
- Other processing changes such as use of trench-capacitor structures, and applying a coating of a radioactive-contaminant-free polymer on top of an integrated circuit have also been used in an effort to reduce soft errors. Such processing changes may be undesirable because they add one or more additional processing steps involving additional time and expense. Further such approaches may not reduce soft errors to the extent desired.
- A method and apparatus for reducing soft errors in a dynamic circuit are described. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
- Other features and advantages of the present invention will be appreciated from the accompanying drawings and from the detailed description that follows below.
- The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which:
- FIG. 1 is a schematic diagram of a dynamic circuit in accordance with one embodiment.
- FIG. 2 is a schematic diagram of a dynamic circuit in accordance with an alternative embodiment.
- A method and apparatus for reducing soft errors in dynamic circuits is described. In the following description, particular types of integrated circuits and integrated circuit configurations are described for purposes of illustration. It will be appreciated, however, that other embodiments are applicable to other types of integrated circuits and to integrated circuits configured in another manner.
- FIG. 1 is a schematic diagram of a
dynamic circuit 100 in accordance with one embodiment. Thedynamic circuit 100 includes adynamic logic gate 105, akeeper circuit 110, and an interface inverter 115 (or another type of interface gate such as a complex gate). - The
dynamic logic gate 105 for the example shown in FIG. 1 is a three-input domino NAND gate, however, other types of dynamic logic gates, including other types of domino gates, may also benefit from various embodiments of the invention. Thedynamic logic gate 105 includes data inputs A, B and C and a clock input CLK. Output data from thedynamic logic gate 105 is provided at anoutput node 120, which may also be referred to as a precharge node. During a precharge phase, the output/precharge node 120 may be precharged to a predetermined level (a logical high level in this example) and during an evaluate phase, an output value may be read at thenode 120. - The
keeper circuit 110 includes afirst inverter 125 having an input coupled to theoutput node 120 and an output coupled to afeedback node 130. Also coupled to thefeedback node 130 is an input of a second inverter including a p-channel metal oxide semiconductor (PMOS)keeper device 135 and an n-channel MOS (NMOS) keeper device 140. An output of the second inverter is coupled to theoutput node 120. - The
keeper circuit 110 operates to maintain a voltage level at theoutput node 120. In operation, thekeeper circuit 110 supplies charge to compensate for loss of charge at theoutput node 120 due to various leakage paths and capacitive coupling of theoutput node 120 to other signal paths. Thekeeper circuit 110 of FIG. 1 is a full keeper (i.e. it is switchable to maintain theoutput node 120 at either a logical high or a logical low level). For other embodiments, a half keeper circuit that only maintains the output node at one level (either high or low) may be used in place of thefull keeper 110. - The
interface inverter 115 for the exemplary circuit shown in FIG. 1 is a gate that provides an interface to subsequent logic (not shown). Theinterface inverter 115 may be provided, for example, so that a domino circuit coupled to thedynamic circuit 100 is in a precharge phase while thedynamic circuit 100 is in an evaluate phase to ensure proper operation of the coupled circuits. Theinterface inverter 115 may be a high-skewed gate for one embodiment such that transitions in a particular direction are favored. - As mentioned above, the
dynamic circuit 100 provides a logical output value from thelogic gate 105 at theoutput node 120. Subsequent logic (not shown) coupled to the dynamic circuit at thenode 145, for example, may use the logical output value at thenode 120 as an input. Thus, a soft error at thenode 120 could cause incorrect data to be supplied to the subsequent logic. - For one embodiment, to harden the
dynamic circuit 100 such that it is less prone to soft errors, a hardeningcapacitor 150 is coupled to thekeeper circuit 1 10 at thefeedback node 130. The hardeningcapacitor 150 operates to slow down a feedback path within thekeeper circuit 110 such that thegate 135 is on longer to maintain charge at thenode 120. In this manner, a critical charge (Qcrit) at thenode 120 is effectively increased such that thenode 120 is less prone to soft errors. In other words, with a higher Qcrit, a larger amount of charge would have to be generated by an alpha particle, proton or heavy ion to cause a soft error as compared to a similar circuit without the hardeningcapacitor 150. - For a logical high output at the
node 120, the above-mentioned feedback path or loop is indicated by the dottedline 155 and includes theinverter 125 and thePMOS keeper device 135. If thenode 120 is at a logical low level, the feedback path through the keeper circuit would, instead, include theinverter 125 and the NMOS keeper device 140 as indicated by the dottedline 160. Because thedynamic logic gate 105 is a domino gate for the example shown in FIG. 1, and domino gates more typically exhibit soft errors that cause an erroneous transition from a logic high level to a logic low level, the examples described herein are focused on this type of error. The hardeningcapacitor 150 may also be used, however, to harden dynamic circuits against soft errors that cause erroneous low to high transitions. - Using the above approach, Qcrit at the
output node 120 can be increased to harden thedynamic circuit 100 against soft errors without increasing the signal delay from the CLK and data (A,B,C) inputs to thenode 145. These clock and data signal output paths determine the speed of thedynamic circuit 100 with respect to surrounding logic. - The increase in Qcrit for this approach depends on several factors including the capacitance of the hardening
capacitor 150, the sizes of thekeeper devices 135 and/or 140, and the equivalent capacitance at theoutput node 120. For one embodiment, the hardeningcapacitor 150 is a 5.6 μm by 0.4 μm gate capacitance. For other embodiments, however, other types of capacitors and/or different capacitance values may be used. - In general, the larger the capacitance provided by the hardening
capacitor 150, the larger the increase in Qcrit. In determining the size of the hardeningcapacitor 150, an integrated circuit designer may balance a desired increase in Qcrit versus a resultant reduction in slope of signals at thefeedback node 130 caused by the addition of the hardeningcapacitor 150. If the slope at thefeedback node 130 becomes too gradual, the time to turn on or turn off thekeeper devices 135 and/or 140 becomes too long such that the performance of thecircuit 100 may be adversely affected. Other factors such as the particular process being used, the area penalty that can be tolerated, etc. may also be considered. - For another embodiment, to further increase Qcrit at the
output node 120, one of thekeeper device 135 or 140 may be sized to further fight charge loss at theoutput node 120. If the concern is for soft errors that cause erroneous transitions from a logic high to a logic low state, for example, thePMOS keeper device 135 may be sized to increase its pull-up strength. To harden thecircuit 100 against soft errors that cause transitions from a logic low to a logic high state, the NMOS keeper device 140 may be sized to increase its pull-down strength. For some embodiments, both pull-up and pull-down keeper devices may be sized in the above-described manner. - Use of the hardening
capacitor 150 coupled to the keepercircuit feedback node 130 in conjunction with sizing of one or more of thekeepers 135 and/or 140 can significantly improve Qcrit at theoutput node 120 with limited performance loss. Increasing the strength of one or more of thekeepers 135 and/or 140 increases delay in the path between the CLK input and thenode 145 and the path between the data inputs A, B and C and thenode 145. Thus, the extent to which the keeper(s) 135 and/or 140 are resized will depend, at least in part, on the delay that can be tolerated in the clock and/or data output paths (i.e. CLK tonode 145 and inputs A, B and C to node 145). - The
PMOS keeper 135 may, for example, be resized from 0.56/0.6 μm (width/channel length) to 0.76/0.4 μm to provide increased pull-up strength and a higher Qcrit at theoutput node 120 to harden thecircuit 100 against erroneous high to low transitions. It will be appreciated that the above dimensions are exemplary and that different dimensions for thePMOS keeper device 135 may be used depending upon tolerable delay and additional factors such as the particular circuit in which the keeper is included, the desired Qcrit at theoutput node 120, space considerations, etc. Similar considerations may be taken into account in sizing the NMOS keeper device 140. - Where a half keeper is used instead of a full keeper, a keeper device in the half keeper may be sized in a similar manner to improve Qcrit at the
output node 120. - For another embodiment, in addition to, or instead of, sizing one or more of the
keeper devices 135 and/or 140, theinverter 125 in the feedback loop(s) 155 and 160 may be sized to reduce its driving strength. For example, where the widths of the devices in theinverter 125 are not at a minimum width for the process used to fabricate thecircuit 100, this width may be reduced. Where the widths of the devices in theinverter 125 are at the minimum width for the process, the channel length of the devices can be increased. Either approach results in reduced driving strength of theinverter 125. By reducing the driving strength of theinverter 125, the feedback path(s) 155 and/or 160 in thekeeper circuit 110 are slowed down such that Qcrit at thenode 120 is increased as described above. - Reducing the driving strength of the
inverter 125 by increasing its channel length may increase the overall loading capacitance at theoutput node 120 to a certain extent. For some embodiments, it may be possible to compensate for this effect by reducing the size of theinverter 115. Where this additional loading capacitance is not compensated for, a slight delay penalty may be introduced into the clock and data output paths. Available area and tolerance for delay balanced against a desired increase in Qcrit may be considered when determining sizing of theinverter 125. - FIG. 2 is a schematic diagram showing a
dynamic circuit 200 of another embodiment. Thedynamic circuit 200, like thecircuit 100 includes adynamic logic gate 205, akeeper circuit 210, an interface inverter 215 (or another type of interface gate such as a complex gate), and anoutput node 220. Thedynamic logic gate 205 is also a three-input domino NAND gate in this example, but may be any type of dynamic logic gate. - For the embodiment shown in FIG. 2, the
keeper circuit 210 is configured to increase Qcrit at theoutput node 220 without the addition of a hardening capacitor. For this embodiment, aninverter 225 in the feedback loop(s) of thekeeper circuit 210 is sized to reduce its driving strength as described above in reference to theinverter 125 of FIG. 1. - As described in reference to FIG. 1, reducing the driving strength of the
inverter 225 by increasing its channel length can increase the loading capacitance at theoutput node 220. This increased loading capacitance may introduce a small delay in a clock output path from a CLK signal to anode 245 and a data output path from data inputs A, B and C to thenode 245. It may be possible, for some embodiments, to compensate for this delay by adjusting the sizing of theinterface inverter 215. - For an alternative embodiment, instead of, or in addition to, sizing the
inverter 225, one ormore keeper devices 235 and/or 240 in the keeper circuit are sized to increase Qcrit in the manner described above in reference to thekeeper devices 135 and/or 140 of FIG. 1. Similar to thekeeper device 135 and 140, this sizing may also increase the delay in the clock and data output paths. This increased delay may be taken into account when determining the desired size of the keeper device(s) 235 and/or 240. - As described above in reference to FIG. 1, decreasing the driving strength of the
inverter 225 operates to delay the feedback loop(s) 255 and/or 260 through thekeeper circuit 210. Delaying the feedback loop(s) in thekeeper circuit 210 fights against changes in charge at theoutput node 220 such that Qcrit at thenode 220 is increased. Increasing the strength of the either or both of thekeeper devices 235 and/or 240 also serves to fight against changes in charge to increase Qcrit at theoutput node 220. This increase in Qcrit in accordance with the above-described embodiments is provided while incurring relatively small delays in the clock and data output paths. - The above-described approaches for increasing Qcrit and thus, hardening dynamic circuits to reduce soft errors, may be used for any type of dynamic circuit in an integrated circuit such as a microprocessor, for example. For some embodiments, it may be desirable to identify particular dynamic circuits that may be more prone to soft errors and employ one or more of the described hardening techniques only to such circuits. These particular dynamic circuits may be the circuits that include smaller devices such that it is more difficult to maintain charge on internal nodes, for example.
- Various embodiments may be used to harden dynamic circuits by increasing Qcrit while introducing little, if any delay penalty. This increase in Qcrit can further be accomplished without adding additional processing steps. Increases in area that may result from circuits in accordance with various embodiments may be balanced by an integrated circuit designer against desired increases in Qcrit.
- Increasing Qcrit in the manner described above reduces the susceptibility of dynamic circuits to soft errors and thus, reduces the soft error Failures In Time (FIT) rate associated with devices that include such circuits. Reducing the soft error FIT rate improves integrated circuit reliability and thus, reduces manufacturing and other costs.
- In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be appreciated that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (19)
1. A dynamic circuit comprising:
a dynamic logic gate having an output node at which a logical output value of the logic gate is detected; and
a keeper circuit coupled to the output node, the keeper circuit being configured to harden the dynamic circuit by increasing the critical charge at the output node.
2. The dynamic circuit of further comprising:
claim 1
a hardening capacitor coupled to a feedback node of the keeper circuit, the hardening capacitor to slow down a feedback path in the keeper circuit.
3. The dynamic circuit of wherein the keeper circuit comprises:
claim 1
a first inverter coupled between the output node and a feedback node, the first inverter being sized to reduce a driving strength of the inverter to slow down the feedback path in the keeper circuit.
4. The dynamic circuit of further comprising:
claim 3
an interface gate coupled to the output node, the interface gate being sized to compensate for a delay introduced by the sized first inverter.
5. The dynamic circuit of wherein the keeper circuit comprises:
claim 1
a keeper device that is sized to increase its strength to fight against charge loss at the output node.
6. The dynamic circuit of wherein the keeper circuit comprises:
claim 2
a keeper device coupled to the hardening capacitor, the keeper device being sized to further increase critical charge at the output node.
7. The dynamic circuit of wherein
claim 6
the dynamic logic gate is a domino gate, and
the keeper device is a PMOS keeper device such that the output node is hardened against erroneous logic high to logic low transitions by increasing the critical charge.
8. The dynamic circuit of wherein the keeper circuit further comprises:
claim 3
a keeper device coupled to the first inverter, the keeper device being sized to further increase critical charge at the output node.
9. A circuit comprising:
a dynamic logic gate having an output node at which a logical output value of the dynamic logic gate is detected;
a keeper circuit coupled to the output node, the keeper circuit including a feedback node; and
a hardening capacitor coupled to the feedback node, the hardening capacitor to harden the circuit against soft errors.
10. The circuit of wherein the keeper circuit comprises:
claim 9
a keeper device having an input coupled to the feedback node, the keeper device being sized to fight against changes in charge at the output node.
11. The circuit of wherein
claim 10
the dynamic logic gate is a domino gate, and
the keeper device is a PMOS keeper device.
12. The circuit of wherein the keeper device is an NMOS keeper device.
claim 10
13. The circuit of wherein the keeper circuit further comprises:
claim 10
an inverter coupled between the output node and the feedback node, the inverter being sized to reduce its driving strength to further harden the circuit.
14. The circuit of further comprising:
claim 13
an interface gate coupled to the output node, the interface gate being sized to compensate for an increase in load capacitance provided by the sized inverter.
15. The circuit of wherein the interface gate is an inverter.
claim 14
16. A method for reducing soft errors in a dynamic circuit, the method comprising:
configuring a keeper circuit of the dynamic circuit to increase the critical charge at an output node of the circuit.
17. The method of wherein increasing the delay comprises coupling a hardening capacitance to a feedback node of the keeper circuit.
claim 16
18. A method comprising:
using a hardening capacitor coupled to a feedback node of a keeper circuit in a dynamic circuit to harden the dynamic circuit against soft errors.
19. The method of further comprising:
claim 18
further hardening the dynamic circuit with a keeper device that is sized to fight charge loss at an output node of the dynamic circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/909,104 US6351151B2 (en) | 1999-12-23 | 2001-07-18 | Method and apparatus for reducing soft errors in dynamic circuits |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/471,650 US6292029B1 (en) | 1999-12-23 | 1999-12-23 | Method and apparatus for reducing soft errors in dynamic circuits |
US09/909,104 US6351151B2 (en) | 1999-12-23 | 2001-07-18 | Method and apparatus for reducing soft errors in dynamic circuits |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/471,650 Continuation US6292029B1 (en) | 1999-12-23 | 1999-12-23 | Method and apparatus for reducing soft errors in dynamic circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010040467A1 true US20010040467A1 (en) | 2001-11-15 |
US6351151B2 US6351151B2 (en) | 2002-02-26 |
Family
ID=23872482
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/471,650 Expired - Lifetime US6292029B1 (en) | 1999-12-23 | 1999-12-23 | Method and apparatus for reducing soft errors in dynamic circuits |
US09/909,104 Expired - Lifetime US6351151B2 (en) | 1999-12-23 | 2001-07-18 | Method and apparatus for reducing soft errors in dynamic circuits |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/471,650 Expired - Lifetime US6292029B1 (en) | 1999-12-23 | 1999-12-23 | Method and apparatus for reducing soft errors in dynamic circuits |
Country Status (1)
Country | Link |
---|---|
US (2) | US6292029B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060163635A1 (en) * | 2005-01-26 | 2006-07-27 | International Business Machines Corporation | Capacitor below the buried oxide of soi cmos technologies for protection against soft errors |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7015300B2 (en) * | 1995-06-07 | 2006-03-21 | Acushnet Company | Multilayered golf ball and composition |
JP3533357B2 (en) * | 2000-02-29 | 2004-05-31 | 株式会社東芝 | Semiconductor integrated circuit with logical operation function |
US6396305B1 (en) * | 2001-03-29 | 2002-05-28 | Intel Corporation | Digital leakage compensation circuit |
US6723597B2 (en) | 2002-07-09 | 2004-04-20 | Micron Technology, Inc. | Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same |
US6986078B2 (en) * | 2002-08-07 | 2006-01-10 | International Business Machines Corporation | Optimization of storage and power consumption with soft error predictor-corrector |
US6794901B2 (en) * | 2002-08-29 | 2004-09-21 | International Business Machines Corporation | Apparatus for reducing soft errors in dynamic circuits |
US6954916B2 (en) * | 2003-06-30 | 2005-10-11 | International Business Machines Corporation | Methodology for fixing Qcrit at design timing impact |
EP1709476A4 (en) * | 2003-09-26 | 2010-08-04 | Tidal Photonics Inc | Apparatus and methods relating to expanded dynamic range imaging endoscope systems |
US7263631B2 (en) * | 2004-08-13 | 2007-08-28 | Seakr Engineering, Incorporated | Soft error detection and recovery |
US7157962B2 (en) * | 2004-09-13 | 2007-01-02 | Texas Instruments Incorporated | Charge pump output device with leakage cancellation |
US7679403B2 (en) * | 2005-11-08 | 2010-03-16 | Honeywell International Inc. | Dual redundant dynamic logic |
US7365587B2 (en) * | 2006-04-07 | 2008-04-29 | Freescale Semiconductor, Inc. | Contention-free keeper circuit and a method for contention elimination |
US7804320B2 (en) * | 2008-06-13 | 2010-09-28 | University Of South Florida | Methodology and apparatus for reduction of soft errors in logic circuits |
US8397204B2 (en) | 2010-12-21 | 2013-03-12 | Ryerson University | System and methodology for development of a system architecture using optimization parameters |
US9948282B2 (en) * | 2015-01-15 | 2018-04-17 | Mediatek Inc. | Low-power retention flip-flops |
JP2021082879A (en) * | 2019-11-15 | 2021-05-27 | 富士電機株式会社 | Logic circuit and circuit chip |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4040015A (en) * | 1974-04-16 | 1977-08-02 | Hitachi, Ltd. | Complementary mos logic circuit |
JPS6342216A (en) * | 1986-08-08 | 1988-02-23 | Hitachi Ltd | Composite circuit containing bipolar transistor and field effect transistor |
US5144163A (en) * | 1988-03-14 | 1992-09-01 | Matsushita Electric Industrial Co., Ltd. | Dynamic BiCMOS logic gates |
US5065048A (en) * | 1988-09-19 | 1991-11-12 | Hitachi, Ltd. | Semiconductor logic circuit with noise suppression circuit |
US5103113A (en) * | 1990-06-13 | 1992-04-07 | Texas Instruments Incorporated | Driving circuit for providing a voltage boasted over the power supply voltage source as a driving signal |
GB2285516B (en) * | 1994-01-05 | 1997-07-30 | Hewlett Packard Co | Quiescent current testing of dynamic logic systems |
US6111434A (en) * | 1997-07-21 | 2000-08-29 | International Business Machines Corporation | Circuit having anti-charge share characteristics and method therefore |
US6191618B1 (en) * | 1999-07-23 | 2001-02-20 | Intel Corporation | Contention-free, low clock load domino circuit topology |
-
1999
- 1999-12-23 US US09/471,650 patent/US6292029B1/en not_active Expired - Lifetime
-
2001
- 2001-07-18 US US09/909,104 patent/US6351151B2/en not_active Expired - Lifetime
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060163635A1 (en) * | 2005-01-26 | 2006-07-27 | International Business Machines Corporation | Capacitor below the buried oxide of soi cmos technologies for protection against soft errors |
US20070272961A1 (en) * | 2005-01-26 | 2007-11-29 | Aitken John M | Capacitor below the buried oxide of soi cmos technologies for protection against soft errors |
US7315075B2 (en) | 2005-01-26 | 2008-01-01 | International Business Machines Corporation | Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors |
US7388274B2 (en) | 2005-01-26 | 2008-06-17 | International Business Machines Corporation | Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors |
US20080191314A1 (en) * | 2005-01-26 | 2008-08-14 | International Busines Machines Corporation | Capacitor below the buried oxide of soi cmos technologies for protection against soft errors |
US7791169B2 (en) | 2005-01-26 | 2010-09-07 | International Business Machines Corporation | Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors |
Also Published As
Publication number | Publication date |
---|---|
US6292029B1 (en) | 2001-09-18 |
US6351151B2 (en) | 2002-02-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6292029B1 (en) | Method and apparatus for reducing soft errors in dynamic circuits | |
EP1844473B1 (en) | Radiation-hardened sram cell with write error protection | |
US7236001B2 (en) | Redundancy circuits hardened against single event upsets | |
US6326809B1 (en) | Apparatus for and method of eliminating single event upsets in combinational logic | |
WO2006004913A2 (en) | Single event upset immune keeper circuit and method for dual redundant dynamic logic | |
US6794901B2 (en) | Apparatus for reducing soft errors in dynamic circuits | |
US7834663B2 (en) | NAND/NOR registers | |
US20030179031A1 (en) | Data retaining circuit | |
US5541537A (en) | High speed static circuit design | |
US6826090B1 (en) | Apparatus and method for a radiation resistant latch | |
Shiyanovskii et al. | A low power memory cell design for SEU protection against radiation effects | |
US10535386B2 (en) | Level shifter with bypass | |
US6710627B2 (en) | Dynamic CMOS circuits with individually adjustable noise immunity | |
US5706237A (en) | Self-restore circuit with soft error protection for dynamic logic circuits | |
US7053663B2 (en) | Dynamic gate with conditional keeper for soft error rate reduction | |
US6504788B1 (en) | Semiconductor memory with improved soft error resistance | |
US10574236B2 (en) | Level shifter with bypass control | |
Chu et al. | A 25-ns low-power full-CMOS 1-Mbit (128 K* 8) SRAM | |
US5691652A (en) | Completion detection as a means for improving alpha soft-error resistance | |
US6377078B1 (en) | Circuit to reduce charge sharing for domino circuits with pulsed clocks | |
US11017848B2 (en) | Static random-access memory (SRAM) system with delay tuning and control and a method thereof | |
US6960941B2 (en) | Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits | |
US7230856B1 (en) | High-speed multiplexer latch | |
Oh et al. | A clock delayed sleep mode domino logic for wide dynamic OR gate | |
US6657471B1 (en) | High performance, low power differential latch |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |