US20010039108A1 - Method for forming gate - Google Patents

Method for forming gate Download PDF

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US20010039108A1
US20010039108A1 US09/901,211 US90121101A US2001039108A1 US 20010039108 A1 US20010039108 A1 US 20010039108A1 US 90121101 A US90121101 A US 90121101A US 2001039108 A1 US2001039108 A1 US 2001039108A1
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layer
tungsten silicide
annealing process
silicide layer
rapid thermal
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Jason Jenq
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation

Definitions

  • the present invention relates to a method for forming a gate. More particularly, the present invention relates to a method for forming a protective layer to protect a gate during a rapid thermal annealing process.
  • Tungsten silicide (WSi x ) is commonly used as a gate conductor in integrated circuits, especially for memory chips, due to its high thermal stability, low resistivity. low contamination levels and good step coverage.
  • the tungsten silicide layer which is usually formed by low pressure chemical vapor deposition (LPCVD) with dichlorosilane (SiH 2 Cl 2 ) and tungsten hexafluoride (WF 6 ) as a gas source, has many advantages—lower fluorine content, improved step coverage, lower post-annealed stress and better adhesion with other materials. Therefore, nowadays, the tungsten silicide layer is formed in the manner described above in some semiconductor processes.
  • a nitride layer serving as a cap layer of the gate structure is usually formed on a tungsten silicide layer after a doped polysilicon layer and a tungsten silicide layer are formed on a substrate in sequence.
  • the nitride layer is formed by low pressure chemical vapor deposition at about 700-800° C.
  • the LPCVD chamber is a vertical furnace without a load lock, so oxygen contamination can occur during wafer loading.
  • the tungsten silicide layer is in an oxidizing atmosphere at a high temperature, silicon dioxide (SiO 2 ) is formed during the process of forming the nitride layer as long as the silicon content of the tungsten silicide layer is adequate.
  • silicon dioxide SiO 2
  • WSi x is decomposed; thus, SiO 2 , elemental W, WO 2 , WO 3 , and other volatile tungsten oxides are formed.
  • Both WO 2 and WO 3 are volatile (the sublimation point for WO 2 is 800° C.) so that a cracking effect and a blistering effect occur in the tungsten silicide layer.
  • a rapid thermal annealing process is performed.
  • the rapid thermal annealing process is usually performed in an oxygen atmosphere, and a temperature of the rapid thermal annealing process is raised to about 1000° C., quickly.
  • the rapid thermal annealing process oxidizes sidewalls of the gate structure to form an isolation structure which prevents the gate structure from coupling with a contact or other devices.
  • Oxide protrusions are also easily formed on the sidewalls of the tungsten silicide layer during the rapid thermal annealing process. Therefore, some regions of a subsequently formed spacer are thin or the oxide protrusions protrude from the spacer.
  • a portion of the gate structure under the thin region of the spacer may be exposed during the etching process.
  • wordline-to-bitline leakage occurs because the gate structure couples with a plug within the bit line contact hole. If these oxide protrusions protrude from the spacer and block the bit line contact hole, the conductive material does not easily fill the bit line contact hole. So, an open bitline contact problem generates.
  • Another function of the rapid thermal annealing process is to change the crystal structure and grain size of WSi x , so that sheet resistance of the tungsten silicide layer can be reduced.
  • the crystal structure of WSi x is transformed into a tetragonal structure by performing the rapid thermal annealing process at 700° C.; the sheet resistance of the tungsten silicide layer is decreased from 30 to 3 ohm/sq. after the rapid thermal annealing process.
  • the grain size of WSi x is less than 100 nm.
  • an agglomeration effect of the tungsten silicide layer easily occurs during the rapid thermal annealing process, and hence causes a narrow linewidth effect on the gate structure. Because of the agglomeration effect of the tungsten silicide layer, the surface of the tungsten silicide layer becomes rough, and the sheet resistance of the tungsten silicide layer is increased.
  • the invention provides a method for forming a gate.
  • two protective layers are respectively formed by performing two rapid thermal annealing processes, and the tungsten silicide layer is surrounded by the protective layers. So. degradation mechanisms, the abnormal WSi x oxidation effect, the cracking effect. the blistering effect and wordline-to-bitline leakage, are avoided.
  • the invention provides a method for forming a gate.
  • a gate oxide layer is formed on a substrate having an isolation structure, and a polysilicon layer is formed on the gate oxide layer.
  • a tungsten silicide layer is formed by low pressure chemical vapor deposition with dichlorosilane and tungsten hexafluoride as a gas source on the polysilicon layer.
  • the polysilicon layer and the tungsten silicide layer constitute a polycide layer.
  • a first rapid thermal annealing process is performed in an ammonia atmosphere to form a first protective layer on the tungsten silicide layer.
  • a nitride layer is formed by low pressure chemical vapor deposition on the first protective layer, and then a gate structure is defined.
  • the gate structure comprises the gate oxide layer.
  • a second rapid thermal annealing process is performed in an ammonia atmosphere to form a second protective layer on sidewalls of the gate oxide layer, the polysilicon layer and the tungsten silicide layer.
  • a spacer is formed and abuts the sidewalls of the first and second protective layers, and the nitride layer.
  • two rapid thermal annealing processes are respectively performed in an ammonia atmosphere, and respectively form protective layers; thus, the tungsten silicide layer is surrounded by protective layers. Because of the protective layer on the tungsten silicide layer, the abnormal WSi x oxidation effect that usually occur during the process of forming the nitride layer is avoided, therefore the cracking effect and the blistering effect are also avoided. Wordline-to-bitline leakage and the open bitline contact problem are avoided due to the other protective layer on the sidewalls of the tungsten silicide layer. Furthermore, the rapid thermal annealing processes are performed in an ammonia atmosphere, so the agglomeration effect does not occur.
  • the sheet resistance of the tungsten silicide layer is reduced and the surface of the tungsten silicide layer is planar.
  • the protective layers protect the tungsten silicide layer from chemical attack during cleaning processes. Moreover, the protective layers avoid loss of dopants from the polycide layer.
  • FIGS. 1A through 1E are schematic, cross-sectional views showing the progression of manufacturing steps for a gate according to one preferred embodiment of this invention.
  • FIG. 2 shows a curve of sheet resistance of a tungsten silicide layer vs. rapid thermal annealing temperature.
  • a substrate 100 having an isolation structure 104 is provided, wherein the isolation structure 104 is a shallow trench isolation (STI), for example.
  • STI shallow trench isolation
  • impurities are implanted into the substrate 100 .
  • a gate oxide layer 106 is formed on the substrate 100 .
  • a polysilicon layer 108 which is preferably doped, is formed on the gate oxide layer 106 ; a tungsten silicide layer 110 is formed on the polysilicon layer 108 .
  • the polysilicon layer 108 and the tungsten silicide layer 110 constitute a polycide layer 112 .
  • the polysilicon layer 108 is preferably formed by chemical vapor deposition; the thickness of the polysilicon layer 108 is about 500-1000 ⁇ .
  • a low pressure chemical vapor deposition process is performed to form the tungsten silicide layer 110 by using a gas source includes dichlorosilane (SiH 2 Cl 2 ) and tungsten hexafluoride (WF 6 ).
  • a rapid thermal annealing process is performed in an ammonia (NH 3 ) atmosphere to form a protective layer 114 a on the tungsten silicide layer 110 .
  • the preferably rapid thermal annealing process is described as having the following steps. First, a first annealing process is performed at a temperature of about 750-850° C. for a duration of about 25-35 seconds, and then a second annealing process is performed at a temperature of about 950-1050° C. for a duration of about 5-15 seconds.
  • the protective layer 114 a is made from a material such as nitride.
  • a nitride layer 116 is formed on the protective layer 114 a . and then a gate structure 118 is defined by photolithography and etching.
  • the gate structure 118 comprises the gate oxide layer 106 , the polysilicon layer 108 , the tungsten silicide layer 110 , the protective layer 114 a and the nitride layer 116 .
  • the nitride layer 116 is formed, for example, by low pressure chemical vapor deposition; the thickness of the nitride layer 116 is about 1400-1600 ⁇ .
  • the process of forming the nitride layer 116 should be performed at a high temperature, the quality of the tungsten silicide layer 110 is still ensured because of the protective layer 114 a on the tungsten silicide layer 110 .
  • the abnormal WSi x oxidation effect is avoided, so that the cracking effect and the blistering effect are also avoided.
  • another rapid thermal annealing process is performed in an ammonia atmosphere to form a protective layer 114 b such as nitride on sidewalls of the gate oxide layer 106 , the polysilicon layer 108 and the tungsten silicide layer 110 .
  • a protective layer 114 b such as nitride on sidewalls of the gate oxide layer 106 , the polysilicon layer 108 and the tungsten silicide layer 110 .
  • the rapid thermal annealing process including two steps is described as follows. First, an annealing process is performed at a temperature about 750-850° C. for a duration of about 25-35 seconds, and then another annealing process is performed at a temperature about 950-1050° C. for a duration of about 5-15 seconds.
  • a spacer 120 is formed and abuts the sidewalls of the protective layers 114 a , 114 b and the nitride layer 116 .
  • the formation of the spacer 120 is described as follows.
  • a conformal oxide layer (not shown in FIG. 1E) is formed, for example, by low pressure chemical vapor deposition.
  • An etch-back process is performed to remove a portion of the oxide layer; thus the spacer 120 is formed on the sidewalls of the protective layers 114 a , 114 b and the nitride layer 116 .
  • the tungsten silicide layer 110 is surrounded by the protective layers 114 a , 114 b , oxide protrusions are not formed on the sidewalls of the tungsten silicide layer 110 ; thus, the thickness of the spacer 120 is uniform. As a result, wordline-to-bitline leakage and the open bitline contact problem are avoided. Additionally, the rapid thermal annealing process is performed in an ammonia atmosphere. Therefore, the agglomeration effect does not occur; i.e. the sheet resistance of the tungsten silicide layer 110 can be reduced and the surface of the tungsten silicide layer 110 can be planar.
  • two rapid thermal annealing processes are respectively performed in an ammonia atmosphere, and the first and the second protective layers are formed respectively; thus, the tungsten silicide layer are surrounded by the protective layers. Because of the protective layer on the tungsten silicide layer, the abnormal WSi x oxidation effect that usually occurs during the process of forming the nitride layer is avoided, therefore the cracking effect and the blistering effect are also avoided. Wordline-to-bitline leakage and the open bitline contact problem are avoided due to the second protective layer on the sidewalls of the tungsten silicide layer. Furthermore, the rapid thermal annealing processes are performed in an ammonia atmosphere, so the agglomeration effect does not occur.
  • the sheet resistance of the tungsten silicide layer is reduced and the surface of the tungsten silicide layer is planar.
  • the protective layers protect the tungsten silicide layer from chemical attack during cleaning processes. Moreover, the protective layers avoid loss of dopants from the polycide layer.
  • two rapid thermal annealing processes in the invention help to change the grain size of WSi x , so that the sheet resistance of the tungsten silicide layer is reduced.
  • FIG. 2 shows a curve of sheet resistance of a tungsten silicide layer vs. rapid thermal annealing temperature.
  • curve 202 represents the sheet resistance of the tungsten silicide layer as a function of a rapid thermal annealing temperature in this invention. As shown in FIG. 2, the sheet resistance of the tungsten silicide layer is greatly decreased after performing the rapid thermal annealing process at above 700° C.

Abstract

A method for forming a gate. A gate oxide layer is formed on a substrate having an isolation structure, and a polysilicon layer is formed on the gate oxide layer. A tungsten silicide layer is formed by low pressure chemical vapor deposition with dichlorosilane and tungsten hexafluoride as a gas source on the polysilicon layer. The polysilicon layer and the tungsten silicide layer constitute a polycide layer. A first rapid thermal annealing process is performed in an ammonia atmosphere to form a first protective layer on the tungsten silicide layer. A nitride layer is formed by low pressure chemical vapor deposition on the first protective layer, and then a gate structure is defined. The gate oxide layer, the polysilicon layer, the tungsten silicide layer, the first protective layer and the nitride layer together constitute the gate structure. A second rapid thermal annealing process is performed in an ammonia atmosphere to form a second protective layer on sidewalls of the gate oxide layer, the polysilicon layer and the tungsten silicide layer. A spacer is formed and abuts the sidewalls of the first and second protective layers, and the nitride layer.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of Invention [0001]
  • The present invention relates to a method for forming a gate. More particularly, the present invention relates to a method for forming a protective layer to protect a gate during a rapid thermal annealing process. [0002]
  • 2. Description of Related Art [0003]
  • Tungsten silicide (WSi[0004] x) is commonly used as a gate conductor in integrated circuits, especially for memory chips, due to its high thermal stability, low resistivity. low contamination levels and good step coverage. The tungsten silicide layer, which is usually formed by low pressure chemical vapor deposition (LPCVD) with dichlorosilane (SiH2Cl2) and tungsten hexafluoride (WF6) as a gas source, has many advantages—lower fluorine content, improved step coverage, lower post-annealed stress and better adhesion with other materials. Therefore, nowadays, the tungsten silicide layer is formed in the manner described above in some semiconductor processes.
  • In the process of forming a gate structure, a nitride layer serving as a cap layer of the gate structure is usually formed on a tungsten silicide layer after a doped polysilicon layer and a tungsten silicide layer are formed on a substrate in sequence. The nitride layer is formed by low pressure chemical vapor deposition at about 700-800° C. The LPCVD chamber is a vertical furnace without a load lock, so oxygen contamination can occur during wafer loading. [0005]
  • Since the tungsten silicide layer is in an oxidizing atmosphere at a high temperature, silicon dioxide (SiO[0006] 2) is formed during the process of forming the nitride layer as long as the silicon content of the tungsten silicide layer is adequate. However, if the silicon content of the tungsten silicide layer is limited, an abnormal WSix oxidation effect occurs. Due to the abnormal WSix oxidation effect, WSix is decomposed; thus, SiO2, elemental W, WO2, WO3, and other volatile tungsten oxides are formed. Both WO2 and WO3 are volatile (the sublimation point for WO2 is 800° C.) so that a cracking effect and a blistering effect occur in the tungsten silicide layer.
  • After the gate structure is defined, a rapid thermal annealing process is performed. The rapid thermal annealing process is usually performed in an oxygen atmosphere, and a temperature of the rapid thermal annealing process is raised to about 1000° C., quickly. The rapid thermal annealing process oxidizes sidewalls of the gate structure to form an isolation structure which prevents the gate structure from coupling with a contact or other devices. Oxide protrusions are also easily formed on the sidewalls of the tungsten silicide layer during the rapid thermal annealing process. Therefore, some regions of a subsequently formed spacer are thin or the oxide protrusions protrude from the spacer. In a subsequent process of forming a bit line contact hole, a portion of the gate structure under the thin region of the spacer may be exposed during the etching process. As a result, wordline-to-bitline leakage occurs because the gate structure couples with a plug within the bit line contact hole. If these oxide protrusions protrude from the spacer and block the bit line contact hole, the conductive material does not easily fill the bit line contact hole. So, an open bitline contact problem generates. Another function of the rapid thermal annealing process is to change the crystal structure and grain size of WSi[0007] x, so that sheet resistance of the tungsten silicide layer can be reduced. For example, the crystal structure of WSix is transformed into a tetragonal structure by performing the rapid thermal annealing process at 700° C.; the sheet resistance of the tungsten silicide layer is decreased from 30 to 3 ohm/sq. after the rapid thermal annealing process. In addition, the grain size of WSix is less than 100 nm. However, an agglomeration effect of the tungsten silicide layer easily occurs during the rapid thermal annealing process, and hence causes a narrow linewidth effect on the gate structure. Because of the agglomeration effect of the tungsten silicide layer, the surface of the tungsten silicide layer becomes rough, and the sheet resistance of the tungsten silicide layer is increased.
    • SUMMARY OF THE INVENTION
  • The invention provides a method for forming a gate. In the method, two protective layers are respectively formed by performing two rapid thermal annealing processes, and the tungsten silicide layer is surrounded by the protective layers. So. degradation mechanisms, the abnormal WSi[0008] x oxidation effect, the cracking effect. the blistering effect and wordline-to-bitline leakage, are avoided.
  • The invention provides a method for forming a gate. A gate oxide layer is formed on a substrate having an isolation structure, and a polysilicon layer is formed on the gate oxide layer. A tungsten silicide layer is formed by low pressure chemical vapor deposition with dichlorosilane and tungsten hexafluoride as a gas source on the polysilicon layer. The polysilicon layer and the tungsten silicide layer constitute a polycide layer. A first rapid thermal annealing process is performed in an ammonia atmosphere to form a first protective layer on the tungsten silicide layer. A nitride layer is formed by low pressure chemical vapor deposition on the first protective layer, and then a gate structure is defined. The gate structure comprises the gate oxide layer. the polysilicon layer, the tungsten silicide layer, the first protective layer and the nitride layer. A second rapid thermal annealing process is performed in an ammonia atmosphere to form a second protective layer on sidewalls of the gate oxide layer, the polysilicon layer and the tungsten silicide layer. A spacer is formed and abuts the sidewalls of the first and second protective layers, and the nitride layer. [0009]
  • In the invention, two rapid thermal annealing processes are respectively performed in an ammonia atmosphere, and respectively form protective layers; thus, the tungsten silicide layer is surrounded by protective layers. Because of the protective layer on the tungsten silicide layer, the abnormal WSi[0010] x oxidation effect that usually occur during the process of forming the nitride layer is avoided, therefore the cracking effect and the blistering effect are also avoided. Wordline-to-bitline leakage and the open bitline contact problem are avoided due to the other protective layer on the sidewalls of the tungsten silicide layer. Furthermore, the rapid thermal annealing processes are performed in an ammonia atmosphere, so the agglomeration effect does not occur. As a result, the sheet resistance of the tungsten silicide layer is reduced and the surface of the tungsten silicide layer is planar. Additionally, the protective layers protect the tungsten silicide layer from chemical attack during cleaning processes. Moreover, the protective layers avoid loss of dopants from the polycide layer.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.[0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description. serve to explain the principles of the invention. In the drawings, [0012]
  • FIGS. 1A through 1E are schematic, cross-sectional views showing the progression of manufacturing steps for a gate according to one preferred embodiment of this invention; and [0013]
  • FIG. 2 shows a curve of sheet resistance of a tungsten silicide layer vs. rapid thermal annealing temperature.[0014]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Referring to FIG. 1A, a [0015] substrate 100 having an isolation structure 104 is provided, wherein the isolation structure 104 is a shallow trench isolation (STI), for example. In order to set the desired threshold voltage for the substrate 100, impurities are implanted into the substrate 100. A gate oxide layer 106 is formed on the substrate 100. A polysilicon layer 108, which is preferably doped, is formed on the gate oxide layer 106; a tungsten silicide layer 110 is formed on the polysilicon layer 108. The polysilicon layer 108 and the tungsten silicide layer 110 constitute a polycide layer 112. The polysilicon layer 108 is preferably formed by chemical vapor deposition; the thickness of the polysilicon layer 108 is about 500-1000 Å. Preferably, a low pressure chemical vapor deposition process is performed to form the tungsten silicide layer 110 by using a gas source includes dichlorosilane (SiH2Cl2) and tungsten hexafluoride (WF6).
  • Referring to FIG. 1B, a rapid thermal annealing process is performed in an ammonia (NH[0016] 3) atmosphere to form a protective layer 114 a on the tungsten silicide layer 110. The preferably rapid thermal annealing process is described as having the following steps. First, a first annealing process is performed at a temperature of about 750-850° C. for a duration of about 25-35 seconds, and then a second annealing process is performed at a temperature of about 950-1050° C. for a duration of about 5-15 seconds. The protective layer 114 a is made from a material such as nitride.
  • Referring to FIG. 1C, a [0017] nitride layer 116 is formed on the protective layer 114 a. and then a gate structure 118 is defined by photolithography and etching. The gate structure 118 comprises the gate oxide layer 106, the polysilicon layer 108, the tungsten silicide layer 110, the protective layer 114 a and the nitride layer 116. The nitride layer 116 is formed, for example, by low pressure chemical vapor deposition; the thickness of the nitride layer 116 is about 1400-1600 Å.
  • Although the process of forming the [0018] nitride layer 116 should be performed at a high temperature, the quality of the tungsten silicide layer 110 is still ensured because of the protective layer 114 a on the tungsten silicide layer 110. The abnormal WSix oxidation effect is avoided, so that the cracking effect and the blistering effect are also avoided.
  • Referring to FIG. 1D, another rapid thermal annealing process is performed in an ammonia atmosphere to form a [0019] protective layer 114 b such as nitride on sidewalls of the gate oxide layer 106, the polysilicon layer 108 and the tungsten silicide layer 110. For example, the rapid thermal annealing process including two steps is described as follows. First, an annealing process is performed at a temperature about 750-850° C. for a duration of about 25-35 seconds, and then another annealing process is performed at a temperature about 950-1050° C. for a duration of about 5-15 seconds.
  • Referring to FIG. 1E, a [0020] spacer 120 is formed and abuts the sidewalls of the protective layers 114 a, 114 b and the nitride layer 116. The formation of the spacer 120 is described as follows. A conformal oxide layer (not shown in FIG. 1E) is formed, for example, by low pressure chemical vapor deposition. An etch-back process is performed to remove a portion of the oxide layer; thus the spacer 120 is formed on the sidewalls of the protective layers 114 a, 114 b and the nitride layer 116.
  • Since the [0021] tungsten silicide layer 110 is surrounded by the protective layers 114 a, 114 b, oxide protrusions are not formed on the sidewalls of the tungsten silicide layer 110; thus, the thickness of the spacer 120 is uniform. As a result, wordline-to-bitline leakage and the open bitline contact problem are avoided. Additionally, the rapid thermal annealing process is performed in an ammonia atmosphere. Therefore, the agglomeration effect does not occur; i.e. the sheet resistance of the tungsten silicide layer 110 can be reduced and the surface of the tungsten silicide layer 110 can be planar.
  • In the invention, two rapid thermal annealing processes are respectively performed in an ammonia atmosphere, and the first and the second protective layers are formed respectively; thus, the tungsten silicide layer are surrounded by the protective layers. Because of the protective layer on the tungsten silicide layer, the abnormal WSi[0022] x oxidation effect that usually occurs during the process of forming the nitride layer is avoided, therefore the cracking effect and the blistering effect are also avoided. Wordline-to-bitline leakage and the open bitline contact problem are avoided due to the second protective layer on the sidewalls of the tungsten silicide layer. Furthermore, the rapid thermal annealing processes are performed in an ammonia atmosphere, so the agglomeration effect does not occur. As a result, the sheet resistance of the tungsten silicide layer is reduced and the surface of the tungsten silicide layer is planar. Additionally, the protective layers protect the tungsten silicide layer from chemical attack during cleaning processes. Moreover, the protective layers avoid loss of dopants from the polycide layer.
  • On the other hand, two rapid thermal annealing processes in the invention help to change the grain size of WSi[0023] x, so that the sheet resistance of the tungsten silicide layer is reduced.
  • FIG. 2 shows a curve of sheet resistance of a tungsten silicide layer vs. rapid thermal annealing temperature. [0024]
  • Referring to FIG. 2, [0025] curve 202 represents the sheet resistance of the tungsten silicide layer as a function of a rapid thermal annealing temperature in this invention. As shown in FIG. 2, the sheet resistance of the tungsten silicide layer is greatly decreased after performing the rapid thermal annealing process at above 700° C.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. [0026]

Claims (15)

What is claimed is:
1. A method for forming a gate, comprising the steps of:
providing a substrate;
forming a gate oxide layer on the substrate;
forming a polysilicon layer on the gate oxide layer;
forming a tungsten silicide layer on the polysilicon layer;
performing a first rapid thermal annealing process in an ammonia atmosphere to form a first protective layer on the tungsten silicide layer;
forming a nitride layer on the first protective layer;
defining a gate structure, wherein the gate structure includes the gate oxide layer, the polysilicon layer, the tungsten silicide layer, the first protective layer and the nitride layer;
performing a second rapid thermal annealing process in an ammonia atmosphere to form a second protective layer on sidewalls of the polysilicon layer and the tungsten silicide layer; and
forming a spacer to abut against sidewalls of the nitride layer, the first and the second protective layers.
2. The method of
claim 1
, wherein the first rapid thermal annealing process further comprises:
performing a first annealing process for about 25-35 seconds at a temperature of about 750-850° C.; and
performing a second annealing process for about 5-15 seconds at a temperature of about 950-1050° C.
3. The method of
claim 1
, wherein the first protective layer includes nitride.
4. The method of
claim 1
. wherein the second rapid thermal annealing process further comprises:
performing a first annealing process for about 25-35 seconds at a temperature of about 750-850 ° C.; and
performing a second annealing process for about 5-15 seconds at a temperature of about 950-1050° C.
5. The method of
claim 1
, wherein the second protective layer includes nitride.
6. The method of
claim 1
, wherein the step of forming the tungsten silicide layer includes low pressure chemical vapor deposition with SiH2Cl2 and WF6 as a gas source.
7. The method of
claim 1
, wherein the step of forming the nitride layer includes low pressure chemical vapor deposition
8. The method of
claim 1
, wherein a thickness of the nitride layer is about 1400-1600 Å.
9. The method of
claim 1
, wherein the polysilicon layer includes doped polysilicon.
10. A method for maintaining quality of a tungsten silicide layer, which is suitable for a semiconductor process, comprising the steps of:
providing a substrate;
forming a tungsten silicide layer on the substrate;
performing a first rapid thermal annealing process in an ammonia atmosphere to form a first protective layer on the tungsten silicide layer;
defining the tungsten silicide layer and the first protective layer to expose sidewalls of the tungsten silicide layer; and
performing a second rapid thermal annealing process in an ammonia atmosphere to form a second protective layer on the sidewalls of the tungsten silicide layer.
11. The method of
claim 10
, wherein the first rapid thermal annealing process further comprises:
performing a first annealing process for about 25-35 seconds at a temperature of about 750-850° C.; and
performing a second annealing process for about 5-15 seconds at a temperature of about 950-1050° C.
12. The method of
claim 10
, wherein the first protective layer includes nitride.
13. The method of
claim 10
, wherein the second rapid thermal annealing process further comprises:
performing a first annealing process for about 25-35 seconds at a temperature of about 750-850° C.; and
performing a second annealing process for about 5-15 seconds at a temperature of about 950-1050° C.
14. The method of
claim 10
, wherein the second protective layer includes nitride.
15. The method of
claim 10
, wherein the step of forming the tungsten silicide layer includes low pressure chemical vapor deposition with SiH2Cl2 and WF6 as a gas source.
US09/901,211 1999-07-07 2001-07-09 Method for forming gate Abandoned US20010039108A1 (en)

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TW463311B (en) * 2000-10-02 2001-11-11 United Microelectronics Corp Manufacturing method of bit line
US6909145B2 (en) * 2002-09-23 2005-06-21 International Business Machines Corporation Metal spacer gate for CMOS FET
US8450221B2 (en) * 2010-08-04 2013-05-28 Texas Instruments Incorporated Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls

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US5483104A (en) * 1990-01-12 1996-01-09 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5482749A (en) * 1993-06-28 1996-01-09 Applied Materials, Inc. Pretreatment process for treating aluminum-bearing surfaces of deposition chamber prior to deposition of tungsten silicide coating on substrate therein
JP2720827B2 (en) * 1994-07-05 1998-03-04 日本電気株式会社 Method for manufacturing semiconductor device
JPH10186969A (en) * 1996-12-24 1998-07-14 Konica Corp Image forming device and control method thereof
US5756392A (en) * 1997-01-22 1998-05-26 Taiwan Semiconductor Manuacturing Company, Ltd. Method of formation of polycide in a semiconductor IC device
US5817562A (en) * 1997-01-24 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)
US5851927A (en) * 1997-08-29 1998-12-22 Motorola, Inc. Method of forming a semiconductor device by DUV resist patterning
US6074908A (en) * 1999-05-26 2000-06-13 Taiwan Semiconductor Manufacturing Company Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits

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