US20010033157A1 - Power device driver circuit - Google Patents
Power device driver circuit Download PDFInfo
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- US20010033157A1 US20010033157A1 US09/765,833 US76583301A US2001033157A1 US 20010033157 A1 US20010033157 A1 US 20010033157A1 US 76583301 A US76583301 A US 76583301A US 2001033157 A1 US2001033157 A1 US 2001033157A1
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 60
- 230000004044 response Effects 0.000 claims abstract description 5
- 238000005516 engineering process Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 9
- 230000000694 effects Effects 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000541 pulsatile effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Definitions
- the present invention relates to techniques for driving devices in half-bridge configurations. More specifically, the present invention provides techniques and circuitry for driving a high side device in a half-bridge configuration into an inductive load in a manner which reduces the effects of parasitic capacitances.
- FIG. 1 is a schematic of a driver circuit 100 for the high side device in a half bridge circuit as described in U.S. Pat. No. 4,994,955 for HALF-BRIDGE DRIVER WHICH IS INSENSITIVE TO COMMON MODE CURRENTS issued on Feb. 19, 1991, the entirety of which is incorporated herein by reference for all purposes.
- the lower half of the schematic is the transmitter portion 76 of a level shifter which converts pulsatile inputs at V ON and V OFF into current pulses I ON and I OFF, respectively.
- the upper half of the schematic is the receiver portion 78 of a high side driver which generates the gate to source voltage for the high side device (not shown) between lines 38 and 40 .
- Current pulse I ON is transmitted alone to place the high side device in a conductive state, while current pulse I OFF is transmitted alone to place the high side device in a non-conductive state.
- a double differential amplifier comprising transistors T 1 and T 2 and matched resistors R 5 and R 6 is employed.
- the double differential amplifier produces substantially identical voltages at V 1 and V 2 in response to the common mode currents which will not turn on transistors T 1 and T 2 .
- the current pulse ION flowing only in line 70 turns on T 1 while the current pulse I OFF flowing only in line 72 turns on T 2 .
- the resulting set and reset voltages (V S and V R ) are input to an RS flip-flop 96 which provides the gate drive to the high side device via buffer 106 .
- the solution provided by the circuit of FIG. 1 does not address other undesirable effects of parasitic capacitance 82 .
- the resonant current in the inductor can drive the device output toward its positive rail.
- This positive going output voltage swing causes current to flow in parasitic capacitances 82 (these capacitances being charged via either R 1 , R 2 , T 9 , and T 12 ).
- the V D supply rail moves up in voltage. That is, V D moves up as the output of the high side device approaches its rail because the high side device output is coupled to the V D rail via a “bootstrap” capacitance.
- a potential solution to this problem could be to reduce the values of resistors R 1 and R 2 in an attempt to reduce the likelihood of this clamping effect.
- eliminating the pulse generators driving V ON and V OFF alone does not solve the problem as the “on” signal may still be shorter in duration than the duration of the clamping.
- the techniques of the present invention prevent the occurrence of resonance oscillations in the MUTE mode of audio amplifiers which may result, at least in part, from parasitic capacitances.
- these goals are achieved by generating a compensating current which effectively cancels the effects of the parasitic current generated in the parasitic capacitance of the driver circuit's input device. This compensating current is generated using a compensating device configured similarly to the driver circuit's input device.
- the compensating current is generated in the compensating device's parasitic capacitance due to the same condition which causes the parasitic current in the input device.
- a current mirror is then used to provide the same magnitude current to the parasitic capacitance of the driver circuit's input device, thereby canceling at least part of the effect of the parasitic current.
- the present invention provides a circuit for compensating for a first parasitic current corresponding to a first parasitic capacitance associated with a first switch.
- a second switch is configured substantially the same as the first switch, the second switch having a second parasitic capacitance associated therewith.
- a current mirror coupled to the second switch generates a compensating current in response to a second parasitic current corresponding to the second parasitic capacitance. The compensating current compensates for at least a portion of the first parasitic current.
- FIG. 1 is a schematic diagram of a half-bridge driver circuit
- FIG. 2 is a schematic diagram of a half-bridge driver circuit
- FIG. 3 is a schematic diagram of a half-bridge driver circuit including parasitic current compensation circuitry designed according to the present invention.
- FIG. 2 shows one solution for the problem described above with reference to FIG. 1 according to which an “on” pulse will not be ignored. That is, with circuit 200 , high side device 202 is always turned on if an “on” signal is present. This is because when an “on” signal is present, the drain of device M 1 is pulled low and latch 206 is set via inverter 208 thereby providing drive to device 202 . By contrast, when the “on” signal is not present, latch 206 is typically reset and the drive to device 202 is removed. It should be noted that because circuit 200 responds to levels rather than pulses, the “on” signal should not go through a pulse generator as with circuit 100 of FIG. 1.
- FIG. 2 The improvement over the circuit of FIG. 1 is largely due to the fact that the driver circuitry of FIG. 2 is single-ended rather than differential and that therefore simultaneous “on” and “off” signals do not create the condition under which true “on” signals are ignored.
- specific devices in FIG. 2 are shown to be field effect transistors (FETs) or that latch 206 is shown as an RS flip-flop, it will be understood that a variety of different device types may be employed such as, for example, bipolar devices in place of the FETs or any type of latch (e.g., JK flip-flop) in place of latch 206 .
- flip-flop 206 could be replaced with another inverter stage.
- high side device 202 of FIG. 2 may still be turned on as a result of the charging of parasitic capacitance in the circuit.
- FIG. 2 it is represented as the current l P1 charging parasitic capacitance C P1 .
- this condition occurs when the low side device (e.g., device 204 in FIG. 2) is switched off and the inductive load (e.g., inductor L of FIG. 2) forces current into the circuit output node (e.g., node 210 of FIG. 2). Under this condition in circuit 200 , voltage is developed across resistor R 1 resulting in current I P1 charging parasitic capacitance C P1 .
- the turning on of high side device 202 as a result of the charging of parasitic capacitance C P1 rather than an actual “on” signal is generally not a problem in switching applications (e.g., a switch mode audio amplifier) in that the shutting off of the low side device typically and immediately precedes the turning on of the high side device. That is, the high side device was to be turned on in any event.
- switching applications e.g., a switch mode audio amplifier
- Circuit 300 of FIG. 3 incorporates an enhancement to the circuit of FIG. 2 which eliminates the undesirable false “on” condition as well as the resonance oscillation described above.
- Circuit elements in FIG. 3 having reference numbers corresponding to circuit elements in FIG. 2 operate similarly to those corresponding elements.
- Circuit 300 includes parasitic current compensation circuitry which provides a compensating current which flows in parasitic capacitance C P1 when the output of the high side device 202 transitions toward the positive rail.
- This compensating current is generated using an additional transistor M 10 configured similarly to transistor M 1 and an associated current mirror comprising transistors M 11 and M 12 .
- M 10 has a corresponding parasitic capacitance C P10 .
- the geometries of transistors M 1 and M 10 are closely matched such that parasitic capacitances C P1 and Cp 10 are also closely matched.
- the parasitic current compensation circuitry of the present invention may also be employed to compensate for the parasitic currents I C (due to parasitic capacitors 82 ) in driver circuit 100 of FIG. 1.
- the parasitic current compensation circuitry of the present invention may be used in a wide variety of applications to compensate for or eliminate parasitic currents and their undesirable effects.
- transistors M 1 and M 10 are described as being closely matched. It will be understood, that these transistors may be substantially identical. It will also be understood, however, that these transistors may not be identical without departing from the scope of the invention. That is, the technique of the present invention may have efficacy in certain applications even where these transistors are not perfectly matched.
Abstract
Description
- The present application claims priority from U.S. Provisional Application No. 60/184,214 for IMPROVED POWER FET DRIVER CIRCUIT filed on Feb. 23, 2000, the entirety of which is incorporated herein by reference for all purposes.
- The present invention relates to techniques for driving devices in half-bridge configurations. More specifically, the present invention provides techniques and circuitry for driving a high side device in a half-bridge configuration into an inductive load in a manner which reduces the effects of parasitic capacitances.
- FIG. 1 is a schematic of a
driver circuit 100 for the high side device in a half bridge circuit as described in U.S. Pat. No. 4,994,955 for HALF-BRIDGE DRIVER WHICH IS INSENSITIVE TO COMMON MODE CURRENTS issued on Feb. 19, 1991, the entirety of which is incorporated herein by reference for all purposes. The lower half of the schematic is thetransmitter portion 76 of a level shifter which converts pulsatile inputs at VON and VOFF into current pulses ION and IOFF, respectively. The upper half of the schematic is thereceiver portion 78 of a high side driver which generates the gate to source voltage for the high side device (not shown) betweenlines - To provide insensitivity to common mode currents Ic(due to parasitic capacitances 82), a double differential amplifier comprising transistors T1 and T2 and matched resistors R5 and R6 is employed. The double differential amplifier produces substantially identical voltages at V1 and V2 in response to the common mode currents which will not turn on transistors T1 and T2. By contrast, the current pulse ION flowing only in
line 70 turns on T1 while the current pulse IOFF flowing only inline 72 turns on T2. The resulting set and reset voltages (VS and VR) are input to an RS flip-flop 96 which provides the gate drive to the high side device viabuffer 106. - Unfortunately, the solution provided by the circuit of FIG. 1 does not address other undesirable effects of
parasitic capacitance 82. For example, if the high side device being driven by the circuit of FIG. 1 drives an inductive load or filter, the resonant current in the inductor can drive the device output toward its positive rail. This positive going output voltage swing, in turn, causes current to flow in parasitic capacitances 82 (these capacitances being charged via either R1, R2, T9, and T12). As this current flows, the VD supply rail moves up in voltage. That is, VD moves up as the output of the high side device approaches its rail because the high side device output is coupled to the VD rail via a “bootstrap” capacitance. - As voltages are developed across R1 and R2 due to the parasitic currents, the “on” and “off” signals into the high side driver are simultaneously activated. The magnitude of these currents can be such as to active the clamping mechanism implemented with transistors T11 and T12. During the time when T11 and T12 are activated, input pulses are ignored. As a result, legitimate “on” pulses could be ignored because of the parasitic currents. This is clearly an undesirable result.
- A potential solution to this problem could be to reduce the values of resistors R1 and R2 in an attempt to reduce the likelihood of this clamping effect. However, this would require more current to operate the circuit and does not guarantee that the problem is eliminated for all values of output inductors, output transistors, and control signal pulse widths. It should also be noted that eliminating the pulse generators driving VON and VOFF alone does not solve the problem as the “on” signal may still be shorter in duration than the duration of the clamping.
- It is therefore desirable to provide techniques by which it can be ensured that an “on” signal for the high side device in a half-bridge configuration is never unintentionally ignored.
- According to the present invention, techniques and circuitry are provided which compensate for the effects of parasitic currents in half-bridge driver circuits such that “on” signals are not unintentionally ignored. In addition, and according to specific embodiments, the techniques of the present invention prevent the occurrence of resonance oscillations in the MUTE mode of audio amplifiers which may result, at least in part, from parasitic capacitances. According to a specific embodiments, these goals are achieved by generating a compensating current which effectively cancels the effects of the parasitic current generated in the parasitic capacitance of the driver circuit's input device. This compensating current is generated using a compensating device configured similarly to the driver circuit's input device. The compensating current is generated in the compensating device's parasitic capacitance due to the same condition which causes the parasitic current in the input device. A current mirror is then used to provide the same magnitude current to the parasitic capacitance of the driver circuit's input device, thereby canceling at least part of the effect of the parasitic current.
- Thus, the present invention provides a circuit for compensating for a first parasitic current corresponding to a first parasitic capacitance associated with a first switch. A second switch is configured substantially the same as the first switch, the second switch having a second parasitic capacitance associated therewith. A current mirror coupled to the second switch generates a compensating current in response to a second parasitic current corresponding to the second parasitic capacitance. The compensating current compensates for at least a portion of the first parasitic current.
- FIG. 1 is a schematic diagram of a half-bridge driver circuit;
- FIG. 2 is a schematic diagram of a half-bridge driver circuit; and
- FIG. 3 is a schematic diagram of a half-bridge driver circuit including parasitic current compensation circuitry designed according to the present invention.
- FIG. 2 shows one solution for the problem described above with reference to FIG. 1 according to which an “on” pulse will not be ignored. That is, with
circuit 200,high side device 202 is always turned on if an “on” signal is present. This is because when an “on” signal is present, the drain of device M1 is pulled low and latch 206 is set viainverter 208 thereby providing drive todevice 202. By contrast, when the “on” signal is not present,latch 206 is typically reset and the drive todevice 202 is removed. It should be noted that becausecircuit 200 responds to levels rather than pulses, the “on” signal should not go through a pulse generator as withcircuit 100 of FIG. 1. - The improvement over the circuit of FIG. 1 is largely due to the fact that the driver circuitry of FIG. 2 is single-ended rather than differential and that therefore simultaneous “on” and “off” signals do not create the condition under which true “on” signals are ignored. In addition and despite the fact that specific devices in FIG. 2 are shown to be field effect transistors (FETs) or that
latch 206 is shown as an RS flip-flop, it will be understood that a variety of different device types may be employed such as, for example, bipolar devices in place of the FETs or any type of latch (e.g., JK flip-flop) in place oflatch 206. Alternatively, flip-flop 206 could be replaced with another inverter stage. - As described above with reference to FIG. 1,
high side device 202 of FIG. 2 may still be turned on as a result of the charging of parasitic capacitance in the circuit. In FIG. 1 this was represented as currents IC chargingparasitic capacitances 82. In FIG. 2 it is represented as the current lP1 charging parasitic capacitance CP1. Also as described above, this condition occurs when the low side device (e.g.,device 204 in FIG. 2) is switched off and the inductive load (e.g., inductor L of FIG. 2) forces current into the circuit output node (e.g.,node 210 of FIG. 2). Under this condition incircuit 200, voltage is developed across resistor R1 resulting in current IP1 charging parasitic capacitance CP1. - The turning on of
high side device 202 as a result of the charging of parasitic capacitance CP1 rather than an actual “on” signal is generally not a problem in switching applications (e.g., a switch mode audio amplifier) in that the shutting off of the low side device typically and immediately precedes the turning on of the high side device. That is, the high side device was to be turned on in any event. - However, there are certain conditions, e.g., MUTE modes in audio amplifiers, where this parasitic “on” signal is undesirable. That is, in a MUTE condition, both high and low side devices should be off. If such a MUTE condition is initiated while the low side device is on, when the low side device is then turned off, the same parasitic “on” condition for the high side device described above may occur, turning the high side device on when it should be off. Moreover, if the high side device should be turned on in this way, an oscillation can be initiated in the absence of a control signal which excites a resonance comprising inductor L, capacitor C and the parasitic capacitance at the output of the power stage, CP2. This oscillation turns the high side device on and off at the resonance frequency which, as will be understood, is undesirable in MUTE mode.
-
Circuit 300 of FIG. 3 incorporates an enhancement to the circuit of FIG. 2 which eliminates the undesirable false “on” condition as well as the resonance oscillation described above. Circuit elements in FIG. 3 having reference numbers corresponding to circuit elements in FIG. 2 operate similarly to those corresponding elements.Circuit 300 includes parasitic current compensation circuitry which provides a compensating current which flows in parasitic capacitance CP1 when the output of thehigh side device 202 transitions toward the positive rail. - This compensating current is generated using an additional transistor M10 configured similarly to transistor M1 and an associated current mirror comprising transistors M11 and M12. M10 has a corresponding parasitic capacitance CP10. According to a specific embodiment, the geometries of transistors M1 and M10 are closely matched such that parasitic capacitances CP1 and Cp10 are also closely matched.
- Under the condition when the output of the high side device is being driven toward the positive rail, the current IP1 is generated in CP1 as described above. Because of the similarities in device geometry, a matching compensating current IP10 is also generated in CP10 under the same condition. Compensating current IP10 also flows in transistor M11 which is then mirrored in transistor M12, effectively canceling current IP1. Without the parasitic current IP1 flowing through resistor R1,
latch 206 is not set andhigh side device 202 is not turned on. That is, neither the false “on” condition nor the undesirable resonance oscillation occurs. - It will be understood that the parasitic current compensation circuitry of the present invention may also be employed to compensate for the parasitic currents IC (due to parasitic capacitors 82) in
driver circuit 100 of FIG. 1. In fact, the parasitic current compensation circuitry of the present invention may be used in a wide variety of applications to compensate for or eliminate parasitic currents and their undesirable effects. - While the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, in the description of the embodiment shown in FIG. 3, transistors M1 and M10 are described as being closely matched. It will be understood, that these transistors may be substantially identical. It will also be understood, however, that these transistors may not be identical without departing from the scope of the invention. That is, the technique of the present invention may have efficacy in certain applications even where these transistors are not perfectly matched.
- In addition, it will be understood that the schematic diagrams described herein represent a wide variety of circuit topologies and process technologies. For example, devices shown as single transistors could, in fact, represent multiple transistors in a parallel configuration. Moreover, the circuitry described herein may be implemented using a wide variety of semiconductor processing techniques such as, for example, CMOS, pMOS, and nMOS. Therefore, the scope of the invention should be determined with reference to the appended claims.
Claims (8)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/765,833 US6362679B2 (en) | 2000-02-23 | 2001-01-19 | Power device driver circuit |
PCT/US2001/005563 WO2001063740A1 (en) | 2000-02-23 | 2001-02-20 | Improved power device driver circuit |
AU2001238610A AU2001238610A1 (en) | 2000-02-23 | 2001-02-20 | Improved power device driver circuit |
TW090104210A TW521497B (en) | 2000-02-23 | 2001-02-23 | Improved power device driver circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18421400P | 2000-02-23 | 2000-02-23 | |
US09/765,833 US6362679B2 (en) | 2000-02-23 | 2001-01-19 | Power device driver circuit |
Publications (2)
Publication Number | Publication Date |
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US20010033157A1 true US20010033157A1 (en) | 2001-10-25 |
US6362679B2 US6362679B2 (en) | 2002-03-26 |
Family
ID=26879924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/765,833 Expired - Lifetime US6362679B2 (en) | 2000-02-23 | 2001-01-19 | Power device driver circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US6362679B2 (en) |
AU (1) | AU2001238610A1 (en) |
TW (1) | TW521497B (en) |
WO (1) | WO2001063740A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105917739A (en) * | 2014-01-17 | 2016-08-31 | 欧司朗有限公司 | Circuit arrangement for operating light sources |
US20190115914A1 (en) * | 2017-10-05 | 2019-04-18 | Rohm Co., Ltd. | Driving circuit for output transistor |
CN114640305A (en) * | 2022-05-12 | 2022-06-17 | 苏州云途半导体有限公司 | Current compensation circuit and method |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4382312B2 (en) * | 2001-09-05 | 2009-12-09 | 三菱電機株式会社 | Drive control device, power conversion device, power conversion device control method, and power conversion device use method |
US6809553B2 (en) * | 2001-10-15 | 2004-10-26 | International Rectifier Corporation | Digital level shifter with reduced power dissipation and false transmission blocking |
US6522083B1 (en) * | 2001-11-08 | 2003-02-18 | Linear Technology Corp. | Driver circuitry with tuned output impedance |
KR100422578B1 (en) * | 2001-12-06 | 2004-03-16 | 주식회사 하이닉스반도체 | Charge Pump Circuit for Reducing Jitter |
US7746935B2 (en) * | 2005-05-13 | 2010-06-29 | Xienetics, Inc. | Digital amplifier system for driving a capacitive load |
TWI309504B (en) * | 2005-10-17 | 2009-05-01 | Realtek Semiconductor Corp | Level shift circuit |
US7710098B2 (en) * | 2005-12-16 | 2010-05-04 | Cambridge Semiconductor Limited | Power supply driver circuit |
US7733098B2 (en) * | 2005-12-22 | 2010-06-08 | Cambridge Semiconductor Limited | Saturation detection circuits |
GB0615029D0 (en) * | 2005-12-22 | 2006-09-06 | Cambridge Semiconductor Ltd | Switch mode power supply controllers |
US9923500B1 (en) * | 2016-09-13 | 2018-03-20 | Infineon Technologies Ag | Gate-driver circuit with improved common-mode transient immunity |
US10333408B1 (en) * | 2018-04-26 | 2019-06-25 | Dialog Semiconductor (Uk) Limited | Compensation of level-shift capacitance |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4994955A (en) | 1989-12-29 | 1991-02-19 | North American Philips Corporation | Half-bridge driver which is insensitive to common mode currents |
EP0703667B1 (en) * | 1994-09-16 | 1997-06-25 | STMicroelectronics S.r.l. | An integrated control circuit with a level shifter for switching an electronic switch |
WO1996032778A2 (en) * | 1995-04-10 | 1996-10-17 | Philips Electronics N.V. | Level-shifting circuit and high-side driver including such a level-shifting circuit |
-
2001
- 2001-01-19 US US09/765,833 patent/US6362679B2/en not_active Expired - Lifetime
- 2001-02-20 WO PCT/US2001/005563 patent/WO2001063740A1/en active Application Filing
- 2001-02-20 AU AU2001238610A patent/AU2001238610A1/en not_active Abandoned
- 2001-02-23 TW TW090104210A patent/TW521497B/en not_active IP Right Cessation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105917739A (en) * | 2014-01-17 | 2016-08-31 | 欧司朗有限公司 | Circuit arrangement for operating light sources |
US9686827B2 (en) | 2014-01-17 | 2017-06-20 | Osram Gmbh | Circuit arrangement for operating light sources |
US20190115914A1 (en) * | 2017-10-05 | 2019-04-18 | Rohm Co., Ltd. | Driving circuit for output transistor |
US10778213B2 (en) * | 2017-10-05 | 2020-09-15 | Rohm Co., Ltd. | Driving circuit for output transistor |
CN114640305A (en) * | 2022-05-12 | 2022-06-17 | 苏州云途半导体有限公司 | Current compensation circuit and method |
Also Published As
Publication number | Publication date |
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TW521497B (en) | 2003-02-21 |
AU2001238610A1 (en) | 2001-09-03 |
WO2001063740A1 (en) | 2001-08-30 |
US6362679B2 (en) | 2002-03-26 |
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