US20010026196A1 - Loop delay compensation for a digital power amplifier - Google Patents
Loop delay compensation for a digital power amplifier Download PDFInfo
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- US20010026196A1 US20010026196A1 US09/796,634 US79663401A US2001026196A1 US 20010026196 A1 US20010026196 A1 US 20010026196A1 US 79663401 A US79663401 A US 79663401A US 2001026196 A1 US2001026196 A1 US 2001026196A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C1/00—Amplitude modulation
- H03C1/02—Details
- H03C1/06—Modifications of modulator to reduce distortion, e.g. by feedback, and clearly applicable to more than one type of modulator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/08—Modifications of modulator to linearise modulation, e.g. by feedback, and clearly applicable to more than one type of modulator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
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Abstract
Description
- The present application claims priority from U.S. Provisional Patent Application Ser. No. 60/186,830 for LOOP DELAY COMPENSATION FOR AN RF DIGITAL POWER AMPLIFIER filed on Mar. 3, 2000, the entirety of which is incorporated herein by reference for all purposes.
- The subject matter of the present application also relates to the subject matter described in U.S. Pat. No. 5,909,153 for METHOD AND APPARATUS FOR COMPENSATING FOR DELAYS IN MODULATOR LOOPS issued Jun. 1, 1999, the entirety of which is incorporated herein by reference for all purposes.
- The present invention relates to delay handling in modulator loops. More specifically, the present invention provides a filter in the modulator loop which compensates for delays introduced by, for example, a power switching stage or an output filter.
- With pulse width modulation (PWM) and other modulation techniques, the delay introduced by switching and output filter stages must be effectively dealt with to alleviate the adverse effects such delays have on circuit stability. This is particularly true for modulators which have relatively high power switching stages because the delays can become very large with respect to the pulse repetition frequency of the loop. A traditional solution to the problem of delay handling will be described with reference to FIGS. 1 and 2.
- FIG. 1 is a block diagram of a
typical modulator loop 100. The logic output ofmodulator 102 drives an invertingpower stage 104 the output of which is filtered byoutput filter 106. Afeedback resistor 108 andattenuation resistor 112 are provided for the purpose of introducing negative feedback from the output of the loop tomodulator 102. FIG. 2 shows twowaveforms - Thus, where the original design of the loop contemplates negative feedback, the delay converts it to positive feedback and therefore loop instability (not shown) results. For this reason, a
filter capacitor 110 is provided in parallel withfeedback resistor 108 for delay compensation. Capacitor 110 produces a zero in the feedback loop, effectively bypassing the attenuation caused byresistors - Unfortunately, because this type of delay compensation is performed after the delay has been introduced into the loop, it is difficult to correct all of the delay's negative consequences with regard to loop stability. In fact, this type of compensation technique has had only limited success and, as a result, has limited the delay tolerance and the overall performance of today's modulators. One solution is to use feedback signals directly from the logic output of the modulator, i.e., before the delay is introduced, in combination with the output of the power stage and/or the output filter. Unfortunately, while the output of the modulator (202) and the filter output (204) have similar characteristics there are significant differences in content in the modulator loop's frequency range of interest due to the non-ideal nature of the power stage as discussed in commonly assigned U.S. Pat. No. 5,974,089 for METHOD AND APPARATUS FOR PERFORMANCE IMPROVEMENT BY QUALIFYING PULSES IN AN OVERSAMPLED, NOISE-SHAPING SIGNAL PROCESSOR issued on Oct. 26, 1999, the entirety of which is incorporated herein by reference for all purposes. This makes it very difficult to achieve high fidelity operation while feeding these signals back.
- In view of the foregoing, it is desirable to provide an improved technique for compensating for delays in modulator loops such that greater delays may be tolerated without adversely affecting loop stability.
- According to the present invention, a feedback technique for modulator loops is introduced which addresses the difficulties discussed above. The feedback technique described herein uses the output of a low voltage modulator stage to compensate for the delay introduced by subsequent power and filter stages while, at the same time, achieving a high level of fidelity notwithstanding the differences in signal content as discussed above. The invention achieves this result by filtering the output of the modulator stage such that its frequency components outside of the modulator loop's frequency range of interest are transmitted to the feedback path while its frequency components inside the loop's range of interest are attenuated. Thus, the stability of the loop is enhanced due to the feeding back of some portion of the modulator output, while the fidelity of the output spectrum of the loop is not adversely affected by undesirable modulator output components within the range.
- Depending upon the type of modulator, the frequencies attenuated and transmitted by the feedback filter of the present invention vary. For example, for a baseband modulator, the filter attenuates frequencies in the baseband and transmits higher frequencies such as, for example, a high pass filter. For a band pass modulator, the feedback filter may behave like a notch filter, attenuating frequencies within the relevant band. Similarly, for a band reject modulator, the filter may behave like a band pass filter, while for a high pass modulator, the filter may behave like a low pass filter.
- In a modulator loop which tolerates a 250 ns delay without the improvements of the present invention, the addition of the feedback technique described herein has been shown to increase the delay tolerance level to greater than 500 ns. This means that, according to the present invention, very large power devices may be employed with low voltage modulators despite the troublesome delays associated with such power devices. For example, a specific embodiment of the invention is capable of delivering more than 1000 W (>1 hp!) into a 4 ohm load with very high fidelity. For a 1 ohm load (e.g., an industrial motor) this is the equivalent of more than 5 hp! This is a significant improvement over currently available high fidelity modulator loops and is sufficient for many relatively high power industrial applications.
- Thus the present invention provides a modulator loop having an associated band pass frequency range and including a switching stage having a first delay associated therewith. The modulator loop also includes a modulator stage having a feedback input. The output of the modulator stage is coupled to the input of the switching stage. A first feedback path is coupled between the output of the switching stage and the modulator stage. A notch filter corresponding to the band pass frequency range is coupled between the output of the modulator stage and the feedback input of the modulator stage for compensating for the first delay.
- A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
- FIG. 1 is a block diagram of a modulator loop designed according to the prior art;
- FIG. 2 shows two waveforms from the modulator loop of FIG. 1;
- FIG. 3 is a block diagram of a modulator loop designed according to a specific embodiment of the invention;
- FIG. 4 is a block diagram of a modulator loop designed according to a more specific embodiment of the invention;
- FIG. 5 is a block diagram of a modulator loop designed according to a still more specific embodiment of the invention;
- FIG. 6 is a block diagram of a modulator loop designed according to an even still more specific embodiment of the invention;
- FIG. 7 is a block diagram of a generalized embodiment of a modulator loop designed according to the invention; and
- FIG. 8 is a block diagram of a band pass amplifier designed according to a specific embodiment of the invention.
- FIG. 3 is a block diagram of a
modulator loop 300 designed according to a specific embodiment of the invention.Modulator stage 302 may be any of a wide variety of modulator types including, for example, a pulse width modulator, or an oversampled mixed-signal modulator such as the one described in commonly assigned, copending U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes. According to specific embodiments,modulator stage 302 comprises a plurality of filters in parallel and/or in series. Switchingstage 304 receives a control signal from the output ofmodulator 302. Switchingstage 304 may be any of a wide variety of switch configurations and power levels. Switchingstage 304 may also be either inverting or noninverting. For an inverting switching stage, an inverter is inserted in the modulator output feedback path in front offeedback filter 308.Output filter 306 may also be implemented according to any of a wide variety of techniques as appropriate for the desired output signal content in a particular application. - As with previous designs, negative feedback may be provided to
modulator 302 from the outputs of switchingstage 304 and/oroutput filter 306 via summingjunction 310. For purposes of this description,junction 310 is assumed to be ideal and therefore, no additional feedback circuitry is shown. However, it will be understood that summingjunction 310 must, of necessity, be implemented using actual circuit components such as, for example, resistors. Therefore, specific embodiments of the invention showing some actual implementations of summingjunction 310 are described below with reference to FIGS. 4-6. The frequency content of the feedback from the switching stage and output filter is both inside and outside of the loop's frequency range of interest. - Unlike previous designs, the
modulator loop 300 also employs feedback from the output ofmodulator 302 viafeedback filter 308 to further enhance loop stability. However, to avoid the negative consequences for output fidelity discussed in the Background of the Invention, this feedback is filtered byfilter 308 such that its frequency content is largely outside of the modulator loop's frequency range of interest. Thus, stability is increased without loss of fidelity. - FIG. 4 is a block diagram of a
baseband modulator loop 400 designed according to a more specific embodiment of the invention.Modulator 402, switchingstage 404, andoutput filter 406 operate substantially similarly to the corresponding loop elements discussed above with reference to FIG. 3. Feedback is provided to the feedback input ofmodulator 402 from the output of switchingstage 404 via a dividernetwork comprising resistors modulator 402 from its logic output viafilter capacitor 408 andseries resistor 410. The value ofcapacitor 408 is selected to attenuate the logic output's signal content in the baseband range of interest while passing higher frequencies to the feedback path for combination with the attenuated switching stage signal. Significant increases in delay tolerance have been achieved with this configuration. - However, because the filtered modulator logic signal is not combined with the feedback path using an ideal filter and an ideal summer, an additional pole and zero are introduced to the transfer function of the loop by the actual circuit elements, i.e.,
capacitor 408 andresistor 410. This can be seen from a network analysis perspective by treating the logic output ofmodulator 402 as ground and observing thatcapacitor 408 adds delay to the loop by low pass filtering the switching stage output. This delay represents a limitation on the performance enhancements made possible by the use of the filtered modulator output as feedback. Therefore, further embodiments of the invention are described below introducing enhancements to the loop of FIG. 4 which address this limitation. - FIG. 5 is a block diagram of a
baseband modulator loop 500 designed according to a still more specific embodiment of the invention.Modulator 502, switchingstage 504, andoutput filter 506 operate substantially similarly to the corresponding loop elements described above with reference to FIG. 3. As with the corresponding elements ofloop 400, feedback is provided to the feedback input ofmodulator 502 from the output of switchingstage 504 via a dividernetwork comprising resistors modulator 502 from its logic output viafilter capacitor 508 andseries resistor 510. The value ofcapacitor 508 is selected to attenuate the logic output's signal content in the baseband range of interest while passing higher frequencies to the feedback path for combination with the attenuated switching stage signal. - An
additional capacitor 516 is provided from the output of switchingstage 504 tonode 1 which cancels the pole introduced into the switching stage's feedback path bycapacitor 508. This may be understood from a network analysis perspective by again treating the logic output ofmodulator 502 as ground and analyzing the feedback path from the output of switchingstage 504. If the ratio ofresistors capacitors node 1 is the same as that seen atnode 2, i.e., the voltage level should be the same. Because the voltages atnodes resistor 510 which can therefore be treated like an open circuit, effectively removingcapacitor 508 and its corresponding pole from the switching stage feedback path. This makes the modulator loop extremely stable as well as delay tolerant. - FIG. 6 is a block diagram of a
modulator loop 600 designed according to an even still more specific embodiment of the invention.Modulator 602, switchingstage 604, andoutput filter 606 operate substantially similarly to the corresponding loop elements described above with reference to FIG. 3.Resistors capacitors filter 606 to the feedback input ofmodulator stage 602, the additional feedback path being implemented with aresistor 620.Capacitor 622 is also included from the output offilter 606 tonode 1 for the purpose of canceling the pole in the new feedback path introduced bycapacitors resistor 620 andresistor 614 in parallel withresistor 612 is made the same as the ratio ofcapacitor 608 in parallel withcapacitor 616 andcapacitor 622, no current flows inresistor 610 and thus,capacitor 608 is effectively removed from either feedback path. - FIG. 7 is a block diagram of a generalized embodiment of a
modulator loop 700 designed according to the invention. Replacing the feedback filter and signal combining circuitry of the previously described embodiments is a 4-port network 708 to whichmodulator stage 702, switchingstage 704, andoutput filter stage 706 are connected.Network 708 takes the modulator logic output signal and attenuates its frequency content within the range of interest ofmodulator loop 700. It also combines the resulting signal with the fed back outputs of the switching and filter stages for use as feedback bymodulator stage 702.Network 708 may be implemented in a variety of ways depending upon the technology used to implementmodulator loop 700. - Moreover, for modulators having amplitude dependent stability (e.g., oversampled and pulse width modulators), it may be desirable to control the magnitude of the modulator feedback with respect to the feedback from the power and/or filter stages to maintain an optimal stability point. Therefore, an
optional gain control 710 is provided before the feedback filter (included in 4-port network 708) to allow gain matching of the modulator logic output signal and the power output. According to a specific embodiment,gain control 710 is implemented using a digital-to-analog converter (DAC) with a variable output amplitude. - While the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, the specific embodiments described above with reference to FIGS. 4 and 5 show the use of analog components (i.e., resistors and capacitors) to both filter the modulator output and combine the resulting filtered feedback signal with the feedback path from the output of the switching stage. It will be understood, however, that, where, for example, the modulator stage is implemented using digital techniques, the circuitry and techniques used to filter and combine the feedback signal could be digital. Similarly, with a mixed-signal modulator, mixed-signal circuitry and techniques may be used to implement the feedback, e.g., combining signals at virtual grounds of op amps.
- It should also be understood that, depending upon the degree to which the contents of the modulator and power outputs in the modulator loop's frequency range of interest are dissimilar, and the degree to which degradation of the loop's output may be tolerated, varying levels of attenuation of the modulator output's components in the range may be appropriate. That is, the frequency components in the modulator stage output which are within the loop's frequency range of interest need not be completely rejected to maintain reasonable fidelity and remain within the scope of the invention.
- FIG. 8 shows an RF band pass noise-shaping
amplifier 800 designed according to the present invention as well as techniques described in U.S. Pat. No. 5,777,512 incorporated herein by reference above. Such an amplifier may be used, for example, in a wireless communication device such as a wireless phone, pager, network device, etc.RF amplifier 800 includes a frequencyselective network 802 which, using continuous-time feedback, noise shapes the modulated RF input. According to a specific embodiment,network 802 comprises at least one resonator stage having a transfer function designed to pass a band centered around 900 MHz. Of course, it will be understood that the band pass frequency range of a noise shaping amplifier designed according to the present invention may center on any of a wide variety of frequencies such as, for example, 1.8 GHz, 2.4 GHz, etc., and that the present invention is not limited to any particular range or set of ranges. - A/
D converter 804 converts the noise shaped RF signal to digital data using a sampling frequency fs which, according to a specific embodiment, is 3.6 GHz. According to one embodiment, A/D converter 804 comprises a comparator. -
Gate drive circuitry 806 takes the pulse train from A/D converter 804 and generates gate drive for each ofFETs amplifier 800. The output power stage shown includes three inductors L1, L2 and L3, and capacitor C1. This configuration creates two separate resonances at nodes A and B respectively when the corresponding one ofFETs selective network 802 is provided viafeedback path 812. The output signal of the power stage is passed to amatching network 814 which passes the output RF signal toantenna 816 for transmission. As will be understood and according to various embodiments,feedback path 812 may originate within matchingnetwork 814. - The loop of
amplifier 800 typically operates best with a loop delay equal to 1/fs, i.e., 1/3.6 GHz. To compensate for any additional and undesirable delay associated with the output power stage,amplifier 800 includes anotherfeedback path 818 to frequencyselective network 802 which includes anotch filter 820 having the same center point asnetwork 802. The source of the feedback is shown as the output of A/D converter 804. However, it will be understood that there are several other points between this node and the input to the power stage from which the feedback may originate. Therefore, the scope of the present invention should not be limited to the embodiment shown. Rather, as with all of the embodiments described herein, the scope of the invention should be interpreted with reference to the following claims.
Claims (15)
Priority Applications (3)
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US09/796,634 US6414560B2 (en) | 2000-03-03 | 2001-02-28 | Loop delay compensation for a digital power amplifier |
PCT/US2001/006780 WO2001067596A1 (en) | 2000-03-03 | 2001-03-01 | Rf communication system using an rf digital amplifier |
AU2001245398A AU2001245398A1 (en) | 2000-03-03 | 2001-03-01 | Rf communication system using an rf digital amplifier |
Applications Claiming Priority (2)
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US18683000P | 2000-03-03 | 2000-03-03 | |
US09/796,634 US6414560B2 (en) | 2000-03-03 | 2001-02-28 | Loop delay compensation for a digital power amplifier |
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US20010026196A1 true US20010026196A1 (en) | 2001-10-04 |
US6414560B2 US6414560B2 (en) | 2002-07-02 |
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Cited By (1)
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US20050059360A1 (en) * | 2003-09-16 | 2005-03-17 | Andrew Corporation, A Delaware Corporation | Compensation of filters in radio transmitters |
Families Citing this family (9)
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CA2362104A1 (en) * | 2000-10-30 | 2002-04-30 | Simon Fraser University | High efficiency power amplifier systems and methods |
JP2002299968A (en) * | 2001-03-30 | 2002-10-11 | Pioneer Electronic Corp | D-class amplifier |
US7200187B2 (en) * | 2001-07-26 | 2007-04-03 | O'brien Thomas J | Modulator for digital amplifier |
US7058464B2 (en) * | 2003-07-17 | 2006-06-06 | Ess Technology, Inc. | Device and method for signal processing |
US7023267B2 (en) * | 2004-02-17 | 2006-04-04 | Prophesi Technologies, Inc. | Switching power amplifier using a frequency translating delta sigma modulator |
US7541864B2 (en) * | 2004-06-04 | 2009-06-02 | Silicon Power Devices Aps | Power amplifier and pulse-width modulated amplifier |
JP2006230186A (en) * | 2005-01-21 | 2006-08-31 | Renesas Technology Corp | Semiconductor device |
US7180439B1 (en) * | 2006-03-16 | 2007-02-20 | Analog Devices, Inc. | Multi-path digital power supply controller |
EP1843465A1 (en) * | 2006-03-29 | 2007-10-10 | STMicroelectronics S.r.l. | Multiple feedback class-D amplifier |
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US4843339A (en) | 1987-10-28 | 1989-06-27 | Burr-Brown Corporation | Isolation amplifier including precision voltage-to-duty-cycle converter and low ripple, high bandwidth charge balance demodulator |
US5023566A (en) | 1989-12-21 | 1991-06-11 | General Electric Company | Driver for a high efficiency, high frequency Class-D power amplifier |
US5352986A (en) | 1993-01-22 | 1994-10-04 | Digital Fidelity, Inc. | Closed loop power controller |
US5610553A (en) | 1993-03-02 | 1997-03-11 | Kirn; Larry | Switching amplifier with impedance transformation output stage |
US5451900A (en) | 1993-03-17 | 1995-09-19 | Kabushiki Kaisha Toshiba | Pulse width modulation circuit |
US5479337A (en) | 1993-11-30 | 1995-12-26 | Kaiser Aerospace And Electronics Corporation | Very low power loss amplifier for analog signals utilizing constant-frequency zero-voltage-switching multi-resonant converter |
US5777512A (en) | 1996-06-20 | 1998-07-07 | Tripath Technology, Inc. | Method and apparatus for oversampled, noise-shaping, mixed-signal processing |
US5909153A (en) * | 1998-02-05 | 1999-06-01 | Tripath Technology, Inc. | Method and apparatus for compensating for delays in modulator loops |
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Cited By (2)
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US20050059360A1 (en) * | 2003-09-16 | 2005-03-17 | Andrew Corporation, A Delaware Corporation | Compensation of filters in radio transmitters |
US7149482B2 (en) * | 2003-09-16 | 2006-12-12 | Andrew Corporation | Compensation of filters in radio transmitters |
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