US20010023112A1 - Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall - Google Patents

Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall Download PDF

Info

Publication number
US20010023112A1
US20010023112A1 US09/837,136 US83713601A US2001023112A1 US 20010023112 A1 US20010023112 A1 US 20010023112A1 US 83713601 A US83713601 A US 83713601A US 2001023112 A1 US2001023112 A1 US 2001023112A1
Authority
US
United States
Prior art keywords
trench
side walls
silicon
substrate
exposed surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/837,136
Other versions
US6437400B2 (en
Inventor
Effendi Leobandung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/837,136 priority Critical patent/US6437400B2/en
Publication of US20010023112A1 publication Critical patent/US20010023112A1/en
Application granted granted Critical
Publication of US6437400B2 publication Critical patent/US6437400B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Definitions

  • the present invention relates to a process of fabricating a trench on a silicon substrate and, more particularly, to a process of forming a trench having tapered side walls on a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • An integrated circuit or an array of discrete integrated circuit devices includes numerous semiconductor devices. Current leakages and parasitic capacitances between devices can interfere with the intended operation of the circuit. Therefore, in many circuits, it is necessary to electrically isolate devices from one another. Several isolation techniques have been developed to meet that requirement.
  • a silicon-on-insulator (SOI) structure is a structure in which a buried insulating layer electrically isolates a silicon layer from a silicon substrate.
  • the SOI structure does not always occupy the entire silicon substrate. Often, the SOI structure occupies only a portion of the silicon substrate.
  • Shallow Trench Isolation is a process used in isolating devices formed on SOI substrates.
  • STI involves etching trenches, having side walls and bottoms, in the SOI substrate. Following etching, the trenches are filled with an oxide.
  • STI shallow trench isolation processing
  • An object of the present invention is to provide a process for fabricating a trench using STI in which the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom.
  • the present invention provides a process for fabricating a trench having a tapered shape, side walls, and a bottom on a silicon substrate.
  • the substrate has an exposed surface.
  • the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom. The process comprises the following steps:
  • the nitrogen ions are implanted on the initial trench side walls at an angle of from about 10 degrees to about 60 degrees relative to the exposed surface.
  • FIG. 1 shows in schematic representation a silicon substrate comprising a trench structure having side walls spaced further apart adjacent the trench bottom than adjacent the top of the silicon layer portion of the trench side wall;
  • FIG. 2A shows the structure of FIG. 1 after the trench has been filled with an oxide, producing a seam in the center of the trench;
  • FIG. 2B shows the structure of FIG. 2A after the seam has been filled with polysilicon, causing shorts between deposited poly gates;
  • FIG. 3 shows in schematic representation a silicon substrate
  • FIG. 4 shows in schematic representation a silicon substrate having a trench with substantially perpendicular side walls
  • FIG. 5 shows in schematic representation a top view of FIG. 4
  • FIG. 6 illustrates the angle to the exposed surface in which nitrogen ions are implanted into the trench side walls
  • FIG. 7 shows in schematic representation a silicon substrate having a tapered trench structure
  • FIG. 8 shows in schematic representation a tapered trench of a silicon substrate that has been filled with oxide.
  • the apparatus is made by the Shallow Trench Isolation (STI) process.
  • the STI process comprises the steps of etching trenches, having side walls and bottoms, in the SOI substrate, oxidizing the silicon layer portions of the trench sidewalls, and filling the trenches with an oxide.
  • FIG. 1 shows a side view of a silicon substrate 1 after the steps of etching a trench 18 and oxidizing those portions 19 , 20 of the side walls 24 , 26 of the trench 18 comprising a silicon layer 14 .
  • the substrate 1 comprises a silicon wafer 10 , a buried silicon oxide layer 12 formed on the silicon wafer 10 , the silicon layer 14 , a silicon nitride layer 16 , and the trench 18 .
  • the next step in STI processing comprises filling the trench 18 with an oxide 32 .
  • an oxide 32 As a result of the bottleneck-shape of the trench 18 , a shape in which the width of the trench 18 is greater near the bottom then at the top, it is very difficult to fill the trench 18 with an oxide 32 . This difficulty results in the formation of a seam 22 in the center of the trench 18 as illustrated in FIG. 2A.
  • FIG. 2B shows the structure of FIG. 2A after the seam 22 has been filled with polysilicon 40 .
  • the polysilicon 40 fills the seam 22 during deposition of poly gates 42 and may cause shorts between the poly gates 42 .
  • the present invention provides a process for fabricating a trench 18 using shallow trench isolation (STI) in which the side walls 24 , 26 of the trench 18 are spaced further apart adjacent the exposed surface than adjacent the trench bottom.
  • STI shallow trench isolation
  • FIG. 3 shows a side view of an embodiment of a silicon substrate comprising a silicon-on-insulator (SOI) substrate 1 .
  • the substrate 1 having an exposed surface 8 , comprises a silicon wafer 10 , a buried silicon oxide layer 12 formed on the silicon wafer 10 , a silicon layer 14 , and a silicon nitride layer 16 .
  • a thin oxide layer 15 of from about 0.006 ⁇ m to about 0.01 ⁇ m can optionally be deposited between the silicon layer 14 and the silicon nitride layer 16 to reduce damage to the silicon layer 14 caused by deposition of the silicon nitride layer 16 .
  • the thickness of the silicon oxide layer 12 is from about 0.1 ⁇ m to about 0.4 ⁇ m, the thickness of the silicon layer 14 is from about 0.1 ⁇ m to about 0.2 ⁇ m, and the thickness of the silicon nitride layer 16 is from about 0.1 ⁇ m to about 0.15 ⁇ m. In a more preferred embodiment, the thickness of the silicon oxide layer 12 is about 0.4 ⁇ m, the thickness of the silicon layer 14 is about 0.18 ⁇ m, and the thickness of the silicon nitride layer 16 is about 0.12 ⁇ m.
  • FIG. 4 shows a side view of a substrate 1 having an initial trench 18 extending into the interior of the substrate 1 .
  • standard photomasking and etching of the silicon substrate 1 , through the silicon nitride layer 16 , thin oxide layer 15 (if present), and silicon layer 14 results in an initial trench 18 having a bottom 21 and four initial trench side walls 24 , 26 , 28 , and 30 .
  • Side walls 24 and 26 are shown in FIG. 4.
  • FIG. 5 is a top view of FIG. 4 showing all four side walls 24 , 26 , 28 , and 30 of initial trench 18 .
  • Initial trench side walls 24 , 26 , 28 , and 30 are substantially perpendicular to the exposed surface 8 of the substrate 1 .
  • initial trench 18 can be cleaned using methods commonly known in the art, which typically include a preliminary step of plasma oxidation stripping or immersion in an inorganic resist stripper, followed by the removal of residual organic contaminants and the desorption of remaining atomic and ionic contaminants.
  • methods commonly known in the art typically include a preliminary step of plasma oxidation stripping or immersion in an inorganic resist stripper, followed by the removal of residual organic contaminants and the desorption of remaining atomic and ionic contaminants.
  • S. Wolf & R. N. Tauber discuss such cleaning processes on pages 516-517 of their text, titled Silicon Processing for the VLSI Era, Volume 1 —Process Technology (1986).
  • FIG. 6 shows the step of nitrogen ion implantation into the side walls 24 , 26 , 28 , and 30 of initial trench 18 .
  • the nitrogen ions 50 are implanted at an angle ( ⁇ ) to the exposed surface 8 of the substrate 1 .
  • Ion implantation is a process in which energetic, charged atoms or molecules are directly introduced into a substrate, such as a silicon wafer.
  • nitrogen ions 50 are implanted on each side wall 24 , 26 , 28 , and 30 of initial trench 18 .
  • a first position of the substrate 1 is determined so that nitrogen ions 50 are beamed at a direction parallel to side walls 28 and 30 onto side wall 24 .
  • the substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a second position.
  • Nitrogen ions 50 are then beamed at a direction parallel to side walls 24 and 26 onto side wall 28 .
  • the substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a third position.
  • Nitrogen ions 50 are then beamed at a direction parallel to side walls 28 and 30 onto side wall 26 .
  • the substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a fourth position. Nitrogen ions 50 are then beamed at a direction parallel to side walls 24 and 26 onto side wall 30 .
  • the optimal angle ( ⁇ ) of nitrogen ion implantation depends on the thickness of the silicon nitride layer 16 and the size of the trench 18 .
  • the side walls 24 , 26 , 28 , and 30 of trench 18 are implanted with from about 5 keV to about 15 keV nitrogen ions 50 to a dose of from about 1 ⁇ 10 14 /cm 2 to about 1 ⁇ 10 15 /cm 2 , and the nitrogen ions 50 are implanted at an angle ( ⁇ ) of from about 10 to about 60 degrees relative to the exposed surface 8 .
  • the side walls 24 , 26 , 28 , and 30 of trench 18 are implanted with about 10 keV nitrogen ions 50 to a dose of about 5 ⁇ 10 14 /cm 2 at an angle ( ⁇ ) of about 20 degrees.
  • angle
  • the side walls 24 , 26 , 28 , and 30 of trench 18 are implanted with about 10 keV nitrogen ions 50 to a dose of about 5 ⁇ 10 14 /cm 2 at an angle ( ⁇ ) of about 20 degrees.
  • FIG. 7 shows a side view of a resulting tapered trench 18 a after oxidation of the side walls 24 , 26 , 28 , and 30 of initial trench 18 , resulting in tapered side walls 24 a and 26 a .
  • the oxidation rate of the side walls 24 , 26 , 28 , and 30 is affected by nitrogen ion concentration which proportionally retards trench side wall oxidation.
  • the high concentration of nitrogen ions in the silicon nitride layer 16 which forms the portion of the side walls 24 and 26 adjacent the exposed surface 8 , inhibits oxidation.
  • the silicon layer 14 which forms the portion of the side walls 24 a and 26 a adjacent trench bottom 21 , has a lower concentration of nitrogen ions. Oxidation of the portion of the side walls 24 a and 26 a of the trench 18 a adjacent the silicon layer 14 results in oxide formation in proportion to nitrogen ion concentration.
  • the nitrogen ions 50 are implanted at an angle ( ⁇ ) relative to the exposed surface 8 , more nitrogen ions 50 are implanted into the portion of the side walls 24 a and 26 a of the trench 18 a adjacent the silicon layer 14 and the bottom 21 of the trench 18 a than in the silicon nitride layer 16 portion of the side walls 24 and 26 adjacent the exposed surface 8 , thereby producing a tapered shape upon oxidation.
  • a portion of silicon layer 14 adjacent the side walls 24 a and 26 a of the trench 18 a is also oxidized.
  • the side walls 24 , 26 , 28 , and 30 are oxidized using dry oxygen at a temperature of about 1 , 000 ° C.
  • FIG. 8 shows a side view of the tapered trench 18 a shown in FIG. 7 after tapered trench 18 a has been filled with the oxide 32 .
  • steps known in the art can be used to complete an STI structure.
  • the present invention can be used in bulk STI processes.
  • a silicon substrate comprising an SOI substrate was formed by the following steps.
  • a 0.4 ⁇ m layer of silicon oxide 12 was formed on a silicon wafer 1 and a 0.18 ⁇ m silicon layer 14 was formed on the silicon oxide layer 12 using the separation by implantation of oxygen (SIMOX) process.
  • a 0.008 ⁇ m layer of silicon oxide (thin silicon oxide layer 15 ) was next formed on the silicon layer 14 followed by deposition of a 0.12 ⁇ m layer of silicon nitride 16 on the thin silicon oxide layer 15 .
  • An initial trench 18 extending from the exposed surface 8 of the substrate 1 into an interior of the substrate was formed by photomasking and plasma etching.
  • the plasma etching was selective to stop at the silicon oxide layer 15 , producing a trench depth of 0.308 ⁇ m.
  • the initial trench side walls 24 , 26 , 28 , and 30 were implanted with 10 keV nitrogen ions 50 to a dose of 5 ⁇ 10 14 /cm 2 at an angle ( ⁇ ) of 30 degrees with respect to the exterior, exposed surface 8 of the substrate 1 .
  • the trench side walls 24 , 26 , 28 , and 30 were next oxidized with dry oxygen at 1,000° C., resulting in a tapered trench 18 a in which the trench side walls 24 , 26 , 28 , and 30 were spaced further apart adjacent the exposed surface 8 of the substrate 1 than adjacent the trench bottom 21 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Description

    TECHNICAL FIELD
  • The present invention relates to a process of fabricating a trench on a silicon substrate and, more particularly, to a process of forming a trench having tapered side walls on a silicon-on-insulator (SOI) substrate. [0001]
  • BACKGROUND OF THE INVENTION
  • An integrated circuit or an array of discrete integrated circuit devices includes numerous semiconductor devices. Current leakages and parasitic capacitances between devices can interfere with the intended operation of the circuit. Therefore, in many circuits, it is necessary to electrically isolate devices from one another. Several isolation techniques have been developed to meet that requirement. [0002]
  • A silicon-on-insulator (SOI) structure is a structure in which a buried insulating layer electrically isolates a silicon layer from a silicon substrate. The SOI structure does not always occupy the entire silicon substrate. Often, the SOI structure occupies only a portion of the silicon substrate. [0003]
  • Shallow Trench Isolation (STI) is a process used in isolating devices formed on SOI substrates. STI involves etching trenches, having side walls and bottoms, in the SOI substrate. Following etching, the trenches are filled with an oxide. [0004]
  • Unfortunately, there is a problem in implementing shallow trench isolation processing (STI) in SOI substrates. Following etching, and before filling the trenches with an oxide, the silicon layer portions of the trench side walls are oxidized. This step produces a bottleneck-shaped trench in which the trench side walls are wider adjacent the trench bottom than adjacent the top of the silicon layer portion of the trench side wall. After the step of oxidizing the silicon layer portion of the trench side walls, the next step in STI processing comprises filling the trenches with an oxide. The bottleneck shape of the trench makes filling the trench with an oxide difficult. This difficulty results in the formation of a seam in the center of the trench. This seam may open up during subsequent processing steps, leading to several problems. For instance, the seam might cause shorts between subsequently deposited poly gates if filled with polysilicon during the poly gate deposition step. [0005]
  • The deficiencies of the conventional processes of fabricating a trench on a silicon substrate using shallow trench isolation (STI) show that a need still exists for a process to eliminate the bottleneck-shaped trench produced after oxidizing the trench side walls. To overcome the shortcomings of the conventional processes, a new process is provided. An object of the present invention is to provide a process for fabricating a trench using STI in which the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom. [0006]
  • SUMMARY OF THE INVENTION
  • To achieve these and other objects, and in view of its purposes, the present invention provides a process for fabricating a trench having a tapered shape, side walls, and a bottom on a silicon substrate. The substrate has an exposed surface. The trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom. The process comprises the following steps: [0007]
  • forming an initial trench having initial trench side walls and a trench bottom extending from the exposed surface into an interior of the substrate; [0008]
  • implanting nitrogen ions on the initial trench side walls so that more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and [0009]
  • oxidizing the trench side walls, thereby creating a trench having the tapered shape. [0010]
  • In a preferred embodiment, the nitrogen ions are implanted on the initial trench side walls at an angle of from about 10 degrees to about 60 degrees relative to the exposed surface. [0011]
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.[0012]
  • BRIEF DESCRIPTION OF THE DRAWING
  • The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures: [0013]
  • FIG. 1 shows in schematic representation a silicon substrate comprising a trench structure having side walls spaced further apart adjacent the trench bottom than adjacent the top of the silicon layer portion of the trench side wall; [0014]
  • FIG. 2A shows the structure of FIG. 1 after the trench has been filled with an oxide, producing a seam in the center of the trench; [0015]
  • FIG. 2B shows the structure of FIG. 2A after the seam has been filled with polysilicon, causing shorts between deposited poly gates; [0016]
  • FIG. 3 shows in schematic representation a silicon substrate; [0017]
  • FIG. 4 shows in schematic representation a silicon substrate having a trench with substantially perpendicular side walls; [0018]
  • FIG. 5 shows in schematic representation a top view of FIG. 4; [0019]
  • FIG. 6 illustrates the angle to the exposed surface in which nitrogen ions are implanted into the trench side walls; [0020]
  • FIG. 7 shows in schematic representation a silicon substrate having a tapered trench structure; and [0021]
  • FIG. 8 shows in schematic representation a tapered trench of a silicon substrate that has been filled with oxide.[0022]
  • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention will next be described with reference to the drawing in which similar numbers indicate the same elements in all figures. Such figures are intended to be illustrative rather than limiting and are included to facilitate the explanation of the apparatus of the present invention. The apparatus is made by the Shallow Trench Isolation (STI) process. The STI process comprises the steps of etching trenches, having side walls and bottoms, in the SOI substrate, oxidizing the silicon layer portions of the trench sidewalls, and filling the trenches with an oxide. [0023]
  • Referring now to the drawing, FIG. 1 shows a side view of a [0024] silicon substrate 1 after the steps of etching a trench 18 and oxidizing those portions 19, 20 of the side walls 24, 26 of the trench 18 comprising a silicon layer 14. The substrate 1 comprises a silicon wafer 10, a buried silicon oxide layer 12 formed on the silicon wafer 10, the silicon layer 14, a silicon nitride layer 16, and the trench 18.
  • After oxidizing the [0025] side walls 24, 26 of the trench 18, the next step in STI processing comprises filling the trench 18 with an oxide 32. As a result of the bottleneck-shape of the trench 18, a shape in which the width of the trench 18 is greater near the bottom then at the top, it is very difficult to fill the trench 18 with an oxide 32. This difficulty results in the formation of a seam 22 in the center of the trench 18 as illustrated in FIG. 2A.
  • The [0026] seam 22 may open up during subsequent processing steps, leading to several problems. For instance, FIG. 2B shows the structure of FIG. 2A after the seam 22 has been filled with polysilicon 40. The polysilicon 40 fills the seam 22 during deposition of poly gates 42 and may cause shorts between the poly gates 42.
  • The present invention provides a process for fabricating a [0027] trench 18 using shallow trench isolation (STI) in which the side walls 24, 26 of the trench 18 are spaced further apart adjacent the exposed surface than adjacent the trench bottom. Forming a trench 18 having this structure eliminates the formation of a seam 22 in the center of the trench 18 when the trench 18 is filled with an oxide 32.
  • FIG. 3 shows a side view of an embodiment of a silicon substrate comprising a silicon-on-insulator (SOI) [0028] substrate 1. In this embodiment, the substrate 1, having an exposed surface 8, comprises a silicon wafer 10, a buried silicon oxide layer 12 formed on the silicon wafer 10, a silicon layer 14, and a silicon nitride layer 16. A thin oxide layer 15 of from about 0.006 μm to about 0.01 μm can optionally be deposited between the silicon layer 14 and the silicon nitride layer 16 to reduce damage to the silicon layer 14 caused by deposition of the silicon nitride layer 16.
  • In a preferred embodiment, the thickness of the [0029] silicon oxide layer 12 is from about 0.1 μm to about 0.4 μm, the thickness of the silicon layer 14 is from about 0.1 μm to about 0.2 μm, and the thickness of the silicon nitride layer 16 is from about 0.1 μm to about 0.15 μm. In a more preferred embodiment, the thickness of the silicon oxide layer 12 is about 0.4 μm, the thickness of the silicon layer 14 is about 0.18 μm, and the thickness of the silicon nitride layer 16 is about 0.12 μm.
  • FIG. 4 shows a side view of a [0030] substrate 1 having an initial trench 18 extending into the interior of the substrate 1. In FIG. 4, standard photomasking and etching of the silicon substrate 1, through the silicon nitride layer 16, thin oxide layer 15 (if present), and silicon layer 14, results in an initial trench 18 having a bottom 21 and four initial trench side walls 24, 26, 28, and 30. Side walls 24 and 26 are shown in FIG. 4. FIG. 5 is a top view of FIG. 4 showing all four side walls 24, 26, 28, and 30 of initial trench 18. Initial trench side walls 24, 26, 28, and 30 are substantially perpendicular to the exposed surface 8 of the substrate 1.
  • To form the [0031] side walls 24, 26, 28, and 30 of initial trench 18 substantially perpendicular to the exposed surface 8, dry etching techniques, which are well known in the art, are preferred. The initial trench 18 can be cleaned using methods commonly known in the art, which typically include a preliminary step of plasma oxidation stripping or immersion in an inorganic resist stripper, followed by the removal of residual organic contaminants and the desorption of remaining atomic and ionic contaminants. S. Wolf & R. N. Tauber discuss such cleaning processes on pages 516-517 of their text, titled Silicon Processing for the VLSI Era, Volume 1—Process Technology (1986).
  • FIG. 6 shows the step of nitrogen ion implantation into the [0032] side walls 24, 26, 28, and 30 of initial trench 18. The nitrogen ions 50 are implanted at an angle (α) to the exposed surface 8 of the substrate 1. Ion implantation is a process in which energetic, charged atoms or molecules are directly introduced into a substrate, such as a silicon wafer. At varying orientations, nitrogen ions 50 are implanted on each side wall 24, 26, 28, and 30 of initial trench 18.
  • In one embodiment, a first position of the [0033] substrate 1 is determined so that nitrogen ions 50 are beamed at a direction parallel to side walls 28 and 30 onto side wall 24. The substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a second position. Nitrogen ions 50 are then beamed at a direction parallel to side walls 24 and 26 onto side wall 28. The substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a third position. Nitrogen ions 50 are then beamed at a direction parallel to side walls 28 and 30 onto side wall 26. The substrate 1 is then rotated by 90 degrees about a rotation axis parallel to the top of the substrate 1 and fixed in a fourth position. Nitrogen ions 50 are then beamed at a direction parallel to side walls 24 and 26 onto side wall 30.
  • The optimal angle (α) of nitrogen ion implantation depends on the thickness of the [0034] silicon nitride layer 16 and the size of the trench 18. In a preferred embodiment, the side walls 24, 26, 28, and 30 of trench 18 are implanted with from about 5 keV to about 15 keV nitrogen ions 50 to a dose of from about 1×1014/cm2 to about 1×1015/cm2, and the nitrogen ions 50 are implanted at an angle (α) of from about 10 to about 60 degrees relative to the exposed surface 8. In a more preferred embodiment, the side walls 24, 26, 28, and 30 of trench 18 are implanted with about 10 keV nitrogen ions 50 to a dose of about 5×1014/cm2 at an angle (α) of about 20 degrees. By implanting nitrogen ions 50 at an angle (α) relative to the exposed surface 8, more nitrogen ions 50 are implanted adjacent the exposed surface 8 than adjacent the bottom 21 of the trench 18.
  • FIG. 7 shows a side view of a resulting tapered [0035] trench 18 a after oxidation of the side walls 24, 26, 28, and 30 of initial trench 18, resulting in tapered side walls 24 a and 26 a. The oxidation rate of the side walls 24, 26, 28, and 30 is affected by nitrogen ion concentration which proportionally retards trench side wall oxidation. The high concentration of nitrogen ions in the silicon nitride layer 16, which forms the portion of the side walls 24 and 26 adjacent the exposed surface 8, inhibits oxidation. In contrast, the silicon layer 14, which forms the portion of the side walls 24 a and 26 a adjacent trench bottom 21, has a lower concentration of nitrogen ions. Oxidation of the portion of the side walls 24 a and 26 a of the trench 18 a adjacent the silicon layer 14 results in oxide formation in proportion to nitrogen ion concentration.
  • Because the [0036] nitrogen ions 50 are implanted at an angle (α) relative to the exposed surface 8, more nitrogen ions 50 are implanted into the portion of the side walls 24 a and 26 a of the trench 18 a adjacent the silicon layer 14 and the bottom 21 of the trench 18 a than in the silicon nitride layer 16 portion of the side walls 24 and 26 adjacent the exposed surface 8, thereby producing a tapered shape upon oxidation. A portion of silicon layer 14 adjacent the side walls 24 a and 26 a of the trench 18 a is also oxidized. In a preferred embodiment, the side walls 24, 26, 28, and 30 are oxidized using dry oxygen at a temperature of about 1,000° C.
  • Following oxidation of the trench sidewalls [0037] 24, 26, 28, and 30, the trench is then filled with an oxide 32. FIG. 8 shows a side view of the tapered trench 18 a shown in FIG. 7 after tapered trench 18 a has been filled with the oxide 32. Following oxide deposition to fill the trench 18 a, steps known in the art can be used to complete an STI structure. In addition, the present invention can be used in bulk STI processes.
  • In one embodiment, a silicon substrate comprising an SOI substrate was formed by the following steps. A 0.4 μm layer of [0038] silicon oxide 12 was formed on a silicon wafer 1 and a 0.18 μm silicon layer 14 was formed on the silicon oxide layer 12 using the separation by implantation of oxygen (SIMOX) process. A 0.008 μm layer of silicon oxide (thin silicon oxide layer 15) was next formed on the silicon layer 14 followed by deposition of a 0.12 μm layer of silicon nitride 16 on the thin silicon oxide layer 15. An initial trench 18 extending from the exposed surface 8 of the substrate 1 into an interior of the substrate was formed by photomasking and plasma etching. The plasma etching was selective to stop at the silicon oxide layer 15, producing a trench depth of 0.308 μm. The initial trench side walls 24, 26, 28, and 30 were implanted with 10 keV nitrogen ions 50 to a dose of 5×1014/cm2 at an angle (α) of 30 degrees with respect to the exterior, exposed surface 8 of the substrate 1. The trench side walls 24, 26, 28, and 30 were next oxidized with dry oxygen at 1,000° C., resulting in a tapered trench 18 a in which the trench side walls 24, 26, 28, and 30 were spaced further apart adjacent the exposed surface 8 of the substrate 1 than adjacent the trench bottom 21.
  • Although illustrated and described above with reference to certain specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention. [0039]

Claims (17)

What is claimed is:
1. A process for fabricating a trench, having a bottom and side walls defining a tapered shape, on a silicon substrate, the substrate having an exposed surface, wherein the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom, the process comprising:
forming an initial trench having initial trench side walls and the trench bottom extending from the exposed surface into an interior of the substrate;
implanting nitrogen ions on the initial trench side walls wherein more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and
oxidizing the trench side walls, thereby creating a trench having the tapered shape.
2. The process of
claim 1
wherein the initial trench side walls extend into the substrate in a direction substantially perpendicular to the exposed surface and are substantially perpendicular to each other.
3. The process according to
claim 2
wherein the step of implanting the nitrogen ions on the initial trench side walls comprises implanting the ions at an angle from about 10 degrees to about 60 degrees relative to the exposed surface.
4. The process according to
claim 3
wherein the nitrogen ions are implanted on the initial trench side walls at an angle of about 30 degrees relative to the exposed surface.
5. The process according to
claim 1
wherein the step of implanting the nitrogen ions comprises implanting from about 5 kev to about 10 keV nitrogen ions on the initial trench side walls to a dose of from about 1×1014/cm2 to about 1×1015/cm2.
6. The process according to
claim 5
wherein the step of implanting the nitrogen ions comprises implanting about 10 keV nitrogen ions on the initial trench side walls to a dose of about 5×1014/cm2.
7. The process according to
claim 1
wherein the step of forming the initial trench comprises photomasking and etching the substrate.
8. The process according to
claim 7
wherein the etching is dry etching.
9. The process according to
claim 1
wherein the substrate is a silicon-on-insulator substrate comprising a silicon oxide layer having a thickness of from about 0.1 μm to about 0.4 μm on a silicon wafer, a silicon layer having a thickness of from about 0.1 μm to about 0.2 μm on the silicon oxide layer, and a silicon nitride layer having a thickness of from about 0.1 μm to about 0.2 μm on the silicon layer.
10. The process according to
claim 9
wherein the silicon oxide layer has a thickness of about 0.4 μm, the silicon layer has a thickness of about 0.18 μm, and the silicon nitride layer has a thickness of about 0.12 μm.
11. The process according to
claim 9
wherein the substrate further comprises a thin silicon oxide layer having a thickness of from about 0.006 μm to about 0.01 μm between the silicon layer and the silicon nitride layer.
12. The process according to
claim 1
further comprising the step of cleaning the initial trench before the step of oxidizing the trench side walls.
13. A process for fabricating a trench having a bottom and side walls defining a tapered shape on a silicon-on-insulator substrate, the substrate having an exposed surface, wherein the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom, the process comprising:
forming an initial trench having initial trench side walls and the trench bottom extending from the exposed surface into an interior of the substrate by photomasking and dry etching the substrate;
implanting about 10 keV nitrogen ions to a dose of about 5×1014 cm/cm2 on the initial trench side walls at an angle from about 10 degrees to about 60 degrees wherein more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and
oxidizing the trench side walls with dry oxygen at about 1,000° C., thereby creating the tapered shape.
14. The process of
claim 13
wherein the substrate comprises a silicon oxide layer having a thickness of about 0.4 μm on a silicon wafer, a silicon layer having a thickness of about 0.18 μm on the silicon oxide layer, and a silicon nitride layer having a thickness of about 0.12 μm on the silicon layer.
15. A silicon substrate having an exposed surface and a trench having a bottom and side walls defining a tapered shape extending through the exposed surface into the substrate, wherein the trench side walls are spaced further apart adjacent the exposed surface than adjacent the trench bottom, and wherein the trench is fabricated by:
forming an initial trench having initial trench side walls and the trench bottom extending from the exposed surface into the substrate;
implanting nitrogen ions on the initial trench side walls wherein more nitrogen ions are implanted adjacent the exposed surface than adjacent the trench bottom; and
oxidizing the trench side walls, thereby creating a trench having the tapered shape.
16. The substrate according to
claim 15
further comprising a silicon oxide layer on a silicon wafer, a silicon layer on the silicon oxide layer, and a silicon nitride layer on the silicon layer.
17. The substrate according to
claim 16
further comprising a thin silicon oxide layer having a thickness of from about 0.006 μm to about 0.01 μm between the silicon layer and the silicon nitride layer.
US09/837,136 1998-11-20 2001-04-18 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall Expired - Fee Related US6437400B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/837,136 US6437400B2 (en) 1998-11-20 2001-04-18 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/197,168 US6238998B1 (en) 1998-11-20 1998-11-20 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall
US09/837,136 US6437400B2 (en) 1998-11-20 2001-04-18 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/197,168 Division US6238998B1 (en) 1998-11-20 1998-11-20 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall

Publications (2)

Publication Number Publication Date
US20010023112A1 true US20010023112A1 (en) 2001-09-20
US6437400B2 US6437400B2 (en) 2002-08-20

Family

ID=22728325

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/197,168 Expired - Fee Related US6238998B1 (en) 1998-11-20 1998-11-20 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall
US09/837,136 Expired - Fee Related US6437400B2 (en) 1998-11-20 2001-04-18 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/197,168 Expired - Fee Related US6238998B1 (en) 1998-11-20 1998-11-20 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall

Country Status (2)

Country Link
US (2) US6238998B1 (en)
KR (1) KR100348932B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090227086A1 (en) * 2008-03-06 2009-09-10 Roland Hampp Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups
US20100244183A1 (en) * 2009-03-31 2010-09-30 Sanken Electric Co., Ltd. Integrated semiconductor device and method of manufacturing the same
EP2573807A1 (en) * 2011-09-23 2013-03-27 Soitec Semiconductor structure and process for bird's beak reduction
CN103633008A (en) * 2012-08-20 2014-03-12 中国科学院微电子研究所 Shallow trench isolation manufacturing method

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6238998B1 (en) * 1998-11-20 2001-05-29 International Business Machines Corporation Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall
EP1049155A1 (en) * 1999-04-29 2000-11-02 STMicroelectronics S.r.l. Process for manufacturing a SOI wafer with buried oxide regions without cusps
US6150670A (en) * 1999-11-30 2000-11-21 International Business Machines Corporation Process for fabricating a uniform gate oxide of a vertical transistor
US6881645B2 (en) * 2000-08-17 2005-04-19 Samsung Electronics Co., Ltd. Method of preventing semiconductor layers from bending and semiconductor device formed thereby
US7247919B1 (en) 2000-08-25 2007-07-24 Micron Technology, Inc. Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs
US6541350B2 (en) * 2000-11-08 2003-04-01 Macronix International Co., Ltd. Method for fabricating shallow trench isolation
TW499729B (en) * 2001-03-16 2002-08-21 Nanya Technology Corp Method of improving uniformity of oxide layer around trench sidewall and manufacture method of deep trench capacitor
US6551937B2 (en) * 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
US6871942B2 (en) * 2002-04-15 2005-03-29 Timothy R. Emery Bonding structure and method of making
US6774415B2 (en) * 2003-01-02 2004-08-10 International Business Machines Corporation Method and structure for ultra-thin film SOI isolation
US6800530B2 (en) * 2003-01-14 2004-10-05 International Business Machines Corporation Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors
US7176104B1 (en) * 2004-06-08 2007-02-13 Integrated Device Technology, Inc. Method for forming shallow trench isolation structure with deep oxide region
JP2008258265A (en) * 2007-04-02 2008-10-23 Fujitsu Microelectronics Ltd Semiconductor device and method for manufacturing the same
US8906759B2 (en) 2013-02-25 2014-12-09 International Business Machines Corporation Silicon nitride gate encapsulation by implantation
KR101638549B1 (en) * 2014-11-05 2016-07-11 성균관대학교산학협력단 Method for silicon photomultiplier using diffusion barrier and apparatus

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656497A (en) * 1984-11-01 1987-04-07 Ncr Corporation Trench isolation structures
US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
JPS61202426A (en) 1985-03-05 1986-09-08 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US4824795A (en) 1985-12-19 1989-04-25 Siliconix Incorporated Method for obtaining regions of dielectrically isolated single crystal silicon
US5429972A (en) 1994-05-09 1995-07-04 Advanced Micro Devices, Inc. Method of fabricating a capacitor with a textured polysilicon interface and an enhanced dielectric
SG50741A1 (en) 1995-07-26 1998-07-20 Chartered Semiconductor Mfg Method for minimizing the hot carrier effect in m-mosfet devices
US5811347A (en) * 1996-04-29 1998-09-22 Advanced Micro Devices, Inc. Nitrogenated trench liner for improved shallow trench isolation
US5891787A (en) * 1997-09-04 1999-04-06 Advanced Micro Devices, Inc. Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure
US6002160A (en) * 1997-12-12 1999-12-14 Advanced Micro Devices, Inc. Semiconductor isolation process to minimize weak oxide problems
US6358818B1 (en) * 1998-03-04 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming trench isolation regions
JP2000150678A (en) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp Nonvolatile semiconductor memory and fabrication thereof
US6238998B1 (en) * 1998-11-20 2001-05-29 International Business Machines Corporation Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall
US6222230B1 (en) * 1998-12-03 2001-04-24 Advanced Micro Devices, Inc. Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090227086A1 (en) * 2008-03-06 2009-09-10 Roland Hampp Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups
US7892939B2 (en) * 2008-03-06 2011-02-22 Infineon Technologies Ag Threshold voltage consistency and effective width in same-substrate device groups
US20100244183A1 (en) * 2009-03-31 2010-09-30 Sanken Electric Co., Ltd. Integrated semiconductor device and method of manufacturing the same
US8349698B2 (en) * 2009-03-31 2013-01-08 Sanken Electric Co., Ltd. Integrated semiconductor device and method of manufacturing the same
EP2573807A1 (en) * 2011-09-23 2013-03-27 Soitec Semiconductor structure and process for bird's beak reduction
CN103633008A (en) * 2012-08-20 2014-03-12 中国科学院微电子研究所 Shallow trench isolation manufacturing method

Also Published As

Publication number Publication date
US6437400B2 (en) 2002-08-20
US6238998B1 (en) 2001-05-29
KR100348932B1 (en) 2002-08-14
KR20000035091A (en) 2000-06-26

Similar Documents

Publication Publication Date Title
US6238998B1 (en) Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall
US6404014B1 (en) Planar and densely patterned silicon-on-insulator structure
US5610083A (en) Method of making back gate contact for silicon on insulator technology
US5212110A (en) Method for forming isolation regions in a semiconductor device
US5466630A (en) Silicon-on-insulator technique with buried gap
EP0444836A2 (en) Process for forming semiconductor device isolation regions
JP2002324905A (en) Method of forming integrated circuit having body contact
US7115463B2 (en) Patterning SOI with silicon mask to create box at different depths
US5573973A (en) Integrated circuit having a diamond thin film trench arrangement as a component thereof and method
US20110018060A1 (en) Method and structures for improving substrate loss and linearity in soi substrates
US20040241955A1 (en) Method of fabricating shallow trench isolation by ultra-thin simox processing
US5179038A (en) High density trench isolation for MOS circuits
KR0168194B1 (en) Method for forming isolation film on a semiconductor device
US6057214A (en) Silicon-on-insulation trench isolation structure and method for forming
EP1851793A1 (en) Method of fabrication a shallow trench isolation structure with oxide sidewall spacers
US6548345B2 (en) Method of fabricating trench for SOI merged logic DRAM
US4731343A (en) Method for manufacturing insulation separating the active regions of a VLSI CMOS circuit
US5449636A (en) Method for the fabrication of DRAM cell having a trench in the field oxide
US7327008B2 (en) Structure and method for mixed-substrate SIMOX technology
JPH10135321A (en) Method of forming semiconductor element isolating regions
US20020025654A1 (en) Method for manufacturing a semiconductor device
JP2002026022A (en) Method of manufacturing semiconductor device and semiconductor device
US5982006A (en) Active silicon-on-insulator region having a buried insulation layer with tapered edge
US6350659B1 (en) Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate
US6479328B1 (en) Method of fabricating SOI wafer

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20100820