US20010022530A1 - Dual independently clocked analog-to-digital conversion for a digital power amplifier - Google Patents
Dual independently clocked analog-to-digital conversion for a digital power amplifier Download PDFInfo
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- US20010022530A1 US20010022530A1 US09/796,845 US79684501A US2001022530A1 US 20010022530 A1 US20010022530 A1 US 20010022530A1 US 79684501 A US79684501 A US 79684501A US 2001022530 A1 US2001022530 A1 US 2001022530A1
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- electronic device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
Definitions
- the present invention relates to noise-shaping digital amplifiers, and specifically to techniques for using and generating multiple and independent clocks in such amplifiers. It should be noted at the outset that although the invention is described herein with reference to a bandpass (e.g., RF) implementation, the present invention is also applicable to other amplifier configurations such as, for example, baseband audio amplifiers and motor drive circuits.
- bandpass e.g., RF
- FIG. 1 shows an RF bandpass noise-shaping amplifier 100 designed according to techniques described in U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes.
- RF amplifier 100 includes a frequency selective network 102 which, using continuous-time feedback, noise shapes the modulated RF input.
- Network 102 comprises at least one resonator stage having a transfer function designed to pass a band centered around 900 MHz.
- A/D converter 104 converts the noise shaped RF signal to digital data using a sampling frequency fs which, in this example, is 3.6 GHz.
- A/D converter 104 may comprise a comparator.
- Gate drive circuitry 106 takes the pulse train from A/D converter 104 and generates gate drive for each of FETs 108 and 110 of the power output stage of amplifier 100 .
- the output power stage shown includes three inductors L 1 , L 2 and L 3 , and capacitor C 1 . This configuration creates two separate resonances at nodes A and B respectively when the corresponding one of FETs 108 and 110 is off.
- the continuous-time feedback to frequency selective network 102 is provided via feedback path 112 .
- the output signal of the power stage is passed to a matching network 114 which passes the output RF signal to antenna 116 for transmission.
- the amplifier configuration of FIG. 1 allows for two quantization states. With two quantization states there is a high number of signal transitions resulting in high drive losses. Therefore, it is desirable to provide techniques by which such losses may be mitigated or eliminated.
- an amplifier architecture in which multi-level switching is enabled. That is, the amplifier architecture described herein exhibits more than two quantization states. This is achieved, in part, with parallel signal paths each of which has its own sampling circuitry.
- the multiple quantization states includes a state in which there is no signal output, thereby avoiding the undesirable switching losses described above.
- the clock signals for the different sampling circuits are independently developed resulting in a variety of other advantages.
- the present invention provides an electronic device which includes at least two sampling circuits, and at least two switching stages configured in parallel. Each of the switching stages is coupled to one of the sampling circuits.
- the sampling circuits and the switching stages enable the electronic device to exhibit more than two quantization states.
- the electronic device further includes clock generation circuitry for generating independent clock signals for each of the sampling circuits.
- FIG. 1 is a simplified schematic of a first amplifier configuration
- FIG. 2 is a simplified schematic of a second amplifier configuration for use with the present invention.
- FIG. 3 shows clock generation circuitry designed according to a specific embodiment of the present invention.
- FIG. 2 shows an RF bandpass noise-shaping amplifier 200 designed according to the present invention as well as techniques described in U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes.
- RF amplifier 200 includes a frequency selective network 202 which, using continuous-time feedback, noise shapes the modulated RF input.
- network 202 comprises at least one resonator stage having a transfer function designed to pass a band centered around 900 MHz.
- Two A/D converters 204 a and 204 b convert the noise shaped RF signal to digital data using independently generated clock signals at a nominal sampling frequency fs (i.e., fs 1 and fs 2 ) which, according to a specific embodiment, is 3.6 GHz.
- A/D converters 204 a and 204 b comprise two comparators configured to implement three-level switching.
- Gate drive circuits 206 a and 206 b take the pulse trains from A/D converters 204 a and 204 b, respectively, and generate gate drive for their pair of transistors, i.e., FETs 208 a and 210 a or FETs 208 b and 210 b. Each pair of transistors has two separate resonances due to resonator circuits 211 and 211 a respectively. That is, the power stage comprising FETs 208 and 210 has separate resonances at nodes A and B, while the stage comprising FETs 208 a and 210 a has separate resonances at nodes A′ and B′.
- Continuous-time feedback is provided to frequency selective network 202 via feedback path 212 and adder 213 .
- the output signals of the power stages are passed to a matching network 214 which passes the output RF signal to antenna 216 for transmission.
- adder 213 may be implemented by tapping into matching network 214 once the signals are combined.
- the clocks for the respective comparators 204 a and 204 b may be generated from independent sources.
- the clocks for A/D converters 204 a and 204 b i.e., fs 1 and fs 2
- fs 1 and fs 2 are generated from at least some of the resonances at nodes A, B, A′ and B′.
- fs 1 is provided in part by the resonance at node A and in part by the resonance at node B
- fs 2 is provided in part by the resonance at node A′ and in part by the resonance at node B′.
- a comparator 302 compares the voltage at node A (i.e., V A ) to a reference voltage less than the positive supply of the power output stage, preferably ground. When node A resonates above and below this reference at 3.6 GHz, a 3.6 GHz clock is generated. Likewise a comparator 304 compares the voltage at node B (i.e., V B ) to a reference voltage greater than ground (or the negative rail), preferably the positive supply, thereby generating a 3.6 GHz clock when node B resonates.
- Multiplexer 308 selects between its inputs in response to a control signal generated by control logic (not shown), thereby generating the clock signal fs 1 .
- the clock signal may be started by generation of a pulse which gets one of the resonances going.
- clock generation technique is that, because the clock is generated at least in part from the resonances at nodes A and B, when these resonances move around (e.g., due to reflections and process variations), the clock to the corresponding comparator also moves around in a corresponding manner. That is, the gate edges generated by A/D converter 204 a and gate drive circuitry 206 a more closely match the timing of the output stage resonances than if an independently generated A/D clock were used.
- the pattern dependent jitter on the A/D converter clock due to the manner in which the resonances move around effectively scrambles the sample rate and “smears” sampling frequency dependent tones into white noise, thereby eliminating undesirable harmonics about the sampling frequency in the output power spectrum.
- “dithering” of the A/D converter clock may be intentionally introduced in a controlled manner irrespective of how the clock was generated (e.g, independent vs. self-timed) to smear the noise tones dependent on the sampling frequency.
- a ring oscillator 306 may also be included in the clock generation circuitry as an additional source of the clock signal. This may be desirable because the damping resistance associated with the output resonant circuits could be high enough to cause the resonances to decay sufficiently such that the oscillations no longer trip comparators 302 and 304 and the clock (and therefore the gate signal) locks up. Therefore, after some number of pulses generated from one of the resonance nodes (which may be determined from the damping resistance associated with the resonant circuits of the output stage) multiplexer 308 is controlled to select the input from the ring oscillator as the clock signal until the resonance on the other node begins.
- the ring oscillator starts and stops synchronously with the resonance oscillations so that the handoffs between clock sources are smooth.
- the ring oscillator may also be used at start up time.
- FIG. 3 shows one implementation by which generation of fs 1 and fs 2 may be accomplished. It will be understood, however that there are other ways in which these clock signals may be generated.
- the difference between fs 1 and fs 2 is intentionally introduced and controlled to derive the benefit of this effect.
- the difference between fs 1 and fs 2 is controlled to derive this benefit. Even where fs 1 and fs 2 are derived from a single source, the difference may be introduced to derive the benefit and still remain within the scope of the invention.
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Abstract
Description
- The present application claims priority from U.S. Provisional Patent Application No. 60/186,831 for DUAL INDEPENDENTLY CLOCKED ANALOG-TO-DIGITAL CONVERSION FOR A DIGITAL POWER AMPLIFIER filed on Mar. 3, 2000, the entirety of which is incorporated herein by reference for all purposes.
- The present invention relates to noise-shaping digital amplifiers, and specifically to techniques for using and generating multiple and independent clocks in such amplifiers. It should be noted at the outset that although the invention is described herein with reference to a bandpass (e.g., RF) implementation, the present invention is also applicable to other amplifier configurations such as, for example, baseband audio amplifiers and motor drive circuits.
- FIG. 1 shows an RF bandpass noise-
shaping amplifier 100 designed according to techniques described in U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes.RF amplifier 100 includes a frequencyselective network 102 which, using continuous-time feedback, noise shapes the modulated RF input.Network 102 comprises at least one resonator stage having a transfer function designed to pass a band centered around 900 MHz. - A/
D converter 104 converts the noise shaped RF signal to digital data using a sampling frequency fs which, in this example, is 3.6 GHz. A/D converter 104 may comprise a comparator. -
Gate drive circuitry 106 takes the pulse train from A/D converter 104 and generates gate drive for each ofFETs amplifier 100. The output power stage shown includes three inductors L1, L2 and L3, and capacitor C1. This configuration creates two separate resonances at nodes A and B respectively when the corresponding one ofFETs - The continuous-time feedback to frequency
selective network 102 is provided viafeedback path 112. The output signal of the power stage is passed to amatching network 114 which passes the output RF signal toantenna 116 for transmission. - As will be understood, the amplifier configuration of FIG. 1 allows for two quantization states. With two quantization states there is a high number of signal transitions resulting in high drive losses. Therefore, it is desirable to provide techniques by which such losses may be mitigated or eliminated.
- According to the present invention, an amplifier architecture is provided in which multi-level switching is enabled. That is, the amplifier architecture described herein exhibits more than two quantization states. This is achieved, in part, with parallel signal paths each of which has its own sampling circuitry. The multiple quantization states includes a state in which there is no signal output, thereby avoiding the undesirable switching losses described above. According to a specific embodiment, the clock signals for the different sampling circuits are independently developed resulting in a variety of other advantages.
- Thus, the present invention provides an electronic device which includes at least two sampling circuits, and at least two switching stages configured in parallel. Each of the switching stages is coupled to one of the sampling circuits. The sampling circuits and the switching stages enable the electronic device to exhibit more than two quantization states. The electronic device further includes clock generation circuitry for generating independent clock signals for each of the sampling circuits.
- A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
- FIG. 1 is a simplified schematic of a first amplifier configuration;
- FIG. 2 is a simplified schematic of a second amplifier configuration for use with the present invention; and
- FIG. 3 shows clock generation circuitry designed according to a specific embodiment of the present invention.
- FIG. 2 shows an RF bandpass noise-
shaping amplifier 200 designed according to the present invention as well as techniques described in U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes.RF amplifier 200 includes a frequencyselective network 202 which, using continuous-time feedback, noise shapes the modulated RF input. According to a specific embodiment,network 202 comprises at least one resonator stage having a transfer function designed to pass a band centered around 900 MHz. - Two A/
D converters D converters -
Gate drive circuits D converters resonator circuits stage comprising FETs - Continuous-time feedback is provided to frequency
selective network 202 viafeedback path 212 andadder 213. The output signals of the power stages are passed to amatching network 214 which passes the output RF signal toantenna 216 for transmission. As will be understood,adder 213 may be implemented by tapping into matchingnetwork 214 once the signals are combined. - Having two comparators for A/
D converters - The clocks for the
respective comparators D converters - The schematic of FIG. 3 shows one implementation by which this may be accomplished. Only generation of fs1 will be described. It will be understood, however that fs2 may be generated in much the same way. A
comparator 302 compares the voltage at node A (i.e., VA) to a reference voltage less than the positive supply of the power output stage, preferably ground. When node A resonates above and below this reference at 3.6 GHz, a 3.6 GHz clock is generated. Likewise acomparator 304 compares the voltage at node B (i.e., VB) to a reference voltage greater than ground (or the negative rail), preferably the positive supply, thereby generating a 3.6 GHz clock when node B resonates.Multiplexer 308 selects between its inputs in response to a control signal generated by control logic (not shown), thereby generating the clock signal fs1. When the circuit is first turned on, the clock signal may be started by generation of a pulse which gets one of the resonances going. - One advantageous consequence of this clock generation technique is that, because the clock is generated at least in part from the resonances at nodes A and B, when these resonances move around (e.g., due to reflections and process variations), the clock to the corresponding comparator also moves around in a corresponding manner. That is, the gate edges generated by A/
D converter 204 a andgate drive circuitry 206 a more closely match the timing of the output stage resonances than if an independently generated A/D clock were used. - Moreover, the pattern dependent jitter on the A/D converter clock due to the manner in which the resonances move around effectively scrambles the sample rate and “smears” sampling frequency dependent tones into white noise, thereby eliminating undesirable harmonics about the sampling frequency in the output power spectrum. In fact, according to the present invention, “dithering” of the A/D converter clock may be intentionally introduced in a controlled manner irrespective of how the clock was generated (e.g, independent vs. self-timed) to smear the noise tones dependent on the sampling frequency.
- Referring back to FIG. 3 and according to a more specific embodiment of the invention, a
ring oscillator 306 may also be included in the clock generation circuitry as an additional source of the clock signal. This may be desirable because the damping resistance associated with the output resonant circuits could be high enough to cause the resonances to decay sufficiently such that the oscillations no longertrip comparators multiplexer 308 is controlled to select the input from the ring oscillator as the clock signal until the resonance on the other node begins. According to a specific embodiment, the ring oscillator starts and stops synchronously with the resonance oscillations so that the handoffs between clock sources are smooth. The ring oscillator may also be used at start up time. - In addition to the randomization of switching frequency dependent noise, there are additional noise benefits due to the independent nature of the two clocks. This is related to the fact that the average clock frequencies fs1 and fs2 typically differ by some relatively constant amount which is, in essence, the smallest repetitive sample rate experienced by the amplifier. That is, the difference between fs1 and fs2 results in an “effective” sample frequency which is much higher than either fs1 or fs2. As a result, any undesirable tones or “radiators” in the output noise spectrum which depend on the sample frequency are moved way out of the band of interest due to this very high “effective” sample frequency.
- The schematic of FIG. 3 shows one implementation by which generation of fs1 and fs2 may be accomplished. It will be understood, however that there are other ways in which these clock signals may be generated.
- According to a specific embodiment, the difference between fs1 and fs2 is intentionally introduced and controlled to derive the benefit of this effect. According to a more specific embodiment in which the clocks fs1 and fs2 are generated from stable independent sources other than the resonance nodes, the difference between fs1 and fs2 is controlled to derive this benefit. Even where fs1 and fs2 are derived from a single source, the difference may be introduced to derive the benefit and still remain within the scope of the invention.
- While the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. Therefore, the scope of the invention should be determined with reference to the appended claims.
Claims (24)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US09/796,845 US6348836B2 (en) | 2000-03-03 | 2001-02-28 | Dual independently clocked analog-to-digital conversion for a digital power amplifier |
PCT/US2001/006780 WO2001067596A1 (en) | 2000-03-03 | 2001-03-01 | Rf communication system using an rf digital amplifier |
AU2001245398A AU2001245398A1 (en) | 2000-03-03 | 2001-03-01 | Rf communication system using an rf digital amplifier |
Applications Claiming Priority (2)
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US18683100P | 2000-03-03 | 2000-03-03 | |
US09/796,845 US6348836B2 (en) | 2000-03-03 | 2001-02-28 | Dual independently clocked analog-to-digital conversion for a digital power amplifier |
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US6348836B2 US6348836B2 (en) | 2002-02-19 |
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US6549069B2 (en) * | 2000-03-03 | 2003-04-15 | Tripath Technology, Inc. | Self-timed switching for a digital power amplifier |
JP2002158549A (en) * | 2000-11-17 | 2002-05-31 | Sony Corp | Digital power amplifier system |
US7200187B2 (en) * | 2001-07-26 | 2007-04-03 | O'brien Thomas J | Modulator for digital amplifier |
US20050069301A1 (en) * | 2003-09-30 | 2005-03-31 | Valeo Electrical Systems, Inc. | Reduction of interference caused by PWM motors |
TWI336166B (en) * | 2006-02-20 | 2011-01-11 | Realtek Semiconductor Corp | Digital amplifier and thereof method |
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US4326170A (en) * | 1980-06-09 | 1982-04-20 | Siemens Corporation | High power and/or high voltage switching operational amplifier |
US4667144A (en) * | 1986-06-03 | 1987-05-19 | The United States Of America As Represented By The Secretary Of The Air Force | High frequency, high voltage MOSFET isolation amplifier |
JPH0728181B2 (en) * | 1988-12-28 | 1995-03-29 | パイオニア株式会社 | Pulse width modulation amplifier circuit |
US5023566A (en) | 1989-12-21 | 1991-06-11 | General Electric Company | Driver for a high efficiency, high frequency Class-D power amplifier |
US5479337A (en) | 1993-11-30 | 1995-12-26 | Kaiser Aerospace And Electronics Corporation | Very low power loss amplifier for analog signals utilizing constant-frequency zero-voltage-switching multi-resonant converter |
US5781067A (en) * | 1996-04-26 | 1998-07-14 | Tota; Tasleem | Electronic inductive switching power amplifier |
US5777512A (en) | 1996-06-20 | 1998-07-07 | Tripath Technology, Inc. | Method and apparatus for oversampled, noise-shaping, mixed-signal processing |
US6130910A (en) * | 1997-11-03 | 2000-10-10 | Motorola, Inc. | Method and apparatus for high efficiency wideband power amplification |
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