US20010020889A1 - Antifuse programming circuit - Google Patents
Antifuse programming circuit Download PDFInfo
- Publication number
- US20010020889A1 US20010020889A1 US09/739,294 US73929400A US2001020889A1 US 20010020889 A1 US20010020889 A1 US 20010020889A1 US 73929400 A US73929400 A US 73929400A US 2001020889 A1 US2001020889 A1 US 2001020889A1
- Authority
- US
- United States
- Prior art keywords
- antifuse
- programming circuit
- negative voltage
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
Definitions
- the present invention relates to a semiconductor device; and, more particularly, to an antifuse programming circuit for performing a programming operation without causing any stress to an antifuse element.
- FIG. 1 there is shown a schematic diagram of a conventional antifuse programming circuit.
- the conventional antifuse programming circuit 10 includes a program signal generator 11 , an antifuse element 12 and a diode-connected NMOS transistor 13 .
- the program signal generator 11 provides a negative voltage signal used for programming the antifuse element 12 .
- a node N between the antifuse element 12 and the diode-connected NMOS transistor 13 is set to a floating state.
- an antifuse programming circuit comprising: an antifuse element, the antifuse element being programmable according to a voltage difference between both terminals thereof; a control logic means for generating a control signal in response to internal address signals and an external address signal; a negative voltage generation means, coupled to the antifuse element, for generating a negative voltage signal; and a power connection control means, in response to the control signal, for coupling the negative voltage signal to a ground terminal when the antifuse element is in an unprogrammed state.
- FIG. 1 is a schematic diagram showing a conventional antifuse programming circuit
- FIG. 2 is a schematic diagram illustrating an antifuse programming circuit in accordance with the present invention.
- FIG. 2 is a schematic diagram illustrating an antifuse programming circuit in accordance with the present invention.
- the antifuse programming circuit 20 in accordance with the present invention includes a control logic circuit 21 , a power connection controller 22 , a negative voltage generator 23 and an antifuse element 24 .
- the power connection controller 22 and the negative voltage generator 23 are operated under a control of the control logic circuit 21 . That is, in an unprogrammed state, an output of the negative voltage generator 23 is electrically coupled to a ground terminal GND via the power connection controller 22 .
- the control logic circuit 21 receives internal address signals REPAIR_X_ADD and REPAIR_Y_ADD and an external address signal PGM_ACT_DLY to generate a control signal for controlling an output of the negative voltage generator 23 .
- the control logic circuit 21 includes a NOR gate 211 for NORing the internal address signals REPAIR_X_ADD and REPAIR_Y_ADD, an inverter 212 for inverting an output of the NOR gate 211 , and a NAND gate 213 for NANDing the external address signal PGM_ACT_DLY and an output of the inverter 212 .
- the power connection controller 22 includes a pull down unit 220 for pulling down a power potential VCC, a first inversion unit 221 , which is coupled to the pull down unit 220 , for inverting the control signal, a second inversion unit 222 , which is coupled to the pull down unit 220 , for inverting an output of the first inversion unit 221 , and a switching unit 223 for coupling the output of the negative voltage generator 23 in response to an output of the second inversion unit 222 .
- the pull down unit 220 is implemented with a plurality of diode-connected PMOS transistors P 3 and P 4 that are serially coupled between a power terminal VCC and the first inversion unit 221 .
- the switching unit 223 is implemented with an NMOS transistor M 3 , coupled between the power terminal VCC and the antifuse element 24 , whose gate receives an output of the second inversion unit 222 .
- the first inversion unit 221 outputs a low level signal via an output node N 2 so that a PMOS transistor P 2 contained in the second inversion unit 222 is turned on.
- a voltage level of a node N 3 is transferred to an output node N 3 of the second inversion unit 222 via a turned-on PMOS transistor P 2 .
- the voltage level of the node N 3 is reduced in proportion to the number of diode-connected PMOS transistors. As a result, a reduced voltage level is applied to the gate of the NMOS transistor M 3 so that the NMOS transistor M 3 is correctly operated.
- the NMOS transistor M 3 is turned on in response to the output of the second inversion unit 222 so that the output of the negative voltage generator 23 is electrically coupled to the ground terminal GND. Therefore, an undesired stress caused due to the negative threshold voltage can be prevented.
- control logic circuit 21 provides the control of a low level
- an NMOS transistor M 1 and a PMOS transistor P 1 contained in the first inversion unit 221 are turned off and on, respectively.
- a voltage level of the node N 3 is transferred to the output node N 2 of the first inversion unit 221 .
- a voltage level that is pulled down through the pull down unit 220 is applied to the gate of the NMOS transistor M 2 so that the NMOS transistor M 2 is turned on. Since the negative voltage signal is applied to the gate of the NMOS transistor M 3 via a turned-on NMOS transistor M 2 , the negative voltage signal is isolated from the ground terminal GND and the antifuse element 24 is programmed.
- the antifuse programming circuit 20 in accordance with the present invention can prevent the stress to the antifuse element by coupling the negative voltage signal to the ground terminal in an unprogrammed state, thereby increasing a lift span of the antifuse element.
Abstract
Description
- The present invention relates to a semiconductor device; and, more particularly, to an antifuse programming circuit for performing a programming operation without causing any stress to an antifuse element.
- In FIG. 1, there is shown a schematic diagram of a conventional antifuse programming circuit.
- The conventional
antifuse programming circuit 10 includes aprogram signal generator 11, anantifuse element 12 and a diode-connectedNMOS transistor 13. Theprogram signal generator 11 provides a negative voltage signal used for programming theantifuse element 12. In an unprogrammed state, a node N between theantifuse element 12 and the diode-connectedNMOS transistor 13 is set to a floating state. - When the negative voltage signal is provided to the node N, a voltage difference between two terminals of the
antifuse element 12 is greatly large so that an insulating material used to form theantifuse element 12 is broken down. In the floating state, a negative threshold voltage, i.e., −Vt, is provided to the node N. Thus, the voltage difference between both terminals of theantifuse element 12 becomes very small, so that the insulating material is not broken down. - However, a successive stress is caused to the
antifuse element 12 due to the negative threshold voltage. As a result, there is a problem that a life span of theantifuse element 12 is shortened. - It is, therefore, an object of the present invention to provide an antifuse programming circuit for performing a programming operation without causing any stress to an antifuse element.
- In accordance with an aspect of the present invention, there is provided an antifuse programming circuit, comprising: an antifuse element, the antifuse element being programmable according to a voltage difference between both terminals thereof; a control logic means for generating a control signal in response to internal address signals and an external address signal; a negative voltage generation means, coupled to the antifuse element, for generating a negative voltage signal; and a power connection control means, in response to the control signal, for coupling the negative voltage signal to a ground terminal when the antifuse element is in an unprogrammed state.
- Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:
- FIG. 1 is a schematic diagram showing a conventional antifuse programming circuit; and
- FIG. 2 is a schematic diagram illustrating an antifuse programming circuit in accordance with the present invention.
- FIG. 2 is a schematic diagram illustrating an antifuse programming circuit in accordance with the present invention.
- Referring to FIG. 2, the antifuse programming circuit20 in accordance with the present invention includes a
control logic circuit 21, apower connection controller 22, anegative voltage generator 23 and anantifuse element 24. - The
power connection controller 22 and thenegative voltage generator 23 are operated under a control of thecontrol logic circuit 21. That is, in an unprogrammed state, an output of thenegative voltage generator 23 is electrically coupled to a ground terminal GND via thepower connection controller 22. - The
control logic circuit 21 receives internal address signals REPAIR_X_ADD and REPAIR_Y_ADD and an external address signal PGM_ACT_DLY to generate a control signal for controlling an output of thenegative voltage generator 23. Thecontrol logic circuit 21 includes aNOR gate 211 for NORing the internal address signals REPAIR_X_ADD and REPAIR_Y_ADD, aninverter 212 for inverting an output of theNOR gate 211, and aNAND gate 213 for NANDing the external address signal PGM_ACT_DLY and an output of theinverter 212. - The
power connection controller 22 includes a pull downunit 220 for pulling down a power potential VCC, afirst inversion unit 221, which is coupled to the pull downunit 220, for inverting the control signal, asecond inversion unit 222, which is coupled to the pull downunit 220, for inverting an output of thefirst inversion unit 221, and aswitching unit 223 for coupling the output of thenegative voltage generator 23 in response to an output of thesecond inversion unit 222. - The pull down
unit 220 is implemented with a plurality of diode-connected PMOS transistors P3 and P4 that are serially coupled between a power terminal VCC and thefirst inversion unit 221. - The
switching unit 223 is implemented with an NMOS transistor M3, coupled between the power terminal VCC and theantifuse element 24, whose gate receives an output of thesecond inversion unit 222. - In case where the
control logic circuit 21 provides the control signal of a high level, thefirst inversion unit 221 outputs a low level signal via an output node N2 so that a PMOS transistor P2 contained in thesecond inversion unit 222 is turned on. As a result, a voltage level of a node N3 is transferred to an output node N3 of thesecond inversion unit 222 via a turned-on PMOS transistor P2. - At this time, if an external power potential is directly applied to a gate of the NMOS transistor M3 contained in the
switching unit 223 and the negative voltage signal is applied to a source of the NMOS transistor M3, a voltage difference between the gate and the source becomes greatly large so that the NMOS transistor M3 is broken down. This phenomenon can be prevented by employing the pull downunit 220. - The voltage level of the node N3 is reduced in proportion to the number of diode-connected PMOS transistors. As a result, a reduced voltage level is applied to the gate of the NMOS transistor M3 so that the NMOS transistor M3 is correctly operated.
- That is, the NMOS transistor M3 is turned on in response to the output of the
second inversion unit 222 so that the output of thenegative voltage generator 23 is electrically coupled to the ground terminal GND. Therefore, an undesired stress caused due to the negative threshold voltage can be prevented. - In case where the
control logic circuit 21 provides the control of a low level, an NMOS transistor M1 and a PMOS transistor P1 contained in thefirst inversion unit 221 are turned off and on, respectively. Thus, a voltage level of the node N3 is transferred to the output node N2 of thefirst inversion unit 221. - Then, a voltage level that is pulled down through the pull down
unit 220 is applied to the gate of the NMOS transistor M2 so that the NMOS transistor M2 is turned on. Since the negative voltage signal is applied to the gate of the NMOS transistor M3 via a turned-on NMOS transistor M2, the negative voltage signal is isolated from the ground terminal GND and theantifuse element 24 is programmed. - As described above, the antifuse programming circuit20 in accordance with the present invention can prevent the stress to the antifuse element by coupling the negative voltage signal to the ground terminal in an unprogrammed state, thereby increasing a lift span of the antifuse element.
- Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (6)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1999-65008 | 1999-12-29 | ||
KR10-1999-0065008A KR100368307B1 (en) | 1999-12-29 | 1999-12-29 | Antifuse program circuit |
KR99-65008 | 1999-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010020889A1 true US20010020889A1 (en) | 2001-09-13 |
US6333667B2 US6333667B2 (en) | 2001-12-25 |
Family
ID=19632214
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/739,294 Expired - Fee Related US6333667B2 (en) | 1999-12-29 | 2000-12-19 | Antifuse programming circuit |
Country Status (3)
Country | Link |
---|---|
US (1) | US6333667B2 (en) |
JP (1) | JP4434498B2 (en) |
KR (1) | KR100368307B1 (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100328447B1 (en) * | 2000-02-21 | 2002-03-16 | 박종섭 | Antifuse repair circuit |
KR100439104B1 (en) * | 2002-07-11 | 2004-07-05 | 주식회사 하이닉스반도체 | Anti fuse control circuit |
US6775197B2 (en) * | 2002-11-27 | 2004-08-10 | Novocell Semiconductor, Inc. | Non-volatile memory element integratable with standard CMOS circuitry and related programming methods and embedded memories |
US6775171B2 (en) * | 2002-11-27 | 2004-08-10 | Novocell Semiconductor, Inc. | Method of utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements and related embedded memories |
US6816427B2 (en) * | 2002-11-27 | 2004-11-09 | Novocell Semiconductor, Inc. | Method of utilizing a plurality of voltage pulses to program non-volatile memory elements and related embedded memories |
JP3878586B2 (en) * | 2003-07-17 | 2007-02-07 | 株式会社東芝 | Read / program potential generation circuit |
JP2005116048A (en) * | 2003-10-07 | 2005-04-28 | Elpida Memory Inc | Anti-fuse programming circuit |
JP4772328B2 (en) * | 2005-01-13 | 2011-09-14 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US8679861B2 (en) | 2007-11-29 | 2014-03-25 | International Business Machines Corporation | Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip |
US9552890B2 (en) | 2014-02-25 | 2017-01-24 | Nxp Usa, Inc. | Antifuse with bypass diode and method thereof |
US9385190B2 (en) | 2014-03-04 | 2016-07-05 | Freescale Semiconductor, Inc. | Deep trench isolation structure layout and method of forming |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5793224A (en) * | 1996-06-18 | 1998-08-11 | Micron Technology, Inc. | Voltage generator for antifuse programming |
US6054893A (en) * | 1997-04-10 | 2000-04-25 | Institute Of Microelectronics | Low current differential fuse circuit |
US5978297A (en) * | 1998-04-28 | 1999-11-02 | Micron Technology, Inc. | Method and apparatus for strobing antifuse circuits in a memory device |
KR100359855B1 (en) * | 1998-06-30 | 2003-01-15 | 주식회사 하이닉스반도체 | Anti-Fuse Programming Circuit Using Variable Voltage Generator |
KR100321169B1 (en) * | 1998-06-30 | 2002-05-13 | 박종섭 | Anti-fuse programming circuit |
US6240033B1 (en) * | 1999-01-11 | 2001-05-29 | Hyundai Electronics Industries Co., Ltd. | Antifuse circuitry for post-package DRAM repair |
-
1999
- 1999-12-29 KR KR10-1999-0065008A patent/KR100368307B1/en not_active IP Right Cessation
-
2000
- 2000-12-19 US US09/739,294 patent/US6333667B2/en not_active Expired - Fee Related
-
2001
- 2001-01-04 JP JP2001000142A patent/JP4434498B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2001243787A (en) | 2001-09-07 |
JP4434498B2 (en) | 2010-03-17 |
KR20010065140A (en) | 2001-07-11 |
KR100368307B1 (en) | 2003-01-24 |
US6333667B2 (en) | 2001-12-25 |
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