US20010020851A1 - High-speed programmable interconnect - Google Patents
High-speed programmable interconnect Download PDFInfo
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- US20010020851A1 US20010020851A1 US09/738,403 US73840300A US2001020851A1 US 20010020851 A1 US20010020851 A1 US 20010020851A1 US 73840300 A US73840300 A US 73840300A US 2001020851 A1 US2001020851 A1 US 2001020851A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17792—Structural details for adapting physical parameters for operating speed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.
Description
- This application claims priority from U.S. provisional application Ser. No. 60/049,275, filed Jun. 10, 1997; Ser. No. 60/049,478, filed Jun. 13, 1997; Ser. No. 60/049,246, filed Jun. 10, 1997; Ser. No. 60/052,990, filed Jun. 10, 1997; Ser. No. 60/049,247, filed Jun. 10, 1997; Ser. No. 60/049,243, filed Jun. 10, 1997; Ser. No. 60/050,953, filed Jun. 13, 1997; and Ser. No. 60/049,245, filed Jun. 10, 1997, all of which are incorporated herein by reference for all purposes.
- The present invention relates to the field of programmable logic devices, and more particularly, to interconnection resources for programmable logic devices.
- Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user. Altera's FLEX® line of programmable logic are among the most advanced and successful programmable logic devices. The FLEX architecture provides a large matrix of small logic elements (also known as macrocells) that can be programmably configured and interconnected to provide desired logic functions.
- In many programmable logic devices, for example, a number of logic elements are arranged in groups to form larger entities referred to as logic array blocks (“LABs”). The various LABs are arranged in a two-dimensional array and are connectable to each other and to I/O pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as horizontal interconnect and vertical interconnect or collectively as “global” interconnect lines. In Altera's line of production these may include what are referred to as “Horizontal FastTracks™” and “Vertical FastTracks™.”
- Each logic element can perform various combinational and registered logical operations. A local interconnect resource is also provided to allow the logic elements in a LAB to share signals without using the global interconnection resources. Additional detail regarding the FLEX devices may be found, for example, in Altera's Data Book, January 1998, along with U.S. Pat. Nos. 5,260,610 and 5,260,611, all of which are incorporated herein by reference for all purposes.
- These logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. For example, a large portion of the delay in the critical path is due to delay in the interconnect resources. A certain amount of delay exists in the connection between the global interconnect structure and the LABs. Thus a faster global interconnect can increase the overall system performance significantly.
- Another aspect of programmable logic integrated circuits that may be improved is the programming flexibility of the interconnect resources in the logic device. In currently available devices, a signal may be routed from a vertical conductor to a horizontal conductor without passing through a logic element, but for a signal to be routed from a horizontal conductor to a vertical conductor, it must pass through a logic element. Also, currently available devices do not provide complete flexibility in routing between horizontal and vertical lines. For example, at a particular junction, a vertical conductor may only be connected to a single horizontal conductor. It is desirable to be able to select from among a plurality of vertical conductors as the destination, thereby increasing the routing flexibility of the logic device.
- For at least the above reasons, a PLD which provides faster and more flexible interconnect resources is needed.
- An improved programmable logic integrated circuit with high-speed interconnection resources and greater routability is described.
- In accordance with a first aspect of the present invention, a faster interconnection between the horizontal interconnect resource and the local interconnect is provided. The local interconnect provides a path to the logic inputs of the logic elements. A signal regeneration circuit is provided in the path between horizontal conductors and the local interconnection. The signal regeneration circuit is preferably a pair of cross-coupled inverters that isolate the capacitance of the horizontal interconnect resource from the local interconnect, thereby allowing the switching to occur at a faster rate. It also boosts the signal allowing for faster switching operation.
- In accordance with another aspect of the present invention, improved routability between the horizontal and vertical interconnects is described. A path is provided allowing the selective routing of signals from the horizontal interconnect to the vertical interconnect, without passing through a logic element. The horizontal interconnect may be selectively coupled to several of the vertical interconnect conductors in some embodiments.
- In accordance with yet another aspect of the present invention, improved routability between the vertical and horizontal interconnects is described. A path is provided to allow a horizontal interconnect to be routed to any of a plurality of vertical interconnect conductors. In an embodiment, a multiplexer allows the selection from a plurality of horizontal interconnect conductors to be routed to the plurality of vertical interconnect conductors.
- A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
- FIG. 1 is a diagram of a system incorporating a programmable logic integrated circuit;
- FIG. 2 is a block diagram of an exemplary architecture of a programmable logic integrated circuit of the present invention;
- FIG. 3 is a more detailed block diagram of the exemplary architecture of a programmable logic integrated circuit of the present invention;
- FIG. 4 is a block diagram of the interconnection between horizontal conductors and logic inputs to logic elements according to the present invention;
- FIG. 5 is a block diagram of the interconnection from vertical interconnect conductors to horizontal interconnect conductors according to the present invention;
- FIG. 6 is a block diagram of the interconnection from horizontal interconnect conductors to vertical interconnect conductors according to the present invention;
- FIG. 7 is a block diagram of clock routing scheme that may be implemented in a programmable logic integrated circuit of the present invention;
- FIG. 8 is a logic diagram of a TTL buffer for the clock routing scheme of FIG. 7; and
- FIG. 9 is a logic element driver circuit for driving a fast output from a logic element.
- FIG. 1 illustrates a typical environment in which an integrated circuit having been designed according to the principles of the present invention may be embodied. A
digital system 100 has aprocessing unit 101 that is coupled with amemory 105 and an input/output device 111. A personal computer is an example ofdigital system 100; however, a wide variety of electronic and consumer products will find beneficial use from the present invention. For example, the present invention will find application in telecommunications, switches, networks, and many other areas of technology. -
Digital system 100 contains one or more programmable logic integratedcircuits 121 of the type described in the present invention. Programmable logic integratedcircuit 121 may be, for example, a programmable logic device (sometimes referred to as PALs, PLAs, FPLAs, PLDs, EPLDs, CPLDS, EEPLDs, LCAs, or FPGAs.) Programmable logic devices are described for example, in U.S. Pat. No. 4,617,479, incorporated herein by reference for all purposes. Such devices are currently represented by, for example, Altera's FLEX® series of PLDs and are described, for example, in the Altera Data Book, January 1998, which is incorporated herein in its entirety by reference for all purposes. In FIG. 1, programmable logic integratedcircuit 121 is shown as a part ofprocessing unit 101, but,memory 105 or input/output device 111 may also advantageously contain programmable logic integratedcircuit 121. - FIG. 2 is a simplified block diagram of the overall internal architecture and organization of an exemplary programmable logic integrated
circuit 121. Many details of the architecture, organization, and circuit design are not necessary for an understanding of the present invention and such details are not shown. The exemplary PLD of FIG. 2 shows an array of logic array blocks (LABs) 200 interconnected by a global interconnect includinghorizontal conductors 210 andvertical conductors 220. EachLAB 200 is a physically grouped set of logical resources includinglogic elements 230. -
Logic elements 230 within aLAB 200 can be programmably coupled to each other and sometimes tologic elements 230 in anadjacent LAB 200 by means of alocal interconnect 240. Details ofLAB 200,logic elements 230, andlocal interconnect 240 may also be found in the Altera Data Book, January 1998, previously incorporated by reference. Other designs may also be preferentially used. Horizontal andvertical conductors output elements 250 for routing signals from programmable logic integratedcircuit 121. - FIG. 3 shows a more detailed block diagram of two
LABs 200 and the interconnections betweenhorizontal conductors 210,vertical conductors 220,local interconnects 240, andLABS 200. EachLAB 200 is coupled to thelocal interconnect 240 on its left and the local interconnect to its right in the matrix. Other architectures may also be used without departing from the spirit and scope of the present invention. - FIG. 4 shows a block diagram of the programmable connections between
horizontal conductors 210 and the logic inputs tologic elements 230. As mentioned above,horizontal conductors 210 are a part of a global interconnection resource. They may extend acrossseveral LABs 200, and possibly across the entirety ofPLD 121.Horizontal conductors 210 are coupled to the logic inputs oflogic elements 230 throughlocal interconnect 240. Although only one logic input of onelogical element 230 is depicted in FIG. 4, it will be recognized that the structure may be substantially replicated many times to accommodate all of the logic inputs for the logic elements inLAB 200. - One or more of
horizontal conductors 210 are selectively coupled to asignal regeneration circuit 310. In the specific embodiment, amultiplexer 318 is provided to programmably select from among a plurality ofhorizontal conductors 210 for connecting one of them to signalregeneration circuit 310.Multiplexer 318 may be a plurality oftransistors 320 connected in parallel with the source of each being coupled to differing ones ofhorizontal conductors 210 and the drains being commonly coupled to an input ofsignal regeneration circuit 310. Aprogramming element 322 is coupled to the gates of each oftransistors 310 to allow one of the paths to be selected. -
Programming element 322 and other programming elements described herein may be a memory cell. For example, in the specific embodiment,programming element 322 is an SRAM cell. - Although any size multiplexer may be used, in the
specific embodiment multiplexer 318 is a 16-1 multiplexer. This arrangement gives the user flexibility in selecting any one of 16 differenthorizontal conductors 210 for routing to a particular line oflocal interconnect 240. -
Signal regeneration circuit 310 may be comprised of a pair of cross-coupled inverting buffers 326 and 328. Atransistor 329 may also be provided selectively coupling the input ofsignal regeneration circuit 310 to GROUND. A reset signal is coupled with the gate oftransistor 329. This provides a method of initializing the state ofregeneration circuit 310 to a known state at the time of resetting programmable logic integratedcircuit 121. -
Signal regeneration circuit 310 serves several functions that is advantageous to the present invention. For example, it isolateslocal interconnect 240 from the capacitance onhorizontal conductors 210. Thus, a signal onlocal interconnect 240 can switch polarity at a faster rate than it would otherwise be able to switch. Further, signalregeneration circuit 310 boosts the signal also allowing it to switch at a faster rate. - Multiplexer318 and signal
regeneration circuit 310 may be replicated a number of times. The output of eachsignal regeneration circuit 310 is coupled to a different line oflocal interconnect 240. In the specific embodiment, 22 instances ofmultiplexer 318 and signalregeneration circuit 310 are provided.Local interconnect 240 also has 10 lines that come from the outputs of thecorresponding LAB 200 making a total of 32 lines in eachlocal interconnect 240. In the specific embodiment, half of the 10 lines come from theLAB 200 to the right oflocal interconnect 240, and half come from theLAB 200 to the left oflocal interconnect 240. - The individual lines in
local interconnect 240 may be programmably coupled to the logic inputs oflogic elements 230 by a logicinput selector circuit 330. Logicinput selector circuit 330 provides amultiplexer 340, the output of which is coupled to one of the logic inputs oflogic element 230.Multiplexer 340 may comprise a number oftransistors 345 coupled in parallel, with the gates oftransistors 345 being coupled to programmable elements 348. Each of the inputs to multiplexer 340 are coupled to traces that extend perpendicularly tolocal interconnect 240.Transistors 345 are coupled between the individual lines oflocal interconnect 240 and the traces. -
Logic input selector 330 provides a logic input to one oflogic elements 230. In the specific embodiment, eachlogic element 230 has four inputs, and eachLAB 200 has 10logic elements 230. Thus, the circuitry shown in FIG. 4 is replicated 40 times, once for each logic input to the LAB. In the specific embodiment, two of the inputs to eachlogic element 230 may be coupled to the local interconnect fromLAB 240 to its left, and the other two may be coupled to the local interconnect fromLAB 240 to its right. - FIG. 5 shows a
column interconnect 500.Column interconnect 500 provides a path for couplinghorizontal conductors 210 orlocal interconnect 240, tovertical conductors 220. One ofhorizontal conductor 210 is coupled to an input of amultiplexer 510 through atransistor 515. The gate oftransistor 515 is coupled to aprogrammable element 518. One of thelocal interconnect lines 240 is coupled to another input ofmultiplexer 510. The selection input tomultiplexer 510 is coupled to a programmable element (not shown) for selecting which input is to be routed to the output ofmultiplexer 510. - The specific embodiment includes inverting
buffers 530 and 532 on the inputs ofmultiplexer 510, and an invertingbuffer 534 on the output of multiplexer 234. The output of invertingbuffer 534 is selectively coupled to one of thevertical conductors 220 through atransistor 540 with aprogramming element 542 coupled to its gate. In some embodiments, the output may be coupled to a plurality ofvertical conductors 220. - A pull-up
transistor 560 is coupled betweentransistor 515 and inverting buffer 530. Pull-uptransistor 560 is a p-type device and has a gate coupled to the output of inverting buffer 530. This boosts the signal as it passes throughcolumn interconnect 500. A pull-down transistor 565 is also provided betweentransistor 515 and inverting buffer 530. ANAND gate 570 is coupled to the gate of pull-down transistor 565.NAND gate 570 is coupled toprogramming element 518 and to the inverse of a reset signal. Thus, when the horizontal conductor path throughtransistor 515 is not selected, the input to inverting buffer is pulled to GROUND. It is also pulled to GROUND when the reset signal is asserted. - FIG. 6 shows a
row interconnect circuit 600.Row interconnect circuit 600 provides a path for one or morevertical conductors 220 to one or morehorizontal conductors 210. A path is also provided to route the output from one of thelogic elements 230 to one or morehorizontal conductors 210. - In the specific embodiment,
row interconnect circuit 600 is coupled to two of thevertical conductors 220. Amultiplexer 610 selects between the two vertical conductors.Multiplexer 610 is programmable and may be constructed in a manner similar to the multiplexers described above usingtransistors 612 and 614, each of which has its gate coupled toprogrammable elements - The output of
multiplexer 610 is coupled through an invertingbuffer 620 to anothermultiplexer 624.Multiplexer 620 is also coupled at its other input to the output of alogic element 230 through an inverting buffer 626. The output ofmultiplexer 624 is coupled through an invertingbuffer 628 to all of thehorizontal conductors 210 through transistors 630-636, each of which has a programmable elements 640-646 coupled to its gate. In some embodiments, the output may only be coupled to a subset ofhorizontal conductors 210. -
Row interconnect circuit 600 also has a pull-uptransistor 650 that is coupled the output ofmultiplexer 610 to boost the signal fromvertical conductor 210. It also includes a pull-down transistor coupled to the output ofmultiplexer 610. ANAND gate 660 and an OR gate 665 are coupled to the gate to turn pull-down transistor 655 on when neitherprogrammable elements - FIG. 7 depicts a clocking scheme that may be implemented in programmable logic integrated
circuit 121 of the present invention. A clock is typically used throughout the programmable logic integratedcircuit 121 to allow synchronous operation. It is desirable in an integrated circuit to reduce the amount of clock skew. A large clock skew will degrade the overall system performance, since the device can only operate as fast as its slowest path. - In the specific embodiment, two clock skew components can be identified. Inter-row clock skew is the amount of skew between the horizontal rows, while inter-column clock skew is the amount of skew between the elements in a column for each row.
- Referring to FIG. 7, a
TTL buffer 710 is placed along each row ofintegrated circuit 121. EachTTL buffer 710 is coupled to aclock pin 720. A typical integrated circuit will have a plurality of clock pins 720. By this arrangement, each row has a similar clock skew. Thus, the clock skew is determined by the inter-column clock skew alone. of further advantage, sinceTTL buffer 710 is repeated for each row, the clock signal is driven to each row by the external driver, which is typically much larger thanTTL buffer 710. Clock pins 720 are preferably centered along the left and right edges ofintegrated circuit 121 to further balance the clocking skews. - FIG. 8 shows a more detailed circuit diagram of
TTL buffer 710.TTL buffer 710 includes a 4:1multiplexer 810.Multiplexer 810 includes three control inputs (MODE 820,NRFAST 822, andRLEONE1 824.) Control inputs 820-824 determine which of the four inputlines TTL buffer 710 will drive. In the specific embodiment,TTL buffer 710 is coupled to four different inputs throughinputs Clock input 830 is coupled to the clock pin.LE inputs logic element 230, andJTAG input 836 is coupled to a JTAG input. The decoder table in FIG. 8 shows how each line is selected by the values on control inputs 820-824. The inverse of a reset signal is provided on areset input 840 which is coupled to aNAND gate 842. This drives the output to GROUND when the reset signal is activated. -
Input 830 is coupled to the output through two invertingbuffers multiplexer 810 is coupled to an output ofTTL buffer 710 through abuffer 860 which drives the fast signal to the rows. - The present invention also provides
LE driver circuitry 900 to allow an asynchronous clock or other fast signal to be driven fromlogic elements 230. FIG. 9 shows a circuit diagram ofLE driver circuitry 900 for driving the asynchronous clock fromlogic elements 230. AnLE driver output 910 is coupled to either ofLE inputs TTL buffer 710. Invertingbuffers LE driver output 910. - A
programmable inversion circuit 930 is also provided to allow the user to selectively invert the asynchronous clock signal. When a signal onPIIN input 932 is asserted, the signal on anLE input 938 is inverted before being driven out onLE driver output 910. Otherwise, the signal is not inverted. - The foregoing description of preferred embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
Claims (14)
1. A programmable integrated circuit comprising:
a plurality of vertical interconnect conductors;
a plurality of horizontal interconnect conductors; and
a buffer circuit to programmably couple one of the plurality of vertical interconnect conductors to any one of the plurality of horizontal interconnect conductors.
2. The programmable integrated circuit of wherein the buffer circuit further comprises:
claim 1
a first transistor coupled between a first conductor in the plurality of vertical interconnect conductors and a first node wherein a control electrode of the first transistor is coupled to a first memory bit;
a second transistor coupled between a second conductor in the plurality of vertical interconnect conductors and the first node wherein a control electrode of the second transistor is coupled to a second memory bit;
a first buffer comprising an input coupled to the first node;
a multiplexer coupled to an output of the first buffer; and
a second buffer coupled to an output of the multiplexer.
3. The programmable integrated circuit of wherein the buffer circuit further comprises:
claim 1
a plurality of transistors coupled to an output line of the buffer circuit, and each of the plurality of transistors coupled to a different one of the plurality of horizontal interconnect conductors.
4. The programmable integrated circuit of further comprising a plurality of memory cells, each coupled to a different one of the plurality of transistors.
claim 3
5. The programmable integrated circuit of wherein the buffer circuit drives a signal from one of the plurality of vertical interconnect conductors to two of the plurality of horizontal interconnect conductors.
claim 1
6. The programmable integrated circuit of wherein the buffer circuit comprises:
claim 1
a first transistor to selectively couple a first conductor of the plurality of vertical interconnect conductors to a first output line;
a second transistor to selectively couple a second conductor of the plurality of vertical interconnect conductors to the first output line;
a third transistor to hold the output line at a known voltage level when the first and second conductors of the plurality of vertical interconnect conductors are not coupled to the output line.
7. The programmable integrated circuit of wherein the buffer circuit may programmably couple an output of a logic element to any one of the plurality of horizontal interconnect conductors.
claim 1
8. The programmable integrated circuit of wherein the memory cells are SRAM cells.
claim 4
9. A programmable integrated circuit comprising:
a plurality of vertical interconnect conductors;
a plurality of horizontal interconnect conductors; and
a buffer circuit to drive one of the plurality of horizontal interconnect conductors to any one of the plurality of vertical interconnect conductors.
10. The programmable integrated circuit of wherein the buffer circuit may drive more than one of the plurality of vertical interconnect conductors.
claim 9
11. A programmable integrated circuit of wherein the buffer circuit may drive an output from a logic element to the plurality of vertical interconnect conductors.
claim 9
12. A programmable integrated circuit of wherein the buffer circuit comprises:
claim 9
a first transistor coupled between one of the plurality of horizontal interconnect and a first node, wherein a control electrode of the first transistor is coupled to a memory cell;
an inverter coupled to the first node and providing an output at a second node;
a second transistor coupled between a first supply and the first node, wherein a control electrode of the second transistor is coupled to the second node; and
a multiplexer comprising a first input coupled to the second node, a second input coupled to an output of a logic element.
13. A programmable integrated circuit comprising:
a plurality of horizontal interconnect conductors;
a multiplexer to selectively couple one of the plurality of horizontal interconnect conductors to a local conductor of a logic array block; and
a signal regeneration circuit coupled between the multiplexer and the local conductor to buffer a signal from the multiplexer.
14. A programmable integrated circuit of wherein the signal regeneration circuit comprises:
claim 13
a first inverter coupled between the multiplexer and the local conductor; and
a second inverter coupled between the local conductor and the multiplexer.
Priority Applications (1)
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US09/738,403 US6384629B2 (en) | 1997-06-10 | 2000-12-15 | High-speed programmable interconnect |
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US09/094,356 US6262595B1 (en) | 1997-06-10 | 1998-06-09 | High-speed programmable interconnect |
US09/738,403 US6384629B2 (en) | 1997-06-10 | 2000-12-15 | High-speed programmable interconnect |
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US7129744B2 (en) * | 2003-10-23 | 2006-10-31 | Viciciv Technology | Programmable interconnect structures |
US6816562B2 (en) * | 2003-01-07 | 2004-11-09 | Mathstar, Inc. | Silicon object array with unidirectional segmented bus architecture |
US7867511B2 (en) * | 2004-01-23 | 2011-01-11 | Travanti Pharma Inc. | Abuse potential reduction in abusable substance dosage form |
US8481357B2 (en) * | 2008-03-08 | 2013-07-09 | Crystal Solar Incorporated | Thin film solar cell with ceramic handling layer |
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US4617479B1 (en) | 1984-05-03 | 1993-09-21 | Altera Semiconductor Corp. | Programmable logic array device using eprom technology |
US4609986A (en) | 1984-06-14 | 1986-09-02 | Altera Corporation | Programmable logic array device using EPROM technology |
US4713557A (en) | 1984-09-26 | 1987-12-15 | Xilinx, Inc. | Bidirectional buffer amplifier |
US4642487A (en) | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
US5241224A (en) | 1991-04-25 | 1993-08-31 | Altera Corporation | High-density erasable programmable logic device architecture using multiplexer interconnections |
US5237218A (en) | 1991-05-03 | 1993-08-17 | Lattice Semiconductor Corporation | Structure and method for multiplexing pins for in-system programming |
US5260611A (en) | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US5384497A (en) * | 1992-11-04 | 1995-01-24 | At&T Corp. | Low-skew signal routing in a programmable array |
US5455525A (en) * | 1993-12-06 | 1995-10-03 | Intelligent Logic Systems, Inc. | Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array |
US5742179A (en) * | 1994-01-27 | 1998-04-21 | Dyna Logic Corporation | High speed programmable logic architecture |
US5497108A (en) * | 1994-12-08 | 1996-03-05 | Dynalogic Corporation | BICMOS repeater circuit for a programmable logic device |
US5710550A (en) * | 1995-08-17 | 1998-01-20 | I-Cube, Inc. | Apparatus for programmable signal switching |
US5583452A (en) | 1995-10-26 | 1996-12-10 | Xilinx, Inc. | Tri-directional buffer |
JP3486725B2 (en) * | 1995-11-28 | 2004-01-13 | 株式会社ルネサステクノロジ | Variable logic integrated circuit |
US5799176A (en) * | 1995-12-26 | 1998-08-25 | Cypress Semiconductor Corp. | Method and apparatus for providing clock signals to macrocells of logic devices |
US5894565A (en) * | 1996-05-20 | 1999-04-13 | Atmel Corporation | Field programmable gate array with distributed RAM and increased cell utilization |
US5880598A (en) * | 1997-01-10 | 1999-03-09 | Xilinx, Inc. | Tile-based modular routing resources for high density programmable logic device |
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1998
- 1998-06-09 US US09/094,356 patent/US6262595B1/en not_active Expired - Lifetime
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2000
- 2000-12-15 US US09/738,403 patent/US6384629B2/en not_active Expired - Lifetime
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US6262595B1 (en) | 2001-07-17 |
US6384629B2 (en) | 2002-05-07 |
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