US20010014034A1 - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory device Download PDFInfo
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- US20010014034A1 US20010014034A1 US09/781,829 US78182901A US2001014034A1 US 20010014034 A1 US20010014034 A1 US 20010014034A1 US 78182901 A US78182901 A US 78182901A US 2001014034 A1 US2001014034 A1 US 2001014034A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
Definitions
- the present invention relates to a semiconductor memory device, in particular to nonvolatile semiconductor memory device having an automatic multi-byte write function.
- memory cell region is divided into a plurality of sectors S 1 , S 2 , . . . , Sn ⁇ 1 and Sn, a Y selector 2 is provided for the memory cell array 1 of each of the sectors S 1 , S 2 , . . . , Sn ⁇ 1 and Sn, and a logic circuit 3 for selecting each Y selector 2 is incorporated.
- a sense amplifier 4 and a write circuit 5 are connected in parallel to a bit line 1 a of each memory cell array 1 , and data are input to and output from the sense amplifier 4 and the write circuit 5 that are connected in parallel via an I/O buffer 6 .
- Numerals 7 are a plurality of I/O terminals provided corresponding to the I/O buffers 6 .
- FIG. 9 is shown a nonvolatile semiconductor memory device having the function of an automatic write operation according to related art.
- the nonvolatile semiconductor memory device according to related art shown in FIG. 9 is formed by adding a data control circuit 9 and a status circuit 10 to the circuit shown in FIG. 8.
- the data control circuit 9 holds write data input from the I/O buffer 6 , and outputs write data to the write circuit 5 at the time of writing. At write inspection, the data control circuit 9 compares data read from the sense amplifier 4 with the write data stored in it, and outputs data (data about the result of the write check for the memory cell array 1 ) about whether or not they match with each other (write pass) to the status circuit 10 .
- the status circuit 10 with the write inspection decision data as an input, outputs pass/fail decision data that indicate whether or not successful write to the memory cell array 1 was obtained, to the I/O terminal 7 and an operation control circuit 11 .
- the operation control circuit 11 completes the write operation to the memory cell array 1 when the write inspection decision data for the memory cell array 1 is a pass, and controls so as to repeat a rewrite and an inspection on the rewrite to the memory cell array 1 when the decision data is a fail.
- the data control circuit 9 reads the write inspection data for the memory cell array 1 through the sense amplifier 4 , compares the write inspection data with the write data that are stored in the data control circuit 9 , and outputs data (write inspection decision data for the memory cell array 1 ) as to whether or not they match (write pass) to the status circuit 10 .
- the status circuit 10 with the write inspection decision data for the memory cell array 1 output from the data control circuit 9 as an input, takes the logical product of the pass/fail decision data which indicate whether or not all the memory cell arrays 1 were successfully written, and when the write to all the memory cell arrays 1 is normally completed, outputs a signal to that effect to the I/O terminal 7 .
- the operation control circuit 11 completes the write operation to the memory cell array 1 , resets all the operations, and sets the relevant components to a standby state for the next operation.
- the operation control circuit 11 controls the memory cell array 1 to be subjected to a rewrite of data and an inspection of the rewriting.
- the pass/fail decision data are output by being taken the logical product at a single I/O terminal 7 . Accordingly, when a defective product is to be saved by means of redundancy, it becomes necessary to verify again as to the write operation to which memory cell array 1 was decided to be in failure.
- the nonvolatile semiconductor memory device in order to achieve the above object, in a nonvolatile semiconductor memory device having memory cell region divided into a plurality of sectors, the nonvolatile semiconductor memory device according to the present invention makes it possible to write simultaneously write data to the memory cell arrays divided into the plurality of sectors, and output the inspection result of the write to the outside by scanning the address signals.
- the nonvolatile semiconductor memory device includes, write means for simultaneously writing write data to the memory cell arrays divided into the plurality of sectors, write inspection means for conducting write inspection as to match/mismatch between the data written to the memory cell array and the write data to be written to the memory cell array, and outputting pass/fail decision data indicating whether or not the memory cell array was successfully written, hold means for holding the pass/fail decision data for the memory cell array, and output means for outputting to the outside the pass/fail decision data arranged to correspond to each memory cell array in response to the externally input address signals.
- FIG. 1 is a circuit diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention
- FIG. 2 is a circuit diagram of a sector MS 1 of the device shown in FIG. 1;
- FIG. 3 is a circuit diagram of a controller shown in FIG. 1;
- FIG. 4 is a timing chart of the device shown in FIG. 1;
- FIG. 5 is a circuit diagram showing the nonvolatile semiconductor memory device according to a second embodiment of the present invention.
- FIG. 6 is a circuit diagram of a sector MS 1 of the device shown in FIG. 5;
- FIG. 7 is a circuit diagram of a data control circuit of the device shown in FIG. 5;
- FIG. 8 is a circuit diagram showing a nonvolatile semiconductor memory device according to related art.
- FIG. 9 is another circuit diagram showing a nonvolatile semiconductor memory device according to the related art.
- FIG. 1 is a circuit diagram showing the nonvolatile semiconductor memory device according to a first embodiment of the present invention.
- the nonvolatile semiconductor memory device has memory sectors MS 1 to MS 4 .
- XY decoders 11 a , 11 b control the memory sectors.
- the decoders 11 a , 11 b receive address signals A 0 to An ⁇ 2 and select one word line among word lines WL 1 to WLm and one Y select line among Y select lines Y 1 to Yn to select one memory cell of each memory cell array 1 a to 1 h .
- a controller 3 is responsive to address signals An ⁇ 1 , An to activate one signal among sector enable signals S 0 to S 3 .
- Each of the memory sectors MS 1 to MS 4 is activated by the respective activated sector enable signals.
- Each of memory sectors MS 1 to MS 3 are connected to bit lines LB 1 to LB 4 .
- Each of memory sectors MS 2 to MS 4 are connected to bit lines LB 5 to LB 8 .
- the bit lines LB 1 , LB 5 are connected to an output line GO 1 .
- the bit lines LB 2 , LB 6 are connected to an input line GI 1 .
- the bit lines LB 3 , LB 7 are connected to an output line GO 2 .
- the bit lines LB 4 , LB 8 are connected to an input line GI 2 .
- the input lines I 1 , I 2 are connected to write circuits 5 a , 5 b , respectively.
- An I/O buffer 6 a is connected to an input of the write circuit 5 a and the output line GO 1 .
- An I/O buffer 6 b is connected to an input of the write circuit 5 b and the output line GO 2 .
- the buffers 6 a and 6 b are connected to terminals 7 a , 7 b , respectively, and outputs their outputs into an operation control circuit 11 . Since the structure of each memory sector MS 1 to MS 4 is substantially identical to each other except sector enable signals receiving at the sectors, respectively, we explain the memory sector MS 1 mainly. The explanation of the sectors MS 2 to MS 4 is omitted.
- FIG. 2 is a circuit diagram of the sector MS 1 shown in FIG. 1.
- the sector MS 1 includes memory cell arrays 1 a , 1 b , Y-selectors 2 a , 2 b , sense amplifiers 4 a , 4 b , data control circuits 9 a , 9 b , and source voltage supply circuits 18 a , 18 b .
- Each of memory cell arrays 1 a , 1 b has non-volatile memory cells M 11 to Mmn (m,n: integer) arranged in a matrix. Memory cells on a line in a row direction, for example, cells M 11 to M 1 n are connected to a single word line, for example, WL 1 .
- Bit lines BL 1 to BLn are connected to the respective memory cells.
- the drains of memory cells M 11 to Mm 1 are connected to bit line BL 1 .
- the sources of memory cells M 11 to Mmn are connected to the source voltage supply circuit 18 a.
- the Y-selectors 2 a , 2 b each is connected to Y-select lines Y 1 to Yn and receives the sector enable signal S 0 .
- the Y-selector lines are connected to gates of the respective select transistors Yt 1 to Ytn.
- the sector enable signal S 0 is input to a gate of transistor 19 a , 19 b .
- the select transistor Yt 1 to Ytn each has a current path between the respective bit line and the transistor 19 a .
- the data control circuits 9 a , 9 b each has exclusive circuits 15 a , 15 b , latch circuits 16 a , 16 b , and gate circuits 17 a , 17 b .
- the gate circuits 17 a , 17 b each is connected to bit lines LB 2 , LB 4 each.
- the bit lines LB 2 , LB 4 are connected to the transistors 19 a , 19 b , respectively.
- the gate circuits 17 a , 17 b are connected to the latch circuits 16 a , 16 b , respectively, so that the latch circuits 16 a , 16 b latches data on the bit lines LB 2 , LB 4 when control signal C 1 , C 2 are activated, respectively.
- the latched data in the latch circuits 16 a , 16 b and the output from the sense amplifier 4 a , 4 b are input to exclusive circuits 15 a , 15 b , respectively.
- the output of the exclusive circuits 15 a , 15 b are connected to the bit lines LB 1 , LB 3 , respectively.
- the exclusive circuits 15 a , 15 b each can output in three states that are logic high and low levels and floating level. That is, when the signal S 0 is a low level, the exclusive circuits 15 a , 15 b sets their output in a floating state. When the signal S 0 is a high level, the exclusive circuits outputs logic high or logic low level as coincident or in-coincident result.
- Exclusive circuits 15 a , 15 b and Y-select transistors 19 a , 19 b in the sectors MS 2 to MS 4 receives the sector enable signals S 1 to S 3 , respectively in place of the signal S 0 .
- FIG. 3 is a circuit diagram of the controller 3 shown in FIG. 1.
- the controller 3 has inverters 20 , 21 and NAND circuits 22 to 39 .
- Multi Program signal has a logic high level
- the signals S 0 to S 3 has logic high levels regardless of levels of address signals An and An ⁇ 1 .
- address signals An and An ⁇ 1 are (L,L), (L,H), (H,L), and (H,H)
- the signals S 0 , S 1 , S 2 , and S 3 become (H,L,L,L), (L,H,L,L), (L,L,H,L), and (L,L,L,H), respectively.
- “L” means “a logic low level”
- “H” means “a logic high level”.
- Sector enable signal has a logic high level
- the respective sector is activated to access the selected memory cells in it with I/O buffers.
- the nonvolatile semiconductor memory device uses the write circuit 5 a and 5 b in common to memory cell arrays 1 a , 1 c , 1 e and 1 g and 1 b , 1 d , 1 f and 1 h , respectively and writes write data from the write circuits 5 a and 5 b simultaneously to all memory cell arrays 1 a to 1 h.
- the data control circuit 9 inputs write information for the memory cell array 1 via a sense amplifier 4 , conducts write inspection as to match/mismatch with the write data to be written to the memory cell arrays 1 based on the received information, outputs the pass/fail decision data for the memory cell arrays 1 .
- the memory cell region divided into a plurality of sectors are divided into two systems and a write circuit 5 is provided for each system, and write data are written simultaneously to all memory cell arrays 1 via a selected word line with the system as a unit.
- bit lines are sequentially activated by appropriately selecting time sequentially the Y selectors 2 .
- the memory device is controlled so as to input write data from the write circuit 5 simultaneously to all memory cell arrays with the system as a unit, by appropriately selecting the word lines and the bit lines time sequentially from the operation control circuit 11 .
- the device externally outputs the pass/fail decision data for all memory cell arrays in sequence, in response to externally input address signals, by time sequentially selecting the Y selectors 2 based on the control from the operation control circuit 11 .
- the memory device will be brought to test mode based on a command from the operation control circuit 11 .
- the write voltages for the memory cells are set by the write circuits 5 a , 5 b and the source voltage supply circuits 18 a , 18 b .
- the control signals C 1 , C 2 of a pulse signal are inputted to the transistors 17 a , 17 b and the write data are held by the latches 16 a , 16 b in the data control circuits 9 a to 9 h as shown at period between T 1 and T 2 in FIG. 4.
- the XY decoders 11 a , 11 b sustain the address signals A 0 to An ⁇ 2 to keep selecting the word line WL 1 and the select line Y 1 . All the memory cells M 11 of memory cell arrays 1 a to 1 h are selected to be read out. Multi Program signal changes low level to high level.
- the only signal So is activated and Data stored in the selected memory cells M 11 in memory sector MS 1 are read out and transfers into the data control circuits 9 a , 9 b through the transistors 19 a , 19 b and sense amplifiers 4 a , 4 b .
- the exclusive circuits 15 a and 15 b compare the read out data from the memory cells M 11 and the latched data in the latch 16 a , 16 b , respectively and outputs the match/mismatch result to the bit lines LB 1 , LB 3 .
- the exclusive circuits in the data control circuits 9 c to 9 h set their outputs in floating level.
- the match/mismatch result data are transferred from the data control circuits 9 a , 9 b to the operation control circuit 11 via the I/O buffers 6 a , 6 b and the output lines GO 1 , GO 2 .
- T in FIG. 4 means data match
- F in FIG. 4 means data mismatch.
- the match/mismatch result data are transferred from the control circuits of sectors MS 2 to MS 4 into the operation control circuit 11 via the I/O buffers 6 a , 6 b , by changing the address n ⁇ 1, n as shown in FIG. 4.
- the operation control circuit 11 detects that the write to all memory cell arrays 1 do not complete normally, the operation control circuit 11 conducts to write the write data to the memory cell arrays failed until the write for all memory cell arrays 1 a to 1 h is completed normally.
- the operation control circuit 11 When write for the memory cell arrays 1 a to 1 h is completed normally, the operation control circuit 11 outputs the sector address signals S 0 to S 3 into the logic circuit 3 to select sequentially sectors MS 1 to MS 4 .
- the pass/fail decision data for the memory cell array 1 a to 1 h held in the data control circuits 9 a to 9 h are outputted to the outside from the I/O terminal 7 .
- the timing at which the operation control circuit 11 reads the pass/fail decision data for memory cell arrays is set at the time when the write to the memory cell arrays 1 is normally completed, but it may be set to be read in the order in which write to the memory cell array 1 is completed normally.
- the decision result of write inspection for the memory cell arrays is output to the outside by scanning the address signals. Accordingly, it is possible to suppress the increase in the write time due to the increase in the number of parallel writing caused by multiple write, or more specifically, due to the increase in the installation number of memory cell arrays divided into a plurality of sectors. Moreover, analogous to the automatic write, it is possible to omit the time for write verify by outputting the pass/fail decision data for the memory cell arrays to the outside in time sequential arrangement corresponding to the memory cell arrays. Furthermore, this method allows automatic multiple write for plural sectors, and has an advantage of reducing the test time for a flash memory or the like.
- FIG. 5 is a circuit diagram of the nonvolatile semiconductor memory device according to a second embodiment of the present invention.
- the nonvolatile semiconductor memory device shown in FIG. 5 is provided with write circuits 5 a to 5 h , sense amplifiers 4 a to 4 h , and data control circuits 9 a to 9 h for each of memory cell arrays 1 a to 1 h .
- the data control circuits has functions of the write inspection means and the hold means. Write data from each of write circuits 5 a to 5 h are written simultaneously to all memory cell arrays 1 a to 1 h.
- the data control circuits 9 a to 9 h each has latch means to hold the pass/fail decision data for the memory cell arrays 1 a to 1 h until the completion of the test mode.
- this memory device is constructed so as to output to the outside the pass/fail decision data for the memory cell arrays held in the data control circuits 9 a to 9 h as time sequential data arranged corresponding to the memory cell arrays 1 a to 1 h each by sequentially changing the address signals for respective sectors S 1 to S 2 .
- the input/output bus line GL 0 is connected between the I/O buffer 6 a and the data control circuits 30 a , 30 c , 30 e and 30 g .
- the input/output bus line GL 1 is connected between the I/O buffer 6 b and the data control circuits 30 b , 30 d , 30 f and 30 h .
- the write circuits 5 a to 5 h are connected between the data control circuits 30 a to 30 h and the Y-selectors 2 a to 2 h .
- the Y-selectors 2 a to 2 h each is connected to the respective select lines S 0 to S 3 .
- FIG. 6 illustrates a circuit diagram of Y-selectors 2 a and 2 b shown in FIG. 5.
- the selection movement to select sectors MS 1 to MS 4 in sequence is substantially the same. That is, responding to the changing the addresses An, An ⁇ 1 , the sectors MS 1 to MS 4 are activated in sequence.
- the explanation is omitted for the Y-selectors 2 c to 2 h because those structures are substantially same to those of Y-selectors 2 a to 2 b , except that And-gates 40 a , 40 b of sectors MS 2 , MS 3 and MS 4 receive S 1 and S 2 , S 0 and S 3 , and S 1 and S 3 in place of S 0 and S 2 .
- FIG. 7 illustrates a circuit diagram of data control circuit 30 a shown in FIG. 5.
- the data control circuit 30 a has a first transistor coupled to a line LL 0 and receiving a sector select signals S 0 and S 2 .
- a second transistor is coupled between a latch circuit 16 a and the first transistor and receives a write signal. During a write operation, the write signal becomes a high level so that the second transistor turns ON.
- a third transistor is coupled between the latch circuit 16 a and the write circuit 5 a and receives a pulse signal C 1 . When a write data is written into a selected memory cell, the pulse signal C 1 is generated to transfer the write data into the write circuit 5 a .
- An exclusive circuit 15 a has input nodes coupled to the latch circuit 16 a and the sense amplifier 4 a .
- a fourth transistor is coupled between the output node of the exclusive circuit 15 a and the first transistor and receives an inverted signal of the write signal. The fourth transistor turns OFF during the write operation and ON during a read operation. During the read operation, the first transistor turns OFF.
- a second latch circuit 50 a is coupled to the connecting point of the first and fourth transistors to latch the match/mismatch result data outputted from the exclusive circuit 15 a .
- the explanation is omitted for the data control circuits 30 b to 30 h because those structures are substantially same to that of the data control circuit 30 a , except that the data control circuits 30 b to 30 h receive respective signals among S 0 , S 1 , S 2 and S 3 .
- the structures of memory cell arrays 1 a to 1 h according to the second embodiment is substantially the same with those of memory cell arrays 1 a to 1 h according to the first embodiment. Moreover, the XY decoders 11 a , 11 b shown in FIG. 1 are attached to the memory device shown in FIG. 5.
- the memory device is brought to the test mode based on a command from the operation control circuit 11 .
- the word line and the bit line are selected based on a command from the operation control circuit 11 .
- write data are input from the external terminals 7 a , 7 b .
- the input data are written simultaneously to the corresponding memory cells of memory cell arrays 1 a to 1 h through respective write circuits.
- the write data are held in the latch circuits 16 a each of the data control circuits 30 a to 30 h.
- the data control circuits 30 a to 30 h receive the data read out from the memory cell arrays 1 a to 1 h via the sense amplifiers 4 a to 4 h .
- Each of the circuits 30 a to 30 h conducts match/mismatch comparison between the data read out from the memory cells and the write data in the latch circuits 16 a and outputs pass/fail decision data for the memory cell arrays 1 a to 1 h .
- Each of the circuits 30 a holds the decision data in the latch circuit 50 a.
- the operation control circuit 11 repeats data write to the failed memory cell arrays and read of write inspection data for these memory cell arrays once again, and stops the series of write operation upon normal completion of write operation for all memory cell arrays 1 .
- the data control circuits 30 a to 30 h holds the pass/fail decision data for the memory cell arrays until the completion of the test mode.
- the operation control circuit 11 When the write to all the memory cell array is completed normally, the operation control circuit 11 outputs a sector address signal to the logic circuit 3 , and the logic circuit 3 selects sequentially a plurality of Y selectors to read the pass/fail decision data for all memory cell arrays held in the data control circuit, and outputs the decision data to the outside from the I/O terminals 7 a , 7 b as time sequential data.
- the timing at which the operation control circuit 11 reads the decision result of the write inspection for the memory cell arrays is set at the time when the write for all memory cell arrays is completed in normal fashion.
- the timing may be set in such a manner that it is read in the order normal write is completed for individual memory cell array.
- the nonvolatile semiconductor memory devices according to the present invention shown in FIG. 1 and FIG. 5 are arranged to be capable of writing simultaneously write data to memory cell arrays 1 that are divided into the plurality of sectors MS 1 , MS 2 , . . . , MSn ⁇ 1 and MSn, and outputting to the outside the result of the write inspection by scanning the address signals.
- the nonvolatile semiconductor memory devices according to the present invention are provided with write means 5 for simultaneously writing write data to the memory cell arrays 1 divided into the plurality of sectors MS 1 , MS 2 , . . . , MSn ⁇ 1 and MSn.
- write inspection means for conducting write inspection as to match/mismatch between the data written to the memory cell arrays 1 and the write data to be written to memory cell arrays 1 , and for outputting pass/fail decision data indicating whether or not the memory cell arrays 1 are successfully written
- hold means for holding the pass/fail decision data for the memory cell arrays 1
- output means 3 and 11 for outputting the pass/fail decision data, arranged corresponding to each memory cell array, to the outside in response to externally input address signals.
- a data control circuit 9 is employed as a circuit having both functions of the write inspection means and the hold means.
- the write means 5 and the hold means are provided for each memory cell array, uses the write means 5 in common to all memory cell arrays 1 , and write data from the write means 5 are written simultaneously to all memory cell arrays 1 .
- the write means 5 , the write inspection means and the hold means are provided for each memory cell array 1 , and write data from each write means 5 are written simultaneously to all memory cell arrays 1 by writing the write data to each individual memory cell array 1 .
- the hold means is so constructed as to hold the pass/fail decision data for the memory cell array 1 until the completion of the test mode.
- the output means 3 and 11 are constructed so as to output the pass/fail decision data held in the hold means to the outside for each memory cell array, by sequentially inputting the address signal for each sector MS 1 , MS 2 , . . . , MSn ⁇ 1 and MSn.
- the present invention has the write means 5 for writing write data simultaneously into the plurality of sectors MS 1 , MS 2 , . . . , MSn ⁇ 1 and MSn, the present invention has the write means 5 for writing write data simultaneously into the plurality of sectors MS 1 , MS 2 , . . .
- the write inspection means for conducting write inspection as to match/mismatch between the data written to the memory cell arrays 1 and the write data to be written to the memory cell arrays 1 , and outputting pass/fail decision data for the memory cell arrays 1
- the hold means for holding the pass/fail data for the memory cell arrays 1
- means 3 and 11 for outputting to the outside the pass/fail decision data for the memory cell arrays 1 in response to the externally input address signals.
- the nonvolatile semiconductor memory device may be configured, as shown in FIG. 1, so as to provide the write inspection means and the hold means for each memory cell array 1 , where the write means 5 is used in common to all memory cell arrays, and write data from the write means 5 are written simultaneously to all memory cell arrays 1 .
- it may be arranged, as shown in FIG. 5 of the nonvolatile semiconductor memory device according to this invention, so that the write means 5 , the write inspection means and the hold means are provided for each memory cell array 1 , and write data from each write means 5 are written simultaneously to all memory cell arrays 1 by writing the write data from each write means 5 to each memory cell array 1 . Accordingly, this invention may be applied corresponding to the configuration of the memory cells, and the versatility of the invention can be expanded.
- the hold means is arranged so as to hold the pass/fail decision data for the memory cell array 1 until the completion of the test mode, so that the system is capable of coping effectively with the situation even if an accident should happen in the midst of the operation.
- the output means 3 and 11 are configured so as to output to the outside the pass/fail decision data held in the hold means as arranged corresponding to the memory cell arrays 1 by sequentially inputting the address signals for each sector MS 1 , MS 2 , . . . , MSn ⁇ 1 and MSn. Accordingly, it is possible to output to the outside the pass/fail decision data as time series data for each memory cell array 1 , so that when a defective product is saved by means of redundancy, write operation to which memory cell array 1 was decided to be in failure can be determined quickly and accurately.
- the decision result of the write inspection for the memory cell arrays is output to the outside by scanning the address signals. Accordingly, the increase in the write time due to the increase in the number of parallel writes caused by the multiple write, and more specifically, due to the increase in the installation number of the memory cell region that is divided into a plurality of sectors, can be suppressed, and analogous to the case of the automatic write, the time for write verify can be omitted by outputting to the outside the pass/fail decision data for the memory cell arrays in time sequential fashion arranged corresponding to the memory cell arrays.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor memory device, in particular to nonvolatile semiconductor memory device having an automatic multi-byte write function.
- 2. Description of the Related Art
- In a nonvolatile semiconductor memory device shown in FIG. 8, memory cell region is divided into a plurality of sectors S1, S2, . . . , Sn−1 and Sn, a
Y selector 2 is provided for thememory cell array 1 of each of the sectors S1, S2, . . . , Sn−1 and Sn, and alogic circuit 3 for selecting eachY selector 2 is incorporated. - A
sense amplifier 4 and awrite circuit 5 are connected in parallel to abit line 1 a of eachmemory cell array 1, and data are input to and output from thesense amplifier 4 and thewrite circuit 5 that are connected in parallel via an I/O buffer 6.Numerals 7 are a plurality of I/O terminals provided corresponding to the I/O buffers 6. - In the nonvolatile semiconductor memory device according to related art shown in FIG. 8, in order to carry out multiple write into the plurality of sectors S1, S2, . . . , Sn−1 and Sn, a plurality (4 bytes) of
bit lines 1 a are selected simultaneously by thelogic circuit 3 based on a multi-program testmode entry signal 8, and the same data are written simultaneously to the corresponding memory cell arrays from eachwrite circuit 5. - Now, when the multi-program is adopted in a nonvolatile semiconductor memory device as shown in FIG. 8, it is necessary after the completion of the operation to check the result of the write by a write verify test mode in order to confirm whether or not the data are written normally.
- However, in the test mode it is necessary to apply a voltage of about 7V to the word lines of the memory cell arrays from an external power supply terminal that is not shown. It incurs an additional test time of 5 ns/address and results in a drawback of diluting the effect of reducing the test time.
- In order to resolve the above problem possessed by the nonvolatile semiconductor memory device shown in FIG. 8, a method in which an automatic write operation is carried out, having a test after write as an on-chip incorporated function, has been proposed.
- In FIG. 9 is shown a nonvolatile semiconductor memory device having the function of an automatic write operation according to related art.
- The nonvolatile semiconductor memory device according to related art shown in FIG. 9 is formed by adding a
data control circuit 9 and astatus circuit 10 to the circuit shown in FIG. 8. - The
data control circuit 9 holds write data input from the I/O buffer 6, and outputs write data to thewrite circuit 5 at the time of writing. At write inspection, thedata control circuit 9 compares data read from thesense amplifier 4 with the write data stored in it, and outputs data (data about the result of the write check for the memory cell array 1) about whether or not they match with each other (write pass) to thestatus circuit 10. - The
status circuit 10, with the write inspection decision data as an input, outputs pass/fail decision data that indicate whether or not successful write to thememory cell array 1 was obtained, to the I/O terminal 7 and anoperation control circuit 11. - The
operation control circuit 11 completes the write operation to thememory cell array 1 when the write inspection decision data for thememory cell array 1 is a pass, and controls so as to repeat a rewrite and an inspection on the rewrite to thememory cell array 1 when the decision data is a fail. - Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 9 will be described. When an operation command, and subsequent data to be written and an address signal are input from the outside to the memory device, the input data are held in the
data control circuit 9 from the I/O terminal 7 via thebuffer 6. - When the write operation to the
memory cell array 1 is started under the control of theoperation control circuit 11 in this state, the write data held in thedata control circuit 9 are written through thewrite circuit 5 to the memory cell in the sector S1, S2, . . . , Sn−1 or Sn selected by the input address signal. - Next, when the write inspection operation to the
memory cell array 1 is started under the control of theoperation control circuit 11, thedata control circuit 9 reads the write inspection data for thememory cell array 1 through thesense amplifier 4, compares the write inspection data with the write data that are stored in thedata control circuit 9, and outputs data (write inspection decision data for the memory cell array 1) as to whether or not they match (write pass) to thestatus circuit 10. - In the meantime, the
status circuit 10, with the write inspection decision data for thememory cell array 1 output from thedata control circuit 9 as an input, takes the logical product of the pass/fail decision data which indicate whether or not all thememory cell arrays 1 were successfully written, and when the write to all thememory cell arrays 1 is normally completed, outputs a signal to that effect to the I/O terminal 7. - When the write inspection decision data for the
memory cell arrays 1 is a pass, theoperation control circuit 11 completes the write operation to thememory cell array 1, resets all the operations, and sets the relevant components to a standby state for the next operation. - When the write inspection decision data indicates a fail, the
operation control circuit 11 controls thememory cell array 1 to be subjected to a rewrite of data and an inspection of the rewriting. - However, in the case of automatic write operation for the nonvolatile semiconductor memory device according to the related art shown in FIG. 9, the pass/fail decision data are output by being taken the logical product at a single I/
O terminal 7. Accordingly, when a defective product is to be saved by means of redundancy, it becomes necessary to verify again as to the write operation to whichmemory cell array 1 was decided to be in failure. - Moreover, for the verify mode, it is necessary to apply a voltage of about 7V to the word line of the memory cell array from the terminal of an external power supply, where the test time is 5 ns/address (write time) so that it results in a problem that a long time is wasted for the test.
- It is the object of the present invention to provide a nonvolatile semiconductor memory device which is capable of suppressing the increase in write time due to the increase in the number of parallel write caused by the multiple write, and omitting analogous to the automatic write the time for write verify.
- In order to achieve the above object, in a nonvolatile semiconductor memory device having memory cell region divided into a plurality of sectors, the nonvolatile semiconductor memory device according to the present invention makes it possible to write simultaneously write data to the memory cell arrays divided into the plurality of sectors, and output the inspection result of the write to the outside by scanning the address signals.
- In a nonvolatile semiconductor memory device having memory cell arrays divided into a plurality of sectors, the nonvolatile semiconductor memory device according to this invention includes, write means for simultaneously writing write data to the memory cell arrays divided into the plurality of sectors, write inspection means for conducting write inspection as to match/mismatch between the data written to the memory cell array and the write data to be written to the memory cell array, and outputting pass/fail decision data indicating whether or not the memory cell array was successfully written, hold means for holding the pass/fail decision data for the memory cell array, and output means for outputting to the outside the pass/fail decision data arranged to correspond to each memory cell array in response to the externally input address signals.
- The above and other objects, features and advantage of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
- FIG. 1 is a circuit diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention;
- FIG. 2 is a circuit diagram of a sector MS1 of the device shown in FIG. 1;
- FIG. 3 is a circuit diagram of a controller shown in FIG. 1;
- FIG. 4 is a timing chart of the device shown in FIG. 1;
- FIG. 5 is a circuit diagram showing the nonvolatile semiconductor memory device according to a second embodiment of the present invention;
- FIG. 6 is a circuit diagram of a sector MS1 of the device shown in FIG. 5;
- FIG. 7 is a circuit diagram of a data control circuit of the device shown in FIG. 5;
- FIG. 8 is a circuit diagram showing a nonvolatile semiconductor memory device according to related art; and
- FIG. 9 is another circuit diagram showing a nonvolatile semiconductor memory device according to the related art.
- FIG. 1 is a circuit diagram showing the nonvolatile semiconductor memory device according to a first embodiment of the present invention.
- As shown in FIG. 1, the nonvolatile semiconductor memory device has memory sectors MS1 to MS4.
XY decoders decoders memory cell array 1 a to 1 h. Acontroller 3 is responsive to address signals An−1, An to activate one signal among sector enable signals S0 to S3. Each of the memory sectors MS1 to MS4 is activated by the respective activated sector enable signals. Each of memory sectors MS1 to MS3 are connected to bit lines LB1 to LB4. Each of memory sectors MS2 to MS4 are connected to bit lines LB5 to LB8. The bit lines LB1, LB5 are connected to an output line GO1. The bit lines LB2, LB6 are connected to an input line GI1. The bit lines LB3, LB7 are connected to an output line GO2. The bit lines LB4, LB8 are connected to an input line GI2. The input lines I1, I2 are connected to writecircuits O buffer 6 a is connected to an input of thewrite circuit 5 a and the output line GO1. An I/O buffer 6 b is connected to an input of thewrite circuit 5 b and the output line GO2. Thebuffers terminals operation control circuit 11. Since the structure of each memory sector MS1 to MS4 is substantially identical to each other except sector enable signals receiving at the sectors, respectively, we explain the memory sector MS1 mainly. The explanation of the sectors MS2 toMS 4 is omitted. - FIG. 2 is a circuit diagram of the sector MS1 shown in FIG. 1. The sector MS1 includes
memory cell arrays selectors sense amplifiers data control circuits voltage supply circuits memory cell arrays voltage supply circuit 18 a. - The Y-
selectors selector transistor transistor 19 a. Thedata control circuits exclusive circuits latch circuits gate circuits gate circuits transistors gate circuits latch circuits latch circuits latch circuits sense amplifier exclusive circuits exclusive circuits exclusive circuits exclusive circuits -
Exclusive circuits select transistors - FIG. 3 is a circuit diagram of the
controller 3 shown in FIG. 1. Thecontroller 3 hasinverters NAND circuits 22 to 39. When Multi Program signal has a logic high level, the signals S0 to S3 has logic high levels regardless of levels of address signals An and An−1. In such condition that Multi Program signal has a logic low level, when address signals An and An−1 are (L,L), (L,H), (H,L), and (H,H), the signals S0, S1, S2, and S3 become (H,L,L,L), (L,H,L,L), (L,L,H,L), and (L,L,L,H), respectively. It is noted that “L” means “a logic low level” and “H” means “a logic high level”. When Sector enable signal has a logic high level, the respective sector is activated to access the selected memory cells in it with I/O buffers. - The nonvolatile semiconductor memory device according to first embodiment of this invention shown in FIG. 1, uses the
write circuit memory cell arrays write circuits memory cell arrays 1 a to 1 h. - The data control
circuit 9 inputs write information for thememory cell array 1 via asense amplifier 4, conducts write inspection as to match/mismatch with the write data to be written to thememory cell arrays 1 based on the received information, outputs the pass/fail decision data for thememory cell arrays 1. - Moreover, in order to output the pass/fail decision data to the outside as time series data corresponding to the memory cell arrays in response to externally input address signals, the memory cell region divided into a plurality of sectors are divided into two systems and a
write circuit 5 is provided for each system, and write data are written simultaneously to allmemory cell arrays 1 via a selected word line with the system as a unit. - Furthermore, the bit lines are sequentially activated by appropriately selecting time sequentially the
Y selectors 2. - With this constitution, the memory device is controlled so as to input write data from the
write circuit 5 simultaneously to all memory cell arrays with the system as a unit, by appropriately selecting the word lines and the bit lines time sequentially from theoperation control circuit 11. In the meantime, the device externally outputs the pass/fail decision data for all memory cell arrays in sequence, in response to externally input address signals, by time sequentially selecting theY selectors 2 based on the control from theoperation control circuit 11. - Next, the operation of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described with using FIG. 4. It is assumed that memory cells M11 of
memory cell arrays - First, the memory device will be brought to test mode based on a command from the
operation control circuit 11. - Subsequently, when the
operation control circuit 11 produce a command so that the word line WL1 and the bit lines BL1 is selected by selecting the select line Y0 of theY selectors 2 a to 2 h. At this time, Multi Program signal changes from high level to low level. The sector signals S0 to S3 are therefore activated so that all the sectors MS1 to MS4 are activated. Then, in response to a command, write data are inputted toterminals memory cell arrays 1 a to 1 h through thewrite circuits write circuits voltage supply circuits transistors latches data control circuits 9 a to 9 h as shown at period between T1 and T2 in FIG. 4. - Next, the write inspection operation for the memory cells M11 is conducted. The XY decoders 11 a, 11 b sustain the address signals A0 to An−2 to keep selecting the word line WL1 and the select line Y1. All the memory cells M11 of
memory cell arrays 1 a to 1 h are selected to be read out. Multi Program signal changes low level to high level. - At period between T2 and T3, the only signal So is activated and Data stored in the selected memory cells M11 in memory sector MS1 are read out and transfers into the
data control circuits transistors sense amplifiers data control circuits exclusive circuits latch data control circuits data control circuits operation control circuit 11 via the I/O buffers 6 a, 6 b and the output lines GO1, GO2. It is noted that “T” in FIG. 4 means data match and “F” in FIG. 4 means data mismatch. Thereafter, in sequence, the match/mismatch result data are transferred from the control circuits of sectors MS2 to MS4 into theoperation control circuit 11 via the I/O buffers 6 a, 6 b, by changing the address n−1, n as shown in FIG. 4. - When the
operation control circuit 11 detects that the write to allmemory cell arrays 1 do not complete normally, theoperation control circuit 11 conducts to write the write data to the memory cell arrays failed until the write for allmemory cell arrays 1 a to 1 h is completed normally. - It may be available to provide latch circuits to latch the output of the
exclusive circuits memory cell array 1 a to 1 h until the completion of the test mode. - When write for the
memory cell arrays 1 a to 1 h is completed normally, theoperation control circuit 11 outputs the sector address signals S0 to S3 into thelogic circuit 3 to select sequentially sectors MS1 to MS4. The pass/fail decision data for thememory cell array 1 a to 1 h held in thedata control circuits 9 a to 9 h are outputted to the outside from the I/O terminal 7. - In the above, the timing at which the
operation control circuit 11 reads the pass/fail decision data for memory cell arrays is set at the time when the write to thememory cell arrays 1 is normally completed, but it may be set to be read in the order in which write to thememory cell array 1 is completed normally. - As in the above, according to this embodiment of the invention, the decision result of write inspection for the memory cell arrays is output to the outside by scanning the address signals. Accordingly, it is possible to suppress the increase in the write time due to the increase in the number of parallel writing caused by multiple write, or more specifically, due to the increase in the installation number of memory cell arrays divided into a plurality of sectors. Moreover, analogous to the automatic write, it is possible to omit the time for write verify by outputting the pass/fail decision data for the memory cell arrays to the outside in time sequential arrangement corresponding to the memory cell arrays. Furthermore, this method allows automatic multiple write for plural sectors, and has an advantage of reducing the test time for a flash memory or the like.
- FIG. 5 is a circuit diagram of the nonvolatile semiconductor memory device according to a second embodiment of the present invention.
- The nonvolatile semiconductor memory device shown in FIG. 5 is provided with
write circuits 5 a to 5 h,sense amplifiers 4 a to 4 h, anddata control circuits 9 a to 9 h for each ofmemory cell arrays 1 a to 1 h. The data control circuits has functions of the write inspection means and the hold means. Write data from each ofwrite circuits 5 a to 5 h are written simultaneously to allmemory cell arrays 1 a to 1 h. - Moreover, the
data control circuits 9 a to 9 h each has latch means to hold the pass/fail decision data for thememory cell arrays 1 a to 1 h until the completion of the test mode. - Furthermore, analogous to the first embodiment, this memory device is constructed so as to output to the outside the pass/fail decision data for the memory cell arrays held in the
data control circuits 9 a to 9 h as time sequential data arranged corresponding to thememory cell arrays 1 a to 1 h each by sequentially changing the address signals for respective sectors S1 to S2. - The structure of the memory device according to the second embodiment is explained with using FIG. 5. The explanation of the same structure with the memory device according to the first embodiment is omitted.
- The input/output bus line GL0 is connected between the I/
O buffer 6 a and thedata control circuits O buffer 6 b and thedata control circuits write circuits 5 a to 5 h are connected between thedata control circuits 30 a to 30 h and the Y-selectors 2 a to 2 h. The Y-selectors 2 a to 2 h each is connected to the respective select lines S0 to S3. - FIG. 6 illustrates a circuit diagram of Y-
selectors selectors 2 c to 2 h because those structures are substantially same to those of Y-selectors 2 a to 2 b, except that And-gates - FIG. 7 illustrates a circuit diagram of
data control circuit 30 a shown in FIG. 5. The data controlcircuit 30 a has a first transistor coupled to a line LL0 and receiving a sector select signals S0 and S2. A second transistor is coupled between alatch circuit 16 a and the first transistor and receives a write signal. During a write operation, the write signal becomes a high level so that the second transistor turns ON. A third transistor is coupled between thelatch circuit 16 a and thewrite circuit 5 a and receives a pulse signal C1. When a write data is written into a selected memory cell, the pulse signal C1 is generated to transfer the write data into thewrite circuit 5 a. Anexclusive circuit 15 a has input nodes coupled to thelatch circuit 16 a and thesense amplifier 4 a. A fourth transistor is coupled between the output node of theexclusive circuit 15 a and the first transistor and receives an inverted signal of the write signal. The fourth transistor turns OFF during the write operation and ON during a read operation. During the read operation, the first transistor turns OFF. Asecond latch circuit 50 a is coupled to the connecting point of the first and fourth transistors to latch the match/mismatch result data outputted from theexclusive circuit 15 a. The explanation is omitted for thedata control circuits 30 b to 30 h because those structures are substantially same to that of thedata control circuit 30 a, except that thedata control circuits 30 b to 30 h receive respective signals among S0, S1, S2 and S3. - The structures of
memory cell arrays 1 a to 1 h according to the second embodiment is substantially the same with those ofmemory cell arrays 1 a to 1 h according to the first embodiment. Moreover, theXY decoders - Next, the operation of the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described. First, the memory device is brought to the test mode based on a command from the
operation control circuit 11. - Subsequently, the word line and the bit line are selected based on a command from the
operation control circuit 11. In response to an operation command, write data are input from theexternal terminals memory cell arrays 1 a to 1 h through respective write circuits. At that time, the write data are held in thelatch circuits 16 a each of thedata control circuits 30 a to 30 h. - Next, the write inspection for the
memory cell arrays 1 a to 1 h starts, thedata control circuits 30 a to 30 h receive the data read out from thememory cell arrays 1 a to 1 h via thesense amplifiers 4 a to 4 h. Each of thecircuits 30 a to 30 h conducts match/mismatch comparison between the data read out from the memory cells and the write data in thelatch circuits 16 a and outputs pass/fail decision data for thememory cell arrays 1 a to 1 h. Each of thecircuits 30 a holds the decision data in thelatch circuit 50 a. - When the write to all memory cell arrays do not complete normally, the
operation control circuit 11 repeats data write to the failed memory cell arrays and read of write inspection data for these memory cell arrays once again, and stops the series of write operation upon normal completion of write operation for allmemory cell arrays 1. - In this case, the
data control circuits 30 a to 30 h holds the pass/fail decision data for the memory cell arrays until the completion of the test mode. - When the write to all the memory cell array is completed normally, the
operation control circuit 11 outputs a sector address signal to thelogic circuit 3, and thelogic circuit 3 selects sequentially a plurality of Y selectors to read the pass/fail decision data for all memory cell arrays held in the data control circuit, and outputs the decision data to the outside from the I/O terminals - In the above, the timing at which the
operation control circuit 11 reads the decision result of the write inspection for the memory cell arrays is set at the time when the write for all memory cell arrays is completed in normal fashion. However, the timing may be set in such a manner that it is read in the order normal write is completed for individual memory cell array. - As described in the above, In nonvolatile semiconductor memory devices having memory cell region divided into a plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, the nonvolatile semiconductor memory devices according to the present invention shown in FIG. 1 and FIG. 5 are arranged to be capable of writing simultaneously write data to
memory cell arrays 1 that are divided into the plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, and outputting to the outside the result of the write inspection by scanning the address signals. - More specifically, in nonvolatile semiconductor memory devices having memory cell region divided into a plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, the nonvolatile semiconductor memory devices according to the present invention are provided with write means 5 for simultaneously writing write data to the
memory cell arrays 1 divided into the plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, write inspection means for conducting write inspection as to match/mismatch between the data written to thememory cell arrays 1 and the write data to be written tomemory cell arrays 1, and for outputting pass/fail decision data indicating whether or not thememory cell arrays 1 are successfully written, hold means for holding the pass/fail decision data for thememory cell arrays 1, and output means 3 and 11 for outputting the pass/fail decision data, arranged corresponding to each memory cell array, to the outside in response to externally input address signals. Here, in the case of FIG. 1, adata control circuit 9 is employed as a circuit having both functions of the write inspection means and the hold means. - In the nonvolatile semiconductor memory device according to the present invention as shown in FIG. 1, the write means5 and the hold means are provided for each memory cell array, uses the write means 5 in common to all
memory cell arrays 1, and write data from the write means 5 are written simultaneously to allmemory cell arrays 1. - In the nonvolatile semiconductor memory device according to the present invention as shown in FIG. 5, the write means5, the write inspection means and the hold means are provided for each
memory cell array 1, and write data from each write means 5 are written simultaneously to allmemory cell arrays 1 by writing the write data to each individualmemory cell array 1. - Moreover, in the nonvolatile semiconductor memory devices according to the invention as shown in FIG. 1 and FIG. 5, the hold means is so constructed as to hold the pass/fail decision data for the
memory cell array 1 until the completion of the test mode. - Besides, in the nonvolatile semiconductor memory devices of the invention as shown in FIG. 1 and FIG. 5, the output means3 and 11 are constructed so as to output the pass/fail decision data held in the hold means to the outside for each memory cell array, by sequentially inputting the address signal for each sector MS1, MS2, . . . , MSn−1 and MSn.
- As described in the above, according to this invention in which a nonvolatile semiconductor memory device having memory cell region is divided into a plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, write data are written simultaneously into the plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, and the result of write inspection is output to the outside by scanning the address signals. Accordingly, it is possible to suppress the increase in the number of parallel writings due to multiple write, or more specifically, to suppress the increase in the write time due to the increase in the installation number of memory cell arrays that are divided into a plurality of sectors. Moreover, since the result of the write inspection can be output to the outside as arranged corresponding to the memory cell arrays similar to the multiple write, it is possible to omit the time for write verify.
- Moreover, in a nonvolatile semiconductor memory device having memory cell region divided into a plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, the present invention has the write means 5 for writing write data simultaneously into the plurality of sectors MS1, MS2, . . . , MSn−1 and MSn, the write inspection means for conducting write inspection as to match/mismatch between the data written to the
memory cell arrays 1 and the write data to be written to thememory cell arrays 1, and outputting pass/fail decision data for thememory cell arrays 1, the hold means for holding the pass/fail data for thememory cell arrays 1, and means 3 and 11 for outputting to the outside the pass/fail decision data for thememory cell arrays 1 in response to the externally input address signals. Accordingly, in addition to obtaining the effect mentioned above, it is possible to conduct automatic multiple write for plural sectors by the application of the present invention without introducing a drastic change to the existing configuration, thereby reducing the test time for a flash memory or the like. - Moreover, the nonvolatile semiconductor memory device according to this invention may be configured, as shown in FIG. 1, so as to provide the write inspection means and the hold means for each
memory cell array 1, where the write means 5 is used in common to all memory cell arrays, and write data from the write means 5 are written simultaneously to allmemory cell arrays 1. Alternatively, it may be arranged, as shown in FIG. 5 of the nonvolatile semiconductor memory device according to this invention, so that the write means 5, the write inspection means and the hold means are provided for eachmemory cell array 1, and write data from each write means 5 are written simultaneously to allmemory cell arrays 1 by writing the write data from each write means 5 to eachmemory cell array 1. Accordingly, this invention may be applied corresponding to the configuration of the memory cells, and the versatility of the invention can be expanded. - Moreover, in the nonvolatile semiconductor memory devices according to this invention as shown in FIG. 1 and FIG. 5, the hold means is arranged so as to hold the pass/fail decision data for the
memory cell array 1 until the completion of the test mode, so that the system is capable of coping effectively with the situation even if an accident should happen in the midst of the operation. - Furthermore, in the nonvolatile semiconductor memory devices according to this invention as shown in FIG. 1 and FIG. 5, the output means3 and 11 are configured so as to output to the outside the pass/fail decision data held in the hold means as arranged corresponding to the
memory cell arrays 1 by sequentially inputting the address signals for each sector MS1, MS2, . . . , MSn−1 and MSn. Accordingly, it is possible to output to the outside the pass/fail decision data as time series data for eachmemory cell array 1, so that when a defective product is saved by means of redundancy, write operation to whichmemory cell array 1 was decided to be in failure can be determined quickly and accurately. - According to this invention, the decision result of the write inspection for the memory cell arrays is output to the outside by scanning the address signals. Accordingly, the increase in the write time due to the increase in the number of parallel writes caused by the multiple write, and more specifically, due to the increase in the installation number of the memory cell region that is divided into a plurality of sectors, can be suppressed, and analogous to the case of the automatic write, the time for write verify can be omitted by outputting to the outside the pass/fail decision data for the memory cell arrays in time sequential fashion arranged corresponding to the memory cell arrays.
- It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without deviating from the scope and spirit of the invention.
Claims (7)
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JP2000036794A JP2001229682A (en) | 2000-02-15 | 2000-02-15 | Non-volatile semiconductor memory |
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US8351262B2 (en) | 2007-04-23 | 2013-01-08 | Samsung Electronics Co., Ltd. | Flash memory device and program method thereof |
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