US20010011770A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
- Publication number
- US20010011770A1 US20010011770A1 US09/835,703 US83570301A US2001011770A1 US 20010011770 A1 US20010011770 A1 US 20010011770A1 US 83570301 A US83570301 A US 83570301A US 2001011770 A1 US2001011770 A1 US 2001011770A1
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- Prior art keywords
- leads
- conductive contacts
- semiconductor device
- adhesive surface
- receiving space
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the invention relates to a semiconductor device and a method for fabricating the same, more particularly to a semiconductor device and a method for fabricating the same that can enhance production yield and that can reduce production costs.
- FIGS. 1 to 4 a conventional method for fabricating a semiconductor device is shown.
- a die 10 having an upper surface provided with a plurality of solder pads 100 is attached to a tie bar 130 on a lead frame 13 by means of a double-side adhesive tape 12 to fix the die 10 on the lead frame 13 .
- the solder pads 100 are exposed via a bore 1300 formed in the tie bar 130 , as shown in FIG. 4.
- each of the solder pads 100 is connected electrically to a respective lead 131 of the lead frame 13 via known wire bonding techniques by means of a conductive wire 14 that extends through the bore 1300 .
- a plastic protective layer 15 formed from a moulding compound is used to encapsulate the die 10 and a portion of the lead frame 13 to form the semiconductor device.
- the aforesaid method needs conductive wires 14 for connecting electrically the solder pads 100 and the leads 131 , respectively, thereby requiring an expensive wire bonder that leads to higher fabricating costs.
- the object of the present invention is to provide a semiconductor device and a method for fabricating the same which can overcome the drawbacks associated with the aforesaid prior art.
- a semiconductor device includes a lead frame, a dielectric tape layer, a plurality of conductive contacts and a semiconductor die.
- the lead frame is provided with a plurality of leads.
- the dielectric tape layer has a first adhesive surface adhered onto the leads, and a second adhesive surface opposite to the first adhesive surface.
- the dielectric tape layer is formed with a plurality of holes at positions registered with the leads for access thereto. Each of the holes is confined by a wall that cooperates with a registered one of the leads to form a contact receiving space.
- the conductive contacts are placed in the contact receiving spaces, respectively.
- the die has a die mounting surface adhered onto the second adhesive surface of the dielectric tape layer.
- the die mounting surface is provided with a plurality of contact pads that are bonded to the conductive contacts to establish electrical connection with the leads of the lead frame.
- a method for fabricating the semiconductor device comprises:
- FIGS. 1 to 3 are fragmentary schematic, partly sectional views illustrating a conventional method for fabricating a semiconductor device
- FIG. 4 is a top view showing a lead frame used in the conventional method for fabricating a semiconductor device
- FIGS. 5 to 8 are fragmentary schematic, partly sectional views illustrating the steps of the method for fabricating the first preferred embodiment of a semiconductor device according to the present invention.
- FIG. 9 is a top view of the first preferred embodiment
- FIG. 10 is a fragmentary schematic, partly sectional view illustrating one of the steps of the method for fabricating the second preferred embodiment of a semiconductor device according to the present invention.
- FIGS. 11 and 12 are fragmentary schematic, partly sectional views illustrating some of the steps of the method for fabricating the third preferred embodiment of a semiconductor device according to the present invention.
- FIG. 13 is a top view showing the fourth preferred embodiment of a semiconductor device according to the present invention.
- FIG. 14 is a top view showing the fifth preferred embodiment of a semiconductor device according to the present invention.
- FIG. 15 is a top view showing the sixth preferred embodiment of a semiconductor device according to the present invention.
- FIGS. 16 and 17 are fragmentary schematic, partly sectional views illustrating some of the steps of the method for fabricating the seventh preferred embodiment of a semiconductor device according to the present invention.
- FIG. 18 is a fragmentary schematic, partly sectional view showing the eighth preferred embodiment of a semiconductor device according to the present invention.
- the first preferred embodiment of a semiconductor device 2 according to the present invention is shown to include a lead frame 3 , two dielectric tape layers 4 and a semiconductor die 5 .
- the lead frame 3 is provided with a plurality of leads 30 at left and right sides thereof.
- Each of the dielectric tape layers 4 has a first adhesive surface 40 adhered onto the leads 30 by heat-curing of a heat-curable adhesive that is provided thereon, and a second adhesive surface 42 opposite to the first adhesive surface 40 .
- a conventional laser cutting technique is employed to form a plurality of holes 44 in each of the dielectric tape layers 4 at positions registered with the leads 30 for access thereto, as shown in FIG. 5.
- Each of the holes 44 is confined by a wall 46 that cooperates with a registered one of the leads 30 to form a contact receiving space.
- a plurality of conductive contacts 48 are placed in the contact receiving spaces, respectively.
- a tin ball is planted in each contact receiving space and serves as a conductive contact 48 , as shown in FIG. 6.
- the die 5 has a die mounting surface 52 provided with a plurality of contact pads 50 that are arranged at equal intervals in two rows.
- the contact pads 50 in the left side row are connected to the leads 30 on the left side of the lead frame 3
- the contact pads 50 in the right side row are connected to the leads 30 on the right side of the lead frame 3 , as shown in FIG. 9.
- the contact pads 50 are to be aligned with and are to be connected to the conductive contacts 48 .
- a heat curing operation is conducted to bond the conductive contacts 48 to the contact pads 50 , and to adhere the die mounting surface 52 onto the second adhesive surface 42 of the dielectric tape layer 4 , as shown in FIG. 7.
- the second adhesive surface 42 is provided with a heat-curable adhesive 43 having a curing point that is lower than the melting point of the contact pads 43 .
- the die mounting surface 52 is already adhered onto the second adhesive surface 42 prior to melting of the conductive contacts 48 , thereby sealing the contact receiving spaces so that the melt of each conductive contact 48 is prevented from flowing out of the respective contact receiving space to avoid formation of undesired connections with adjacent conductive contacts 48 .
- a dielectric casing 6 is formed using known packaging techniques to enclose the semiconductor die 5 and a portion of the lead frame 3 .
- each conductive contact 48 ′ is formed from conductive paste, such as conductive silver paste.
- each conductive contact 48 ′′ is formed by placing a conductive metal material 49 , such as a gold or aluminum ball, in each contact receiving space. A chemical electroplating process is subsequently performed to complete each conductive contact 48 ′′ prior to bonding with the contact pads on the semiconductor die (not shown).
- a conductive metal material 49 such as a gold or aluminum ball
- the contact pads 50 are arranged at equal intervals in a single row, and are connected alternately to the leads 30 at the left and right sides of the lead frame 3 , which are staggered relative to each other.
- the contact pads 50 are arranged along the periphery of the die 5 at equal intervals. Each contact pad 50 is connected to a corresponding lead 30 provided along the periphery of the lead frame 3 .
- the contact pads 50 are arranged at equal intervals in four rows, such as a front row, a rear row and two intermediate rows.
- the front and rear rows of contact pads 50 are connected to corresponding leads 30 on front and rear ends of the lead frame 3 .
- the intermediate rows of contact pads 50 are connected to corresponding leads 30 on left and right sides of the lead frame 3 .
- the semiconductor device 2 further includes a dielectric housing 60 and a dielectric cover 61 .
- the housing 60 which is made from a moulding compound, has a base plate 601 , and a surrounding wall 602 that extends upwardly from a periphery of the base plate 601 and that cooperates with the base plate 61 to confine a receiving space 603 .
- the housing 60 further has an inner peripheral surface 6021 .
- An engaging groove 6022 is formed in the inner peripheral surface 6021 of the housing 60 .
- the lead frame 3 is disposed inside the receiving space 603 .
- Each of the leads 30 has a first end 31 disposed in the housing 60 , and a second end 32 extending outwardly of the receiving space 603 through the surrounding wall 602 .
- the dielectric tape layer 4 and the semiconductor die 5 are disposed on the leads 30 of the lead frame 3 in a manner similar to that of the previous embodiments.
- the cover 61 which is made from epoxy resin having a melting point lower than that of the moulding compound, is provided on the housing 60 at one side 54 of the semiconductor die 5 opposite to the die mounting surface 52 .
- the cover 61 has an outer peripheral flange 612 engaged within the engaging groove 6022 to seal the receiving space 603 and retain the semiconductor die 5 inside the receiving space.
- the cover 61 ′ fills the receiving space 603 ′ of the housing 60 ′ to enclose the semiconductor die 5 .
- the contact pads 50 of the semiconductor die 5 are electrically connected to the leads 30 of the lead frame 3 via the conductive contacts 48 instead of conductive wires, thereby obviating the need for an expensive wire bonder so as to reduce the fabricating costs.
- Each of the conductive contacts 48 is confined within a sealed space after adhering the die mounting surface 50 of the semiconductor die 5 onto the dielectric tape layer 4 so as to avoid corrosion and short circuiting due to excessively high humidity.
- the cover 61 can be removed by heating, thus facilitating inspection and recycling of the semiconductor die 5 .
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
A semiconductor device includes a lead frame, a dielectric tape layer, a plurality of conductive contacts and a semiconductor die. The lead frame is provided with a plurality of leads. The dielectric tape layer has a first adhesive surface adhered onto the leads, and a second adhesive surface opposite to the first adhesive surface. The dielectric tape layer is formed with a plurality of holes at positions registered with the leads for access thereto. Each of the holes is confined by a wall that cooperates with a registered one of the leads to form a contact receiving space. The conductive contacts are placed in the contact receiving spaces, respectively. The die has a die mounting surface adhered onto the second adhesive surface of the dielectric tape layer. The die mounting surface is provided with a plurality of contact pads that are bonded to the conductive contacts to establish electrical connection with the leads of the lead frame. A method for fabricating the semiconductor device is also disclosed.
Description
- 1. Field of the Invention
- The invention relates to a semiconductor device and a method for fabricating the same, more particularly to a semiconductor device and a method for fabricating the same that can enhance production yield and that can reduce production costs.
- 2. Description of the Related Art
- Referring to FIGS.1 to 4, a conventional method for fabricating a semiconductor device is shown. As shown in FIG. 1, a
die 10 having an upper surface provided with a plurality ofsolder pads 100 is attached to atie bar 130 on alead frame 13 by means of a double-sideadhesive tape 12 to fix thedie 10 on thelead frame 13. Thesolder pads 100 are exposed via abore 1300 formed in thetie bar 130, as shown in FIG. 4. Referring to FIG. 2, each of thesolder pads 100 is connected electrically to arespective lead 131 of thelead frame 13 via known wire bonding techniques by means of aconductive wire 14 that extends through thebore 1300. Referring to FIG. 3, a plasticprotective layer 15 formed from a moulding compound is used to encapsulate thedie 10 and a portion of thelead frame 13 to form the semiconductor device. - The following are some of the drawbacks of the conventional method for fabricating the semiconductor device:
- 1. The aforesaid method needs
conductive wires 14 for connecting electrically thesolder pads 100 and theleads 131, respectively, thereby requiring an expensive wire bonder that leads to higher fabricating costs. - 2. In the aforesaid method, because there is a height difference between the
solder pads 100 and theleads 131, wire bonding is unstable and inconvenient to conduct, thereby resulting in a relatively low production yield. - 3. In the aforesaid method, when the die10 needs to be inspected, it will take a relatively long time to remove the plastic
protective layer 15 from thedie 10, thereby further increasing the fabricating costs. - Therefore, the object of the present invention is to provide a semiconductor device and a method for fabricating the same which can overcome the drawbacks associated with the aforesaid prior art.
- According to one aspect of the present invention, a semiconductor device includes a lead frame, a dielectric tape layer, a plurality of conductive contacts and a semiconductor die.
- The lead frame is provided with a plurality of leads.
- The dielectric tape layer has a first adhesive surface adhered onto the leads, and a second adhesive surface opposite to the first adhesive surface. The dielectric tape layer is formed with a plurality of holes at positions registered with the leads for access thereto. Each of the holes is confined by a wall that cooperates with a registered one of the leads to form a contact receiving space.
- The conductive contacts are placed in the contact receiving spaces, respectively.
- The die has a die mounting surface adhered onto the second adhesive surface of the dielectric tape layer. The die mounting surface is provided with a plurality of contact pads that are bonded to the conductive contacts to establish electrical connection with the leads of the lead frame.
- According to another aspect of the present invention, a method for fabricating the semiconductor device comprises:
- adhering a first adhesive surface of a dielectric tape layer on a plurality of leads that are provided on a lead frame, the dielectric tape layer being formed with a plurality of holes at positions registered with the leads for access thereto, each of the holes being confined by a wall that cooperates with a registered one of the leads to form a contact receiving space;
- placing a plurality of conductive contacts in the contact receiving spaces, respectively; and
- adhering a die mounting surface of a semiconductor die onto a second adhesive surface of the dielectric tape layer opposite to the first adhesive surface, and bonding a plurality of contact pads that are provided on the die mounting surface of the semiconductor die to the conductive contacts to establish electrical connection with the leads of the lead frame.
- Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:
- FIGS.1 to 3 are fragmentary schematic, partly sectional views illustrating a conventional method for fabricating a semiconductor device;
- FIG. 4 is a top view showing a lead frame used in the conventional method for fabricating a semiconductor device;
- FIGS.5 to 8 are fragmentary schematic, partly sectional views illustrating the steps of the method for fabricating the first preferred embodiment of a semiconductor device according to the present invention;
- FIG. 9 is a top view of the first preferred embodiment;
- FIG. 10 is a fragmentary schematic, partly sectional view illustrating one of the steps of the method for fabricating the second preferred embodiment of a semiconductor device according to the present invention;
- FIGS. 11 and 12 are fragmentary schematic, partly sectional views illustrating some of the steps of the method for fabricating the third preferred embodiment of a semiconductor device according to the present invention;
- FIG. 13 is a top view showing the fourth preferred embodiment of a semiconductor device according to the present invention;
- FIG. 14 is a top view showing the fifth preferred embodiment of a semiconductor device according to the present invention;
- FIG. 15 is a top view showing the sixth preferred embodiment of a semiconductor device according to the present invention;
- FIGS. 16 and 17 are fragmentary schematic, partly sectional views illustrating some of the steps of the method for fabricating the seventh preferred embodiment of a semiconductor device according to the present invention; and
- FIG. 18 is a fragmentary schematic, partly sectional view showing the eighth preferred embodiment of a semiconductor device according to the present invention.
- Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure.
- Referring to FIGS.5 to 9, the first preferred embodiment of a
semiconductor device 2 according to the present invention is shown to include alead frame 3, twodielectric tape layers 4 and asemiconductor die 5. - The
lead frame 3 is provided with a plurality ofleads 30 at left and right sides thereof. - Each of the
dielectric tape layers 4 has a firstadhesive surface 40 adhered onto theleads 30 by heat-curing of a heat-curable adhesive that is provided thereon, and a secondadhesive surface 42 opposite to the firstadhesive surface 40. A conventional laser cutting technique is employed to form a plurality ofholes 44 in each of thedielectric tape layers 4 at positions registered with theleads 30 for access thereto, as shown in FIG. 5. - Each of the
holes 44 is confined by awall 46 that cooperates with a registered one of theleads 30 to form a contact receiving space. A plurality ofconductive contacts 48 are placed in the contact receiving spaces, respectively. In this embodiment, a tin ball is planted in each contact receiving space and serves as aconductive contact 48, as shown in FIG. 6. - The die5 has a
die mounting surface 52 provided with a plurality ofcontact pads 50 that are arranged at equal intervals in two rows. In this embodiment, thecontact pads 50 in the left side row are connected to theleads 30 on the left side of thelead frame 3, while thecontact pads 50 in the right side row are connected to theleads 30 on the right side of thelead frame 3, as shown in FIG. 9. Thecontact pads 50 are to be aligned with and are to be connected to theconductive contacts 48. A heat curing operation is conducted to bond theconductive contacts 48 to thecontact pads 50, and to adhere thedie mounting surface 52 onto the secondadhesive surface 42 of thedielectric tape layer 4, as shown in FIG. 7. Preferably, the secondadhesive surface 42 is provided with a heat-curable adhesive 43 having a curing point that is lower than the melting point of thecontact pads 43. Thus, thedie mounting surface 52 is already adhered onto the secondadhesive surface 42 prior to melting of theconductive contacts 48, thereby sealing the contact receiving spaces so that the melt of eachconductive contact 48 is prevented from flowing out of the respective contact receiving space to avoid formation of undesired connections with adjacentconductive contacts 48. Thereafter, a dielectric casing 6 is formed using known packaging techniques to enclose thesemiconductor die 5 and a portion of thelead frame 3. - Referring to FIG. 10, in the second preferred embodiment of a semiconductor device according to the present invention, instead of using tin balls as conductive contacts, each
conductive contact 48′ is formed from conductive paste, such as conductive silver paste. - Referring to FIGS. 11 and 12, in the third preferred embodiment of a semiconductor device according to the present invention, each
conductive contact 48″ is formed by placing aconductive metal material 49, such as a gold or aluminum ball, in each contact receiving space. A chemical electroplating process is subsequently performed to complete eachconductive contact 48″ prior to bonding with the contact pads on the semiconductor die (not shown). - Referring to FIG. 13, in the fourth preferred embodiment of a semiconductor device according to the present invention, the
contact pads 50 are arranged at equal intervals in a single row, and are connected alternately to theleads 30 at the left and right sides of thelead frame 3, which are staggered relative to each other. - Referring to FIG. 14, in the fifth preferred embodiment of a semiconductor device according to the present invention, the
contact pads 50 are arranged along the periphery of thedie 5 at equal intervals. Eachcontact pad 50 is connected to acorresponding lead 30 provided along the periphery of thelead frame 3. - Referring to FIG. 15, in the sixth preferred embodiment of a semiconductor device according to the present invention, the
contact pads 50 are arranged at equal intervals in four rows, such as a front row, a rear row and two intermediate rows. The front and rear rows ofcontact pads 50 are connected to corresponding leads 30 on front and rear ends of thelead frame 3. The intermediate rows ofcontact pads 50 are connected to corresponding leads 30 on left and right sides of thelead frame 3. - Referring to FIGS. 16 and 17, in the seventh preferred embodiment of a semiconductor device according to the present invention, instead of the dielectric casing6, the
semiconductor device 2 further includes adielectric housing 60 and adielectric cover 61. Thehousing 60, which is made from a moulding compound, has abase plate 601, and asurrounding wall 602 that extends upwardly from a periphery of thebase plate 601 and that cooperates with thebase plate 61 to confine a receivingspace 603. Thehousing 60 further has an innerperipheral surface 6021. An engaginggroove 6022 is formed in the innerperipheral surface 6021 of thehousing 60. Thelead frame 3 is disposed inside the receivingspace 603. Each of theleads 30 has afirst end 31 disposed in thehousing 60, and asecond end 32 extending outwardly of the receivingspace 603 through the surroundingwall 602. Subsequently, thedielectric tape layer 4 and the semiconductor die 5 are disposed on theleads 30 of thelead frame 3 in a manner similar to that of the previous embodiments. Thereafter, in this embodiment, thecover 61, which is made from epoxy resin having a melting point lower than that of the moulding compound, is provided on thehousing 60 at oneside 54 of the semiconductor die 5 opposite to thedie mounting surface 52. Thecover 61 has an outerperipheral flange 612 engaged within the engaginggroove 6022 to seal the receivingspace 603 and retain the semiconductor die 5 inside the receiving space. With the construction as such, thesemiconductor device 2 can be heated to melt thecover 61 for removing the same in order to facilitate inspection of the semiconductor die 5. - Referring to FIG. 18, in the eighth preferred embodiment of a semiconductor device according to the present invention, unlike the seventh preferred embodiment shown in FIG. 17, the
cover 61′ fills the receivingspace 603′ of thehousing 60′ to enclose the semiconductor die 5. - The following are some of the advantages of the present invention:
- 1. The
contact pads 50 of the semiconductor die 5 are electrically connected to theleads 30 of thelead frame 3 via theconductive contacts 48 instead of conductive wires, thereby obviating the need for an expensive wire bonder so as to reduce the fabricating costs. - 2. Each of the
conductive contacts 48 is confined within a sealed space after adhering thedie mounting surface 50 of the semiconductor die 5 onto thedielectric tape layer 4 so as to avoid corrosion and short circuiting due to excessively high humidity. - 3. Because the
conductive contacts 48 are in use instead of the conventional conductive wires, the production yield can be increased. - 4. The
cover 61 can be removed by heating, thus facilitating inspection and recycling of the semiconductor die 5. - While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Claims (32)
1. A semiconductor device, comprising:
a lead frame provided with a plurality of leads;
a dielectric tape layer having a first adhesive surface adhered onto said leads, and a second adhesive surface opposite to said first adhesive surface, said dielectric tape layer being formed with a plurality of holes at positions registered with said leads for access thereto, each of said holes being confined by a wall that cooperates with a registered one of said leads to form a contact receiving space;
a plurality of conductive contacts placed in said contact receiving spaces, respectively; and
a semiconductor die having a die mounting surface adhered onto said second adhesive surface of said dielectric tape layer, said die mounting surface being provided with a plurality of contact pads that are bonded to said conductive contacts to establish electrical connection with said leads of said lead frame.
2. The semiconductor device as claimed in , wherein said second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of said conductive contacts.
claim 1
3. The semiconductor device as claimed in , wherein each of said conductive contacts is a tin ball.
claim 1
4. The semiconductor device as claimed in , wherein each of said conductive contacts is formed from conductive paste.
claim 1
5. The semiconductor device as claimed in , wherein each of said conductive contacts is formed from a conductive material that undergoes chemical electroplating prior to bonding with said contact pads.
claim 1
6. The semiconductor device as claimed in , further comprising a dielectric casing to enclose said semiconductor die and a portion of said lead frame.
claim 1
7. A semiconductor device, comprising:
a dielectric housing having a base plate and a surrounding wall extending upwardly from a periphery of said base plate, and cooperating with said base plate to confine a receiving space;
a lead frame disposed inside said receiving space, said lead frame being provided with a plurality of leads, each of said leads having a first end disposed in said housing and a second end extending outwardly of said receiving space through said surrounding wall;
a dielectric tape layer having a first adhesive surface adhered onto said leads in said receiving space of said housing, and a second adhesive surface opposite to said first adhesive surface, said dielectric tape layer being formed with a plurality of holes at positions registered with said leads for access thereto, each of said holes being confined by a wall that cooperates with a registered one of said leads to form a contact receiving space;
a plurality of conductive contacts placed in said contact receiving spaces, respectively;
a semiconductor die having a die mounting surface adhered onto said second adhesive surface of said dielectric tape layer, said die mounting surface being provided with a plurality of contact pads that are bonded to said conductive contacts to establish electrical connection with said leads of said lead frame; and
a dielectric cover provided on said housing to seal said receiving space and retain said semiconductor die inside said receiving space.
8. The semiconductor device as claimed in , wherein said second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of said conductive contacts.
claim 7
9. The semiconductor device as claimed in , wherein said cover has a melting point lower than that of said housing.
claim 7
10. The semiconductor device as claimed in , wherein said cover is disposed at one side of said semiconductor die opposite to said die mounting surface.
claim 9
11. The semiconductor device as claimed in , wherein said cover fills said receiving space of said housing.
claim 9
12. The semiconductor device as claimed in , wherein said cover is made from epoxy resin.
claim 9
13. The semiconductor device as claimed in , wherein each of said conductive contacts is a tin ball.
claim 7
14. The semiconductor device as claimed in , wherein each of said conductive contacts is formed from conductive paste.
claim 7
15. The semiconductor device as claimed in , wherein each of said conductive contacts is formed from a conductive material that undergoes chemical electroplating prior to bonding with said contact pads.
claim 7
16. A method for fabricating a semiconductor device, comprising:
adhering a first adhesive surface of a dielectric tape layer on a plurality of leads that are provided on a lead frame, the dielectric tape layer being formed with a plurality of holes at positions registered with the leads for access thereto, each of the holes being confined by a wall that cooperates with a registered one of the leads to form a contact receiving space;
placing a plurality of conductive contacts in the contact receiving spaces, respectively; and
adhering a die mounting surface of a semiconductor die onto a second adhesive surface of the dielectric tape layer opposite to the first adhesive surface, and bonding a plurality of contact pads that are provided on the die mounting surface of the semiconductor die to the conductive contacts to establish electrical connection with the leads of the lead frame.
17. The method as claimed in , wherein the second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of the conductive contacts, and adhering of the semiconductor die onto the dielectric tape layer and bonding of the contact pads to the conductive contacts are performed simultaneously through a heat curing operation such that the die mounting surface is already adhered onto the second adhesive surface prior to melting of the conductive contacts.
claim 16
18. The method as claimed in , wherein adhering of the dielectric tape layer onto the leads is accomplished by heat curing of a heat-curable adhesive provided on the first adhesive surface.
claim 16
19. The method as claimed in , wherein each of the conductive contacts is a tin ball.
claim 16
20. The method as claimed in , wherein each of the conductive contacts is formed from conductive paste.
claim 16
21. The method as claimed in , wherein each of the conductive contacts is formed from a conductive material that undergoes chemical electroplating prior to bonding with the contact pads.
claim 16
22. The method as claimed in , further comprising the step of forming a dielectric casing to enclose the semiconductor die and a portion of the lead frame.
claim 16
23. A method for fabricating a semiconductor device, comprising:
providing a dielectric housing having a base plate and a surrounding wall that extends upwardly from a periphery of the base plate, and that cooperates with the base plate to confine a receiving space;
placing a lead frame inside the receiving space of the housing such that each of a plurality of leads that are provided on the lead frame has a first end disposed in the housing and a second end extending outwardly of the receiving space through the surrounding wall;
adhering a first adhesive surface of a dielectric tape layer onto the leads in the receiving space of the housing, the dielectric tape layer being formed with a plurality of holes at positions registered with the leads for access thereto, each of the holes being confined by a wall that cooperates with a registered one of the leads to form a contact receiving space;
placing a plurality of conductive contacts in the contact receiving spaces, respectively;
adhering a die mounting surface of a semiconductor die onto the second adhesive surface of the dielectric tape layer opposite to the first adhesive surface, and bonding a plurality of contact pads that are provided on the die mounting surface to the conductive contacts to establish electrical connection with the leads of the lead frame; and
providing a dielectric cover on the housing to seal the receiving space and retain the semiconductor die inside the receiving space.
24. The method as claimed in , wherein the second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of the conductive contacts, and adhering of the semiconductor die onto the dielectric tape layer and bonding of the contact pads to the conductive contacts are performed simultaneously through a heat curing operation such that the die mounting surface is already adhered onto the second adhesive surface prior to melting of the conductive contacts.
claim 23
25. The method as claimed in , wherein adhering of the dielectric tape layer onto the leads is accomplished by heat curing of a heat-curable adhesive provided on the first adhesive surface.
claim 23
26. The method as claimed in , wherein each of the conductive contacts is a tin ball.
claim 23
27. The method as claimed in , wherein each of the conductive contacts is formed from conductive paste.
claim 23
28. The method as claimed in , wherein each of the conductive contacts is formed from a conductive material that undergoes chemical electroplating prior to bonding with the contact pads.
claim 23
29. The method as claimed in , wherein the cover has a melting point lower than that of the housing.
claim 23
30. The method as claimed in , wherein the cover is disposed at one side of the semiconductor die opposite to the die mounting surface.
claim 29
31. The method as claimed in , wherein the cover fills the receiving space of the housing.
claim 29
32. The method as claimed in , wherein the cover is made from epoxy resin.
claim 29
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/835,703 US20010011770A1 (en) | 1999-08-05 | 2001-04-16 | Semiconductor device and method for fabricating the same |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW88113399A TW416115B (en) | 1999-08-05 | 1999-08-05 | Method for packaging semiconductor dies |
TW88113399 | 1999-08-05 | ||
TW88213225U TW427557U (en) | 1999-08-05 | 1999-08-05 | Semiconductor integrated circuit device |
US09/400,592 US6246109B1 (en) | 1999-08-05 | 1999-09-22 | Semiconductor device and method for fabricating the same |
US09/835,703 US20010011770A1 (en) | 1999-08-05 | 2001-04-16 | Semiconductor device and method for fabricating the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/400,592 Division US6246109B1 (en) | 1999-08-05 | 1999-09-22 | Semiconductor device and method for fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20010011770A1 true US20010011770A1 (en) | 2001-08-09 |
Family
ID=26666727
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/400,592 Expired - Fee Related US6246109B1 (en) | 1999-08-05 | 1999-09-22 | Semiconductor device and method for fabricating the same |
US09/835,703 Abandoned US20010011770A1 (en) | 1999-08-05 | 2001-04-16 | Semiconductor device and method for fabricating the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/400,592 Expired - Fee Related US6246109B1 (en) | 1999-08-05 | 1999-09-22 | Semiconductor device and method for fabricating the same |
Country Status (2)
Country | Link |
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US (2) | US6246109B1 (en) |
JP (1) | JP3220691B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6310390B1 (en) | 1999-04-08 | 2001-10-30 | Micron Technology, Inc. | BGA package and method of fabrication |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4303934A (en) | 1979-08-30 | 1981-12-01 | Burr-Brown Research Corp. | Molded lead frame dual in line package including a hybrid circuit |
JPS63209152A (en) | 1987-02-25 | 1988-08-30 | Nec Corp | Lead frame |
US5086558A (en) | 1990-09-13 | 1992-02-11 | International Business Machines Corporation | Direct attachment of semiconductor chips to a substrate with a substrate with a thermoplastic interposer |
US5559366A (en) * | 1994-08-04 | 1996-09-24 | Micron Technology, Inc. | Lead finger tread for a semiconductor lead package system |
JPH08264706A (en) | 1995-03-20 | 1996-10-11 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH08288424A (en) * | 1995-04-18 | 1996-11-01 | Nec Corp | Semiconductor device |
JPH08306840A (en) | 1995-05-11 | 1996-11-22 | Toppan Printing Co Ltd | Manufacture of lead frame with bumps |
JPH10214925A (en) * | 1996-11-28 | 1998-08-11 | Nitto Denko Corp | Sealing label for sealing semiconductor device |
JP3593833B2 (en) * | 1997-02-10 | 2004-11-24 | 富士通株式会社 | Semiconductor device |
-
1999
- 1999-09-22 US US09/400,592 patent/US6246109B1/en not_active Expired - Fee Related
- 1999-10-14 JP JP29231099A patent/JP3220691B2/en not_active Expired - Fee Related
-
2001
- 2001-04-16 US US09/835,703 patent/US20010011770A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP3220691B2 (en) | 2001-10-22 |
JP2001053107A (en) | 2001-02-23 |
US6246109B1 (en) | 2001-06-12 |
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