US20010010965A1 - Method for fabricating semiconductor device including capacitor with improved bottom electrode - Google Patents
Method for fabricating semiconductor device including capacitor with improved bottom electrode Download PDFInfo
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- US20010010965A1 US20010010965A1 US09/794,143 US79414301A US2001010965A1 US 20010010965 A1 US20010010965 A1 US 20010010965A1 US 79414301 A US79414301 A US 79414301A US 2001010965 A1 US2001010965 A1 US 2001010965A1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 112
- 239000001301 oxygen Substances 0.000 claims abstract description 63
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 63
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 61
- 230000004888 barrier function Effects 0.000 claims abstract description 52
- 238000009792 diffusion process Methods 0.000 claims abstract description 50
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910052741 iridium Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052703 rhodium Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910019897 RuOx Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910010252 TiO3 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002926 oxygen Chemical class 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- the present invention relates to a memory device with a high device packing density, and more particularly, a semiconductor device including a capacitor with an improved bottom electrode and a method for fabricating the same.
- a semiconductor memory device is provided with a driving transistor and a capacitor which stores information therein.
- a volatile memory device such as a dynamic random access memory (DRAM) stores information as an amount of charge in the capacitor.
- the amount of charge stored in the memory device, such as a DRAM can be increased as follows: fabricating a three dimensional capacitor to increase an effective area of the capacitor; reducing a thickness of a dielectric in the capacitor; and using a dielectric having a higher dielectric constant.
- the stored charge is increased by using high dielectric constant dielectric films.
- the high dielectric constant dielectric films (Ba, Sr)TiO 3 and (Pb, La)(Zr,Ti)O 3 may be used.
- the high dielectric constant dielectric films BST[(Ba, Sr)TiO 3 ] are mostly used in DRAMs, and the high dielectric constant dielectric films PZT(PbZrTiO 3 ) are mostly used in flash random access memories (FRAMs).
- a high dielectric constant dielectric film such as BST is deposited on a silicon substrate directly, the silicon oxidizes making a defective contact or the BST film degrades due to a reaction between BST and Si. Because of this, when high dielectric constant dielectric films such as BST are used as the dielectric of a capacitor, a metal film such as Pt, Ru and Ir, which is less reactive, is usually used as the bottom electrode of the capacitor. This is applicable to both DRAMs and FRAMs.
- a memory device having a device packing density greater than the giga class can be fabricated according to the simple structure shown in FIG. 1.
- an interlayer insulation layer 2 is formed on a substrate 1 , and has a contact hole formed therein.
- a plug 3 fills the contact hole, and a barrier 4 is formed on the substrate 1 and the plug 3 .
- a bottom electrode 5 is formed on the barrier 4 , and a dielectric 6 covers the interlayer insulation layer 2 , the bottom electrode 5 and the barrier layer 4 .
- a top electrode (not shown) is then formed on the dielectric 6 .
- FIG. 2A illustrates the use of Pt as the bottom electrode 5 .
- Pt has a great work function, which results in excellent electrical characteristics and reduced leakage current, but Pt is oxygen permeable.
- oxidation at the barrier 4 and plug 3 interface takes place to form an oxide layer 7 .
- this oxidation consumes the barrier 4 .
- the oxygen diffuses mostly along the Pt grain boundaries during the formation of the dielectric 6 causing oxygen holes in the dielectric 6 , which degrades the electrical characteristics thereof.
- FIG. 2B illustrate the use of Ru as the bottom electrode 5 .
- the bottom electrode 5 is usually oxidized prior to deposition of the dielectric 6 so that the oxide layer formed therein prevents further oxidation using the oxygen in the dielectric 6 .
- the Ru bottom electrode 5 is formed through etching with oxygen to form an oxide layer 9 , RuOx, at the surface of the Ru bottom electrode 5 as shown in FIG. 2B.
- the oxide of Ru conducts. But the oxide of Ru also forms a rugged deposition surface as shown in FIG. 2B. Because of this rugged surface, the oxide layer 9 has poor electrical characteristics.
- One object of the present invention is to provide a semiconductor device including a capacitor with an improved bottom electrode that overcomes the disadvantages and problems noted above with respect to the conventional art.
- Another object of the present invention is to provide a semiconductor device including a capacitor with an improved bottom electrode and therefore improved electrical characteristics.
- a semiconductor device having a capacitor with a bottom electrode comprising: a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the contact hole; a first bottom electrode formed on a portion of the interlayer insulating layer and over the contact hole; a first oxygen diffusion barrier formed on the first bottom electrode; a second bottom electrode formed on the first oxygen diffusion barrier; and a third bottom electrode formed on sidewalls of the first bottom electrode, the first oxygen diffusion barrier and the second bottom electrode.
- a method of forming a semiconductor device having a capacitor with a bottom electrode comprising: providing a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the hole; forming a first bottom electrode layer on the interlayer insulating layer over the hole; forming a first oxygen diffusion barrier layer on the first bottom electrode layer; forming a second bottom electrode layer on the first oxygen diffusion barrier layer; selectively removing portions of the second bottom electrode layer, the oxygen diffusion barrier layer and the first bottom electrode layer to form a bottom electrode pattern; and forming a third bottom electrode on sidewalls of the bottom electrode pattern.
- FIG. 1 illustrates a cross-section of a partially formed conventional capacitor in a semiconductor device
- FIGS. 2A and 2B illustrate cross-sections of the conventional art capacitor using Pt as the bottom electrode
- FIG. 3 illustrates a cross-section of the conventional art capacitor using Ru as the bottom electrode
- FIG. 4 illustrates a cross-section of a partially formed capacitor in a semiconductor device in accordance with a preferred embodiment of the present invention
- FIGS. 5A - 5 F illustrate the process steps of the method for fabricating a semiconductor device having a capacitor with an improved bottom electrode in accordance with a preferred embodiment of the present invention
- FIGS. 6A - 6 E illustrate in detail the process steps for performing the bottom electrode patterning process step shown in FIG. 5D.
- FIGS. 7A - 7 C illustrate further embodiments of a capacitor in a semiconductor device according to the present invention.
- FIG. 4 illustrates a cross-section of a partially formed capacitor in a semiconductor device in accordance with a preferred embodiment of the present invention.
- an interlayer insulation layer 41 is formed on a semiconductor substrate 40 , and has a contact hole formed therein.
- the semiconductor substrate 40 will already have cell transistors and the like formed thereon.
- a plug 42 fills the contact hole, and a first bottom electrode 43 a is formed on a portion of the interlayer insulation layer 41 and the plug 42 .
- the plug 42 is formed of polysilicon, tungsten or Pt, and the first bottom electrode 43 a is formed of a metal, the oxide of which is conductive, or the oxide of the metal.
- An oxygen diffusion barrier 44 a is formed on the first bottom electrode 43 a , and a second bottom electrode 43 b is formed on the oxygen diffusion barrier 44 a .
- the oxygen diffusion barrier 44 a is silicon oxide or silicon nitride and the second bottom electrode 43 b is formed of Pt to a thickness of 10 nm + ⁇ 5%.
- the first bottom electrode 43 a , the oxygen diffusion barrier 44 a and the second bottom electrode 43 b form a bottom electrode pattern.
- a third bottom electrode 43 c is formed as sidewalls of the bottom electrode pattern.
- the height of the third bottom electrode 43 c is greater than the height of the bottom electrode pattern, and the third bottom electrode 43 c is formed of Pt.
- a dielectric layer 45 is formed over the resulting structure, and an upper electrode (not shown) is formed thereon.
- the dielectric layer 45 is a high dielectric constant dielectric such as BST or PZT.
- FIGS. 5A - 5 F illustrate the process steps of the method for fabricating a semiconductor device having a capacitor with an improved bottom electrode in accordance with a preferred embodiment of the present invention
- FIGS. 6A - 6 E illustrate in detail the process steps for performing the bottom electrode patterning process step shown in FIG. 5D.
- an interlayer insulation layer 41 is formed on a semiconductor substrate 40 , and a portion thereof is selectively removed to form a contact hole therein.
- the semiconductor substrate 40 will typically have cell transistors already formed therein.
- a plug 42 is formed in the contact hole by depositing polysilicon, which has excellent step coverage, and performing etch back or chemical mechanical polishing (CMP) to expose the interlayer insulation layer 41 .
- the plug 42 may be formed of tungsten or Pt.
- a metal film, the oxide of which is conductive, or the oxide of the metal is deposited on a surface of the interlayer insulation layer 41 and the plug 42 to from a first bottom electrode layer 43 a in electrical contact with the semiconductor substrate 40 via the plug 42 .
- the first bottom electrode layer is preferably formed of Ru, Ir, Rh, Os, Sn and the like, or a mixture of these metals.
- an oxygen diffusion barrier 44 a of silicon oxide or silicon nitride is formed on surface of the first bottom electrode layer 43 a .
- a second bottom electrode layer 43 b of Pt is formed on the oxygen diffusion barrier 44 a .
- the second bottom electrode layer 43 b is deposited to a thickness of 10 nm + ⁇ 5% so that the Pt film can be etched in a following patterning process without leaving any residue.
- a patterning process is carried out to form the bottom electrode pattern shown in FIG. 5D. This patterning process will be described in detail with respect to FIGS. 6 A- 6 E.
- a photoresist layer 60 is deposited and patterned by lithography.
- the patterned photoresist layer 60 is used as a mask to etch the silicon oxide film 44 b using a gas, such as CHF 3 , CF 4 , C 2 F 6 , C 2 HF 5 , Ar, or Cl 2 .
- the second bottom electrode layer 43 b is etched by sputtering. This etching process also results in the oxygen diffusion layer 44 a being partially etched.
- the second bottom electrode layer 43 b is formed to a thickness of 10 nm + ⁇ 5%, no residue from this etching step remains.
- the oxygen diffusion barrier 44 a is etched using a gas, such as CHF 3 , CF 4 , C 2 F 6 , C 2 HF 5 , Ar, or Cl 2 .
- a gas such as CHF 3 , CF 4 , C 2 F 6 , C 2 HF 5 , Ar, or Cl 2 .
- the photoresist layer 60 is removed, and as shown in FIG. 6E, O 2 plasma is used to etch the first bottom electrode layer 43 a and produce the bottom electrode pattern of FIG. 5D.
- the O 2 plasma etching results in the interlayer insulation layer 41 being partially etched as well.
- a Pt film is CVD or sputter deposited over the entire surface of the semiconductor substrate 40 and etched back to from a third bottom electrode 43 c .
- the etch back leaves Pt film only at the sides of the bottom electrode pattern (i.e., the patterned silicon oxide film 44 b , the second bottom electrode layer 43 b , the oxygen diffusion barrier layer 44 a , and the first bottom electrode layer 43 a ).
- the height of the third bottom electrode 43 c is greater than the height of the bottom electrode pattern. Forming the third bottom electrode 43 c to such a height increases the effective surface area thereof.
- the total surface area of the third bottom electrode 43 c is increased by the amount the interlayer insulation layer 41 was etched. Increasing the total surface area of the third bottom electrode 43 a increases an effective area of the resulting capacitor; and therefore, increases the amount of charge the capacitor can store.
- a heat treatment may be conducted in an oxygen ambient atmosphere to form an RuOx film between the third bottom electrode 43 c and the first bottom electrode 43 a .
- the silicon oxide film 44 b is removed and a dielectric film 45 is deposited.
- the dielectric film 45 is chemical vapor deposited to provide good step coverage.
- the dielectric film 45 may be formed of any high dielectric constant dielectric such as BST and PZT.
- FIGS. 7A - 7 C illustrate cross-sections of partially formed capacitors in accordance with further embodiments of the present invention.
- the capacitor of FIG. 7A has the same structure as the capacitor of FIG. 4, except that the plug 42 only partially fills the contact hole in the interlayer insulation layer 41 .
- the remaining portion of the contact hole is filled with another oxygen diffusion barrier 46 .
- this oxygen diffusion barrier 46 is formed from one of TiN, TiW, TaN, and TiAIN.
- the capacitor of FIG. 7B also has the same structure as the capacitor of FIG. 4, except that another oxygen diffusion barrier 48 is disposed between (1) the first bottom electrode 43 a and (2) the plug 42 and a portion of the interlayer insulation layer 41 .
- this oxygen diffusion barrier 48 is formed from one of TiN, TiW, TaN, and TiAlN.
- FIG. 7C illustrates a bottom electrode pattern the same as in FIG. 5D except that (1) a first adhesive 47 a is disposed between the first bottom electrode 43 a and the oxygen diffusion barrier 44 a , (2) a second adhesive 47 b is disposed between the oxygen diffusion barrier 44 b and the second bottom electrode 43 b , and (3) a third adhesive 47 c is disposed between the second bottom electrode 43 b and the silicon oxide layer 44 b .
- Each of the first, second, and third adhesive layers 47 a , 47 b , and 47 c is formed from Ti or Ta.
- the bottom electrode of a capacitor of the present invention it is possible to differ a thickness of each layer to adjust contact resistance and the capacitor s effective area. Furthermore, an electrode layer of Pt film is formed in direct contact with the dielectric film having a high dielectric constant, and oxidation of the plug caused by oxygen diffusion due to the Pt film is inhibited. Namely, an oxygen diffusion barrier is provided in the bottom electrode for preventing oxygen diffusion from occurring during the dielectric film forming process, and the first bottom electrode is formed of a material, the oxide of which is conductive, to prevent lateral diffusion of oxygen through the Pt film during the dielectric film forming process.
- the present invention further has the following advantages: first, the use of Pt, which has a great work function, as an electrode material in direct contact with the dielectric film improves electrical performances of the device; second, the inhibition of residue production in Pt film patterning and the use of a simple etch back process can simplify the fabrication process; third, the prevention of oxygen diffusion by the oxygen diffusion barrier and the first bottom electrode during the formation of the dielectric film, which prevents oxidation of the plug layer, improves device performance; and fourth, by minimizing a contact area between a Pt film and a Ru film, and as RuOx film is formed by the oxygen diffused through the Pt film, degradation of the capacitor during formation of the dielectric film can be prevented.
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Abstract
A method for fabricating a bottom electrode structure for a semiconductor capacitor. The method according to the present invention includes providing an interlayer insulating layer having a conductive plug formed therein. A first bottom electrode layer is formed on the interlayer insulating layer. An oxygen diffusion barrier layer is formed on the first bottom electrode layer. A second bottom electrode layer is formed on the first oxygen diffusion barrier layer. Thereafter, portions of the second bottom electrode layer, first oxygen diffusion barrier layer, and first bottom electrode layer are selectively removed to form a bottom electrode pattern. A third bottom electrode is formed on side walls of the bottom electrode pattern.
Description
- 1. Field of the Invention
- The present invention relates to a memory device with a high device packing density, and more particularly, a semiconductor device including a capacitor with an improved bottom electrode and a method for fabricating the same.
- 2. Description of Related Art
- In general, a semiconductor memory device is provided with a driving transistor and a capacitor which stores information therein. A volatile memory device, such as a dynamic random access memory (DRAM), stores information as an amount of charge in the capacitor. The amount of charge stored in the memory device, such as a DRAM, can be increased as follows: fabricating a three dimensional capacitor to increase an effective area of the capacitor; reducing a thickness of a dielectric in the capacitor; and using a dielectric having a higher dielectric constant.
- Because increasing the stored charge by increasing the surface area and reducing the thickness of the dielectric requires complicated fabrication process steps, these techniques for increasing the stored charge are not generally adopted. Instead, the stored charge is increased by using high dielectric constant dielectric films. As the high dielectric constant dielectric films, (Ba, Sr)TiO3 and (Pb, La)(Zr,Ti)O3 may be used. The high dielectric constant dielectric films BST[(Ba, Sr)TiO3] are mostly used in DRAMs, and the high dielectric constant dielectric films PZT(PbZrTiO3) are mostly used in flash random access memories (FRAMs). If a high dielectric constant dielectric film such as BST is deposited on a silicon substrate directly, the silicon oxidizes making a defective contact or the BST film degrades due to a reaction between BST and Si. Because of this, when high dielectric constant dielectric films such as BST are used as the dielectric of a capacitor, a metal film such as Pt, Ru and Ir, which is less reactive, is usually used as the bottom electrode of the capacitor. This is applicable to both DRAMs and FRAMs. Because a complicated three dimensional electrode is not required for increasing an effective area of the capacitor if a high dielectric constant dielectric film such as BST or PZT is used, a memory device having a device packing density greater than the giga class can be fabricated according to the simple structure shown in FIG. 1.
- As shown in FIG. 1, an
interlayer insulation layer 2 is formed on asubstrate 1, and has a contact hole formed therein. Aplug 3 fills the contact hole, and abarrier 4 is formed on thesubstrate 1 and theplug 3. Abottom electrode 5 is formed on thebarrier 4, and a dielectric 6 covers theinterlayer insulation layer 2, thebottom electrode 5 and thebarrier layer 4. A top electrode (not shown) is then formed on the dielectric 6. - When PZT or BST is used as the
dielectric film 6, one of Pt, Ru and Ir is used as thebottom electrode 5. However, when Pt or Ru is used as thebottom electrode 5, the electrical characteristics of the capacitor change. - FIG. 2A illustrates the use of Pt as the
bottom electrode 5. Pt has a great work function, which results in excellent electrical characteristics and reduced leakage current, but Pt is oxygen permeable. As a result, oxidation at thebarrier 4 andplug 3 interface takes place to form anoxide layer 7. Typically this oxidation consumes thebarrier 4. The oxygen diffuses mostly along the Pt grain boundaries during the formation of the dielectric 6 causing oxygen holes in the dielectric 6, which degrades the electrical characteristics thereof. - FIG. 2B illustrate the use of Ru as the
bottom electrode 5. When the dielectric film is deposited, oxygen is absorbed from the dielectric 6 by thebottom electrode 5 as thebottom electrode 5 oxidizes. This forms an oxygen depletion layer between the dielectric 6 and thebottom electrode 5 resulting in poor electrical performance. To prevent this, thebottom electrode 5 is usually oxidized prior to deposition of the dielectric 6 so that the oxide layer formed therein prevents further oxidation using the oxygen in the dielectric 6. Typically, theRu bottom electrode 5 is formed through etching with oxygen to form anoxide layer 9, RuOx, at the surface of theRu bottom electrode 5 as shown in FIG. 2B. Besides preventing the absorption of oxygen from the dielectric 6, the oxide of Ru, conducts. But the oxide of Ru also forms a rugged deposition surface as shown in FIG. 2B. Because of this rugged surface, theoxide layer 9 has poor electrical characteristics. - One object of the present invention is to provide a semiconductor device including a capacitor with an improved bottom electrode that overcomes the disadvantages and problems noted above with respect to the conventional art.
- Another object of the present invention is to provide a semiconductor device including a capacitor with an improved bottom electrode and therefore improved electrical characteristics.
- These and other objects are achieved by providing a semiconductor device having a capacitor with a bottom electrode, comprising: a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the contact hole; a first bottom electrode formed on a portion of the interlayer insulating layer and over the contact hole; a first oxygen diffusion barrier formed on the first bottom electrode; a second bottom electrode formed on the first oxygen diffusion barrier; and a third bottom electrode formed on sidewalls of the first bottom electrode, the first oxygen diffusion barrier and the second bottom electrode.
- These and other objects are also achieved by providing a method of forming a semiconductor device having a capacitor with a bottom electrode, comprising: providing a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the hole; forming a first bottom electrode layer on the interlayer insulating layer over the hole; forming a first oxygen diffusion barrier layer on the first bottom electrode layer; forming a second bottom electrode layer on the first oxygen diffusion barrier layer; selectively removing portions of the second bottom electrode layer, the oxygen diffusion barrier layer and the first bottom electrode layer to form a bottom electrode pattern; and forming a third bottom electrode on sidewalls of the bottom electrode pattern.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention:
- In the drawings:
- FIG. 1 illustrates a cross-section of a partially formed conventional capacitor in a semiconductor device;
- FIGS. 2A and 2B illustrate cross-sections of the conventional art capacitor using Pt as the bottom electrode;
- FIG. 3 illustrates a cross-section of the conventional art capacitor using Ru as the bottom electrode;
- FIG. 4 illustrates a cross-section of a partially formed capacitor in a semiconductor device in accordance with a preferred embodiment of the present invention;
- FIGS. 5A -5F illustrate the process steps of the method for fabricating a semiconductor device having a capacitor with an improved bottom electrode in accordance with a preferred embodiment of the present invention;
- FIGS. 6A -6E illustrate in detail the process steps for performing the bottom electrode patterning process step shown in FIG. 5D; and
- FIGS. 7A -7C illustrate further embodiments of a capacitor in a semiconductor device according to the present invention.
- Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. FIG. 4 illustrates a cross-section of a partially formed capacitor in a semiconductor device in accordance with a preferred embodiment of the present invention.
- As shown in FIG. 4, an
interlayer insulation layer 41 is formed on asemiconductor substrate 40, and has a contact hole formed therein. Typically, thesemiconductor substrate 40 will already have cell transistors and the like formed thereon. Aplug 42 fills the contact hole, and a firstbottom electrode 43 a is formed on a portion of theinterlayer insulation layer 41 and theplug 42. Preferably, theplug 42 is formed of polysilicon, tungsten or Pt, and the firstbottom electrode 43 a is formed of a metal, the oxide of which is conductive, or the oxide of the metal. - An
oxygen diffusion barrier 44 a is formed on the firstbottom electrode 43 a, and a secondbottom electrode 43 b is formed on theoxygen diffusion barrier 44 a. Preferably, theoxygen diffusion barrier 44 a is silicon oxide or silicon nitride and thesecond bottom electrode 43 b is formed of Pt to a thickness of 10 nm +−5%. The firstbottom electrode 43 a, theoxygen diffusion barrier 44 a and thesecond bottom electrode 43 b form a bottom electrode pattern. - A third
bottom electrode 43 c is formed as sidewalls of the bottom electrode pattern. Preferably the height of the thirdbottom electrode 43 c is greater than the height of the bottom electrode pattern, and the thirdbottom electrode 43 c is formed of Pt. Adielectric layer 45 is formed over the resulting structure, and an upper electrode (not shown) is formed thereon. Preferably, thedielectric layer 45 is a high dielectric constant dielectric such as BST or PZT. - The method for fabricating a semiconductor device having a capacitor with the improved bottom electrode of FIG. 4 will be described with reference to FIGS. 5A -5F and 6A - 6E. FIGS. 5A - 5F illustrate the process steps of the method for fabricating a semiconductor device having a capacitor with an improved bottom electrode in accordance with a preferred embodiment of the present invention, and FIGS. 6A - 6E illustrate in detail the process steps for performing the bottom electrode patterning process step shown in FIG. 5D.
- Referring to FIG. 5A, an
interlayer insulation layer 41 is formed on asemiconductor substrate 40, and a portion thereof is selectively removed to form a contact hole therein. At this point in the process, thesemiconductor substrate 40 will typically have cell transistors already formed therein. - Then, as shown in FIG. 5B, a
plug 42 is formed in the contact hole by depositing polysilicon, which has excellent step coverage, and performing etch back or chemical mechanical polishing (CMP) to expose theinterlayer insulation layer 41. Instead of polysilicon, theplug 42 may be formed of tungsten or Pt. - Next, as shown in FIG. 5C, a metal film, the oxide of which is conductive, or the oxide of the metal is deposited on a surface of the
interlayer insulation layer 41 and theplug 42 to from a firstbottom electrode layer 43 a in electrical contact with thesemiconductor substrate 40 via theplug 42. The first bottom electrode layer is preferably formed of Ru, Ir, Rh, Os, Sn and the like, or a mixture of these metals. Then anoxygen diffusion barrier 44 a of silicon oxide or silicon nitride is formed on surface of the firstbottom electrode layer 43 a. A secondbottom electrode layer 43 b of Pt is formed on theoxygen diffusion barrier 44 a. The secondbottom electrode layer 43 b is deposited to a thickness of 10 nm +−5% so that the Pt film can be etched in a following patterning process without leaving any residue. Asilicon oxide film 44 b, serving as a buffer layer, is formed on the secondbottom electrode layer 43 b. - A patterning process is carried out to form the bottom electrode pattern shown in FIG. 5D. This patterning process will be described in detail with respect to FIGS.6A-6E. As shown in 6A, a
photoresist layer 60 is deposited and patterned by lithography. The patternedphotoresist layer 60 is used as a mask to etch thesilicon oxide film 44 b using a gas, such as CHF3, CF4, C2F6, C2HF5, Ar, or Cl2. Then, as shown in FIG. 6B, the secondbottom electrode layer 43 b is etched by sputtering. This etching process also results in theoxygen diffusion layer 44 a being partially etched. As the secondbottom electrode layer 43 b is formed to a thickness of 10 nm +−5%, no residue from this etching step remains. - As shown in FIG. 6C, the
oxygen diffusion barrier 44 a is etched using a gas, such as CHF3, CF4, C2F6, C2HF5, Ar, or Cl2. Then, as shown in FIG. 6D, thephotoresist layer 60 is removed, and as shown in FIG. 6E, O2 plasma is used to etch the firstbottom electrode layer 43 a and produce the bottom electrode pattern of FIG. 5D. The O2 plasma etching results in theinterlayer insulation layer 41 being partially etched as well. - Referring to FIG. 5E, a Pt film is CVD or sputter deposited over the entire surface of the
semiconductor substrate 40 and etched back to from a thirdbottom electrode 43 c. The etch back leaves Pt film only at the sides of the bottom electrode pattern (i.e., the patternedsilicon oxide film 44 b, the secondbottom electrode layer 43 b, the oxygendiffusion barrier layer 44 a, and the firstbottom electrode layer 43 a). As shown, the height of the thirdbottom electrode 43 c is greater than the height of the bottom electrode pattern. Forming the thirdbottom electrode 43 c to such a height increases the effective surface area thereof. Additionally, the total surface area of the thirdbottom electrode 43 c is increased by the amount theinterlayer insulation layer 41 was etched. Increasing the total surface area of the thirdbottom electrode 43 a increases an effective area of the resulting capacitor; and therefore, increases the amount of charge the capacitor can store. - Optionally, after forming the third
bottom electrode 43 a, a heat treatment may be conducted in an oxygen ambient atmosphere to form an RuOx film between the thirdbottom electrode 43 c and the firstbottom electrode 43 a. Then, as shown in FIG. 5F, thesilicon oxide film 44 b is removed and adielectric film 45 is deposited. Thedielectric film 45 is chemical vapor deposited to provide good step coverage. Thedielectric film 45 may be formed of any high dielectric constant dielectric such as BST and PZT. - From the forgoing description, it will be recognized that the method according to the present invention is not limited to forming the bottom electrode of a capacitor as described above. Instead, various modifications to further improve the electrical characteristics thereof can be made. For example, FIGS. 7A -7C illustrate cross-sections of partially formed capacitors in accordance with further embodiments of the present invention.
- The capacitor of FIG. 7A has the same structure as the capacitor of FIG. 4, except that the
plug 42 only partially fills the contact hole in theinterlayer insulation layer 41. The remaining portion of the contact hole is filled with anotheroxygen diffusion barrier 46. Preferably, thisoxygen diffusion barrier 46 is formed from one of TiN, TiW, TaN, and TiAIN. - The capacitor of FIG. 7B also has the same structure as the capacitor of FIG. 4, except that another oxygen diffusion barrier48 is disposed between (1) the first
bottom electrode 43 a and (2) theplug 42 and a portion of theinterlayer insulation layer 41. Preferably, this oxygen diffusion barrier 48 is formed from one of TiN, TiW, TaN, and TiAlN. - FIG. 7C illustrates a bottom electrode pattern the same as in FIG. 5D except that (1) a first adhesive47 a is disposed between the first
bottom electrode 43 a and theoxygen diffusion barrier 44 a, (2) a second adhesive 47 b is disposed between theoxygen diffusion barrier 44 b and thesecond bottom electrode 43 b, and (3) a third adhesive 47 c is disposed between thesecond bottom electrode 43 b and thesilicon oxide layer 44 b. Each of the first, second, and thirdadhesive layers - In the bottom electrode of a capacitor of the present invention, it is possible to differ a thickness of each layer to adjust contact resistance and the capacitor s effective area. Furthermore, an electrode layer of Pt film is formed in direct contact with the dielectric film having a high dielectric constant, and oxidation of the plug caused by oxygen diffusion due to the Pt film is inhibited. Namely, an oxygen diffusion barrier is provided in the bottom electrode for preventing oxygen diffusion from occurring during the dielectric film forming process, and the first bottom electrode is formed of a material, the oxide of which is conductive, to prevent lateral diffusion of oxygen through the Pt film during the dielectric film forming process.
- The present invention further has the following advantages: first, the use of Pt, which has a great work function, as an electrode material in direct contact with the dielectric film improves electrical performances of the device; second, the inhibition of residue production in Pt film patterning and the use of a simple etch back process can simplify the fabrication process; third, the prevention of oxygen diffusion by the oxygen diffusion barrier and the first bottom electrode during the formation of the dielectric film, which prevents oxidation of the plug layer, improves device performance; and fourth, by minimizing a contact area between a Pt film and a Ru film, and as RuOx film is formed by the oxygen diffused through the Pt film, degradation of the capacitor during formation of the dielectric film can be prevented.
- It will be apparent to those skilled in the art that various modifications and variations of the present invention can be made without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (33)
1. A semiconductor device having a capacitor with a bottom electrode, comprising:
a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the hole contact;
a first bottom electrode formed on the interlayer insulating layer over the contact hole;
a first oxygen diffusion barrier formed on the first bottom electrode;
a second bottom electrode formed on the first oxygen diffusion barrier; and
a third bottom electrode formed on sidewalls of the first bottom electrode, the first oxygen diffusion barrier and the second bottom electrode.
2. The semiconductor device of , wherein the first bottom electrode is formed of a material which conducts as an oxide.
claim 1
3. The semiconductor device of , wherein the first bottom electrode is form from one of Ru, Ir, Rh, Os, Sn, and a mixture thereof.
claim 2
4. The semiconductor device of , wherein the first bottom electrode is formed of a first material having a first work function, the second bottom electrode is formed of a second material having a second work function, and the second work function is greater than the first work function.
claim 1
5. The semiconductor device of , wherein the third bottom electrode has a height which greater than a combined height of the first bottom electrode, the first oxygen diffusion barrier and the second bottom electrode.
claim 1
6. The semiconductor device of , wherein the second bottom electrode has a thickness of 10 nm +−5%.
claim 1
7. The semiconductor device of , wherein the first bottom electrode, the first oxygen diffusion barrier, and the second bottom electrode have a same bottom surface area.
claim 1
8. The semiconductor device of , wherein
claim 1
the first bottom electrode is formed of a material which conducts as an oxide;
the first bottom electrode is formed of a first material having a first work function, the second bottom electrode is formed of a second material having a second work function, and the second work function is greater than the first work function; and
the third bottom electrode has a height which greater than a combined height of the first bottom electrode, the first oxygen diffusion barrier and the second bottom electrode.
9. The semiconductor device of , wherein the first oxygen diffusion barrier is formed from one of silicon oxide and silicon nitride.
claim 1
10. The semiconductor device of , wherein the second bottom electrode is formed of Pt.
claim 1
11. The semiconductor device of , wherein the third bottom electrode is formed of Pt.
claim 1
12. The semiconductor device of , further comprising:
claim 1
a second oxygen barrier layer formed between the plug and the first bottom electrode.
13. The semiconductor device of , wherein the second oxygen diffusion barrier is formed from one of TiN, TiW, TaN and TiAIN.
claim 12
14. The semiconductor device of , wherein the second oxygen diffusion barrier is formed in the contact hole in the interlayer insulating layer.
claim 12
15. The semiconductor device of , further comprising:
claim 1
a first adhesive between the first bottom electrode and the first oxygen diffusion barrier; and
a second adhesive between the first oxygen diffusion barrier and the second bottom electrode.
16. The semiconductor device of , further comprising:
claim 1
a dielectric film formed on the third bottom electrode, the second bottom electrode and at least a portion of the interlayer insulating layer.
17. A method of forming a semiconductor device having a capacitor with a bottom electrode, comprising:
providing a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the contact hole;
forming a first bottom electrode layer on the interlayer insulating layer over the contact hole;
forming a first oxygen diffusion barrier layer on the first bottom electrode layer;
forming a second bottom electrode layer on the first oxygen diffusion barrier layer;
selectively removing portions of the second bottom electrode layer, the oxygen diffusion barrier layer and the first bottom electrode layer to form a bottom electrode pattern; and
forming a third bottom electrode on sidewalls of the bottom electrode pattern.
18. The method of , wherein the first bottom electrode layer is formed of a material which conducts as an oxide.
claim 17
19. The capacitor of , wherein the first bottom electrode layer is form from one of Ru, Ir, Rh, Os, Sn, and a mixture thereof.
claim 18
20. The capacitor of , wherein the first bottom electrode layer is formed of a first material having a first work function, the second bottom electrode is formed of a second material having a second work function, and the second work function is greater than the first work function.
claim 16
21. The capacitor of , wherein forming a third bottom electrode step forms the third bottom electrode to a height which is greater than a height of the bottom electrode pattern.
claim 16
22. The capacitor of , wherein the forming a third bottom electrode step comprises:
claim 16
forming a third bottom electrode layer over the substrate and the bottom electrode pattern; and
etching back the third bottom electrode layer.
23. The method of , wherein forming a second electrode layer step forms the second bottom electrode to a thickness of 10 nm +−5%.
claim 16
24. The method of , wherein
claim 16
the first bottom electrode layer is formed of a material which conducts as an oxide;
the first bottom electrode layer is formed of a first material having a first work function, the second bottom electrode layer is formed of a second material having a second work function, and the second work function is greater than the first work function; and
the forming a third bottom electrode layer step forms the third bottom electrode to a height which is greater than a height of the bottom electrode pattern.
25. The method of , wherein the first oxygen diffusion barrier layer is formed from one of silicon oxide and silicon nitride.
claim 16
26. The method of , wherein the second bottom electrode is formed of Pt.
claim 16
27. The method of , wherein the third bottom electrode is formed of Pt.
claim 16
28. The method of , further comprising:
claim 16
forming a second oxygen barrier layer between the plug layer and the first bottom electrode layer.
29. The method of , wherein the second oxygen diffusion barrier layer is formed from one of TiN, TiW, TaN and TiAIN.
claim 28
30. The method of , wherein the second oxygen diffusion barrier layer is formed in the hole in the interlayer insulating layer.
claim 28
31. The method of , further comprising:
claim 16
forming a first adhesive on the first bottom electrode layer prior to forming the first oxygen diffusion barrier layer; and
forming a second adhesive the first oxygen diffusion barrier layer prior to forming the second bottom electrode layer.
32. The method of , further comprising:
claim 16
heat treating the substrate in an oxygen ambient atmosphere prior to forming the third bottom electrode layer.
33. The method of , wherein the removing step comprises:
claim 16
forming a buffer layer on the second electrode layer;
forming a photoresist pattern on the buffer layer;
etching the buffer layer and the second electrode layer using the photoresist pattern as a mask;
removing the photoresist pattern;
etching the oxygen diffusion barrier layer and the first electrode layer using a remaining portion of the buffer layer as a mask; and
removing the remaining portion of the buffer layer.
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US09/794,143 US6396097B2 (en) | 1998-06-30 | 2001-02-28 | Semiconductor device including capacitor with improved bottom electrode |
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KR1019980025918A KR100290895B1 (en) | 1998-06-30 | 1998-06-30 | Capacitor structure of semiconductor device and manufacturing method thereof |
KR98-25918 | 1998-06-30 | ||
KR25918/1998 | 1998-06-30 | ||
US09/191,374 US6218258B1 (en) | 1998-06-30 | 1998-11-13 | Method for fabricating semiconductor device including capacitor with improved bottom electrode |
US09/794,143 US6396097B2 (en) | 1998-06-30 | 2001-02-28 | Semiconductor device including capacitor with improved bottom electrode |
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US09/794,143 Expired - Lifetime US6396097B2 (en) | 1998-06-30 | 2001-02-28 | Semiconductor device including capacitor with improved bottom electrode |
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US6075264A (en) * | 1999-01-25 | 2000-06-13 | Samsung Electronics Co., Ltd. | Structure of a ferroelectric memory cell and method of fabricating it |
US6387748B1 (en) | 1999-02-16 | 2002-05-14 | Micron Technology, Inc. | Semiconductor circuit constructions, capacitor constructions, and methods of forming semiconductor circuit constructions and capacitor constructions |
US6407004B1 (en) * | 1999-05-12 | 2002-06-18 | Matsushita Electric Industrial Co., Ltd. | Thin film device and method for manufacturing thin film device |
US6635528B2 (en) * | 1999-12-22 | 2003-10-21 | Texas Instruments Incorporated | Method of planarizing a conductive plug situated under a ferroelectric capacitor |
KR100587046B1 (en) * | 2000-05-31 | 2006-06-07 | 주식회사 하이닉스반도체 | Method of manufacturing stroage electrode |
US6583460B1 (en) * | 2000-08-29 | 2003-06-24 | Micron Technology, Inc. | Method of forming a metal to polysilicon contact in oxygen environment |
US6297123B1 (en) * | 2000-11-29 | 2001-10-02 | United Microelectronics Corp. | Method of preventing neck oxidation of a storage node |
KR100410716B1 (en) * | 2001-03-07 | 2003-12-18 | 주식회사 하이닉스반도체 | FeRAM capable of connecting bottom electrode to storage node and method for forming the same |
KR100423906B1 (en) * | 2001-08-08 | 2004-03-22 | 삼성전자주식회사 | Ferroelectric memory device amd method of forming the same |
US7373026B2 (en) * | 2004-09-27 | 2008-05-13 | Idc, Llc | MEMS device fabricated on a pre-patterned substrate |
US7630114B2 (en) * | 2005-10-28 | 2009-12-08 | Idc, Llc | Diffusion barrier layer for MEMS devices |
US7560392B2 (en) | 2006-05-10 | 2009-07-14 | Micron Technology, Inc. | Electrical components for microelectronic devices and methods of forming the same |
US7733552B2 (en) | 2007-03-21 | 2010-06-08 | Qualcomm Mems Technologies, Inc | MEMS cavity-coating layers and methods |
US7719752B2 (en) | 2007-05-11 | 2010-05-18 | Qualcomm Mems Technologies, Inc. | MEMS structures, methods of fabricating MEMS components on separate substrates and assembly of same |
US20100288346A1 (en) * | 2009-04-29 | 2010-11-18 | Gobi Ramakrishnan Padmanabhan | Configurations and methods to manufacture solar cell device with larger capture cross section and higher optical utilization efficiency |
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US5191510A (en) | 1992-04-29 | 1993-03-02 | Ramtron International Corporation | Use of palladium as an adhesion layer and as an electrode in ferroelectric memory devices |
US5566045A (en) | 1994-08-01 | 1996-10-15 | Texas Instruments, Inc. | High-dielectric-constant material electrodes comprising thin platinum layers |
US5555486A (en) | 1994-12-29 | 1996-09-10 | North Carolina State University | Hybrid metal/metal oxide electrodes for ferroelectric capacitors |
US5654222A (en) * | 1995-05-17 | 1997-08-05 | Micron Technology, Inc. | Method for forming a capacitor with electrically interconnected construction |
US5663088A (en) * | 1995-05-19 | 1997-09-02 | Micron Technology, Inc. | Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer |
KR100189982B1 (en) * | 1995-11-29 | 1999-06-01 | 윤종용 | High dielectric capacitor fabrication method of semiconductor device |
US5914851A (en) * | 1995-12-22 | 1999-06-22 | International Business Machines Corporation | Isolated sidewall capacitor |
US5825609A (en) * | 1996-04-23 | 1998-10-20 | International Business Machines Corporation | Compound electrode stack capacitor |
KR100226772B1 (en) * | 1996-09-25 | 1999-10-15 | 김영환 | Semiconductor memory device and fabricating method thereof |
KR100239418B1 (en) * | 1996-12-03 | 2000-01-15 | 김영환 | Semiconductor device capacitor and manufacturing method thereof |
KR100243285B1 (en) * | 1997-02-27 | 2000-02-01 | 윤종용 | High-dielectric capacitor and manufacturing method thereof |
US6020233A (en) * | 1997-06-30 | 2000-02-01 | Hyundai Electronics Industries Co., Ltd. | Ferroelectric memory device guaranteeing electrical interconnection between lower capacitor electrode and contact plug and method for fabricating the same |
JP3319994B2 (en) * | 1997-09-29 | 2002-09-03 | シャープ株式会社 | Semiconductor storage element |
US5985731A (en) * | 1998-08-17 | 1999-11-16 | Motorola, Inc. | Method for forming a semiconductor device having a capacitor structure |
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1998
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US6218258B1 (en) | 2001-04-17 |
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KR100290895B1 (en) | 2001-07-12 |
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