US20010010394A1 - Semiconductor package - Google Patents
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- US20010010394A1 US20010010394A1 US09/767,720 US76772001A US2001010394A1 US 20010010394 A1 US20010010394 A1 US 20010010394A1 US 76772001 A US76772001 A US 76772001A US 2001010394 A1 US2001010394 A1 US 2001010394A1
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- bonding wire
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Definitions
- the present invention relates to a resin encapsulated semiconductor package using a lead frame.
- a lead frame of a resin encapsulated semiconductor package uses a 42 Ni-Fe alloy or a copper alloy.
- quad flat packages such as application specific integrated circuits (ASIC) and microcomputers entail large power dissipation and so use a lead frame of a copper alloy.
- Thin small outline packages (TSOP) mounting thereon memory devices such as a dynamic random access memory (DRAM), a static random access memory (SRAM) or the like, which are large in generation of heat and size are mounted, use a 42 Ni-Fe alloy.
- a quad flat nonleaded package (QFN), a SOP and a QFP which mount thereon an IC for electric power, generally uses a lead frame formed of a copper alloy.
- Linear expansion coefficients of parts constituting a resin encapsulated semiconductor package are significantly different from one another such that a copper alloy used as a frame material has a linear expansion coefficient of 17 ⁇ 10 ⁇ 6 /° C., a 42 Ni-Fe alloy has a linear expansion coefficient of 4 ⁇ 10 ⁇ 6 to 5 ⁇ 10 ⁇ 6 /° C., silicon as a semiconductor device has a linear expansion coefficient of 3 ⁇ 10 ⁇ 6 /° C., and a molding or encapsulating resin has a linear expansion coefficient of 12 to 25 ⁇ 10 ⁇ 6 /° C.
- thermal stresses generate inside the semiconductor package in a cooling process after a resin molding or encapsulating process, in a temperature cycle test for testing reliability.
- a copper alloy based lead frame has been used which is small in self inductance to be suited to the high frequency operation, and high in heat conducting properties.
- solder fatigue occurs to deteriorate bonding, so that only an epoxy based bonding material (silver paste or the like) having a low Young's modulus has been used.
- CSPs chip scale package
- solder bumps arranged in a matrix configuration.
- CSPs have a large volume ratio of a device in a semiconductor package, and an apparent linear expansion coefficient close to that of the device. Therefore, with packaged substrates of small-sized portable equipments with a large number of CSPs mounted thereon, it has become general to use a low thermal expansion substrate, in which a conventional linear expansion coefficient of 15 to 16 ⁇ 10 ⁇ 6 /° C. is reduced to about half, that is, 8 ⁇ 10 ⁇ 6 /° C.
- An object of the present invention is to solve at least one of the aforementioned problems, and to provide a resin encapsulated semiconductor package, which ensures reliability on strength and has high heat conducting properties.
- the object of the present invention is attained, for example, by constituting a resin encapsulated semiconductor package in the following manner. That is to say, used as a material for a lead frame is a material composed mainly of a composite alloy of Cu 2 O and Cu (having largest contents among materials constituting leads), which is sintered to have a thermal conductivity comparable to that of a copper alloy conventionally used and a smaller linear expansion coefficient than that of the copper alloy.
- a range where physical properties of the Cu/Cu 2 O composite alloy are examined is 20 to 80 vol. % in terms of a compounding ratio of Cu 2 O, and involves 280 to 41 W/(mK) of thermal conductivity and 13.8 to 5.5 ⁇ 10 ⁇ 6 /° C. of linear expansion coefficient.
- the compounding ratio of Cu 2 O suffices to be set to 20 to 46%.
- the linear expansion coefficient of the Cu/Cu 2 O composite alloy amounts to about 13.8 to 10.5 ⁇ 10 ⁇ 6 /° C., and approximates to 3 ⁇ 10 ⁇ 6 /° C. of linear expansion coefficient of a chip as compared with 17 ⁇ 10 ⁇ 6 /° C. of linear expansion coefficient of a copper alloy.
- FIG. 1 is a cross sectional view showing a semiconductor package according to a first embodiment of the present invention, in which a QFN using a Cu/Cu 2 O composite alloy for a lead frame is mounted on a substrate by soldering.
- FIG. 2 is a cross sectional view showing a semiconductor package according to a second embodiment of the present invention, in which a back surface of a tab of a QFN using a Cu/Cu 2 O composite alloy for a lead frame is exposed, and the QFN is mounted on a substrate by soldering.
- FIG. 3 is a cross sectional view showing a semiconductor package according to a third embodiment of the present invention, in which a QFP or a SOP using a Cu/Cu 2 O composite alloy for a lead frame mounted on a substrate by soldering.
- FIG. 4 is a cross sectional view showing a semiconductor package according to a fourth embodiment of the present invention, in which a HQFP or a HSOP includes a lead frame having fused leads using a Cu/Cu 2 O composite alloy.
- FIG. 5 is a cross sectional view showing a semiconductor package according to a fifth embodiment of the present invention, in which a HQFP or a HSOP uses a Cu/Cu 2 O composite alloy for a lead frame and a back surface of a tab is exposed.
- FIG. 6 is a cross sectional view showing a semiconductor package according to a sixth embodiment of the present invention, in which a HQFP or a HSOP uses a Cu/Cu 2 O composite alloy for a lead frame, which has two or more different thicknesses, and a back surface of a tab is exposed.
- FIG. 7 is a cross sectional view showing a semiconductor package according to a seventh embodiment of the present invention, in which a TSOP of LOC structure uses a Cu/Cu 2 O composite alloy for a lead frame.
- FIG. 8 is a cross sectional view showing a semiconductor package according to an eighth embodiment of the present invention, in which two semiconductor devices are mounted in a TSOP of LOC structure using a Cu/Cu 2 O composite alloy for a lead frame.
- FIG. 9 is a graph showing changes in Young's modulus, thermal conductivity, and linear expansion coefficient for a compounding ratio of Cu 2 O in a Cu/Cu 2 O composite alloy in the present invention.
- FIG. 1 A cross sectional view of a semiconductor package according to a first embodiment of the present invention is shown in FIG. 1.
- a semiconductor device 1 is bonded to a tab 3 of a lead frame formed of a Cu/Cu 2 O composite alloy by an attachment material 2 , and electrically connected to leads 6 of the lead frame of the Cu/Cu 2 O composite alloy by lengths of bonding wire 4 .
- the semiconductor device 1 and electric connections are encapsulated by a resin 5 .
- the leads 6 are exposed to a lower surface of the molding or encapsulating resin, and such exposed portions are electrically connected to foot prints 8 of a substrate 9 by solders 7 .
- the tab 3 and leads 6 are portions of the uniformly thick lead frame of the Cu/Cu 2 O composite alloy, but the tab 3 is processed by etching a tab back surface to be made thinner than the leads 6 .
- the substrate is provided with multi-layers of trace, and a surface trace is electrically connected to inner layers or a back surface trace by through holes 10 .
- the present structure is effective in preventing resin crack on the tab back surface.
- Physical property values for compounding ratios of Cu 2 O in Cu/Cu 2 O composite alloy are shown in FIG. 9.
- a lead frame material desirably has a compounding ratio of the Cu/Cu 2 O composite alloy in the range of 20 to 46 vol.
- the semiconductor device 1 is larger than the tab 3 , but may be smaller than the tab 3 .
- FIG. 2 A cross sectional view of a semiconductor package according to a second embodiment is shown in FIG. 2.
- the semiconductor device 1 is bonded to the tab 3 of the lead frame formed of the Cu/Cu 2 O composite alloy by means of the attachment material 2 , and electrically connected to leads 6 of the lead frame of the Cu/Cu 2 O composite alloy by lengths of bonding wire 4 .
- the semiconductor device 1 and electric connections are encapsulated by the resin 5 .
- the leads 6 are electrically connected to foot prints 8 of a substrate 9 by solders 7 .
- the tab 3 and leads 6 constitute one lead frame of the Cu/Cu 2 O composite alloy having a uniform thickness, and a back surface of the tab 3 is exposed to an underside of the molding or encapsulating resin in the same manner as the leads 6 .
- Heat conduction can be enhanced by soldering such back surface of the tab to the substrate 9 .
- a trace, to which the back surface of the tab is soldered, is provided with a thermal via 11 , which promotes heat conduction of inner layers to surface-shaped trace.
- the semiconductor device is firmly fixed to the substrate as shown in FIG. 2, it is difficult to cause deformation of the leads to accommodate thermal stresses generated by temperature cycle. Therefore, in the same manner as the first embodiment, particularly when a substrate of low thermal expansion is used, the use of the Cu/Cu 2 O composite alloy in the lead frame of the present structure is effective in reduction of stresses.
- FIG. 3 A cross sectional view of a semiconductor package according to a third embodiment is shown in FIG. 3.
- the semiconductor device 1 is bonded to the tab 3 of the lead frame formed of the Cu/Cu 2 O composite alloy by means of the attachment material 2 , and electrically connected to leads 6 of the lead frame of the Cu/Cu 2 O composite alloy by lengths of bonding wire 4 .
- the semiconductor device 1 and electric connections are encapsulated by the resin 5 .
- the leads 6 are drawn outside of the resin from the side of the semiconductor device, and external leads are electrically connected to foot prints 8 of the substrate 9 by solders 7 .
- Conventional examples of the semiconductor device according to the third embodiment include a quad flat package (QFP) and a small outline package (SOP), in which a copper alloy is used for a lead frame.
- QFP quad flat package
- SOP small outline package
- ASICs, microcomputerds, or the like, which are relatively large in device area, are mounted on a large-sized QFP having an external shape of 28 mm square.
- a solder of large rigidity cannot be used for the attachment material 2 , and so a soft epoxy based silver paste is used therefor making the sacrifice of heat conducting properties.
- the use of a lead frame material of the Cu/Cu 2 O composite alloy according to the present invention makes attachment by a solder of good thermal conductivity possible, and further enhanced heat conduction of the semiconductor package is enabled.
- FIG. 4 A cross sectional view of a semiconductor package according to a fourth embodiment is shown in FIG. 4.
- the semiconductor device 1 is bonded to the tab 3 of the lead frame formed of the Cu/Cu 2 O composite alloy by means of the attachment material 2 , and electrically connected to leads 6 of the lead frame of the Cu/Cu 2 O composite alloy by lengths of bonding wire 4 .
- the semiconductor device 1 and electric connections are encapsulated by the resin 5 .
- the leads 6 for receiving/transmitting electric signals are electrically insulated from the tab 3 , but the fused leads 12 contiguous to the tab 3 are provided as shown in FIG. 4.
- ICs for electric power do not need a large number of signal pins, and so make much use of QFPs with a heatsink (HQFP) or SOPs with the heatsink (HSOP), which are formed by providing fused leads 12 on QFPs and SOPs. Heat conduction can be further enhanced by soldering the fused leads 12 to the substrate.
- the fused leads 12 have the same width as that of signal leads in some cases, but is formed wide having priority to heat conduction in other cases. In the latter case, the fused leads are firmly soldered to the substrate, so that it is difficult for the fused leads to accommodate thermal deformation, which can lead to breakage of a solder joint. However, the breakage of the solder joint portion can be prevented by using the Cu/Cu 2 O composite alloy for the lead frame of the present structure.
- FIG. 5 A cross sectional view of a semiconductor package according to a fifth embodiment is shown in FIG. 5.
- the semiconductor device 1 is bonded to the tab 3 formed of the Cu/Cu 2 O composite alloy by means of the attachment material 2 , and electrically connected to leads 6 formed of the Cu/Cu 2 O composite alloy by lengths of bonding wire 4 .
- the semiconductor device 1 and electric connections are encapsulated by the resin 5 .
- the tab 3 and leads 6 constitute one lead frame of the Cu/Cu 2 O composite alloy having a uniform thickness, and a back surface of the tab 3 is exposed to an underside of the molding or encapsulating resin.
- the present arrangement has the same effect as described in the second embodiment.
- FIG. 6 A cross sectional view of a semiconductor package according to a sixth embodiment is shown in FIG. 6.
- the semiconductor device 1 is bonded to the tabs 3 of the lead frame formed of the Cu/Cu 2 O composite alloy by means of the attachment material 2 , and electrically connected to leads 6 of the lead frame of the Cu/Cu 2 O composite alloy by lengths of bonding wire 4 .
- the semiconductor device 1 and electric connections are encapsulated by the resin 5 .
- the tab 13 and leads 6 constitute parts of a single sheet of profile lead frame formed of the Cu/Cu 2 O composite alloy and having at least two different kinds of thicknesses, the tab 13 is formed to be thicker than the leads 6 , and the back surface of the tab is exposed to an underside of the molding or encapsulating resin. Enhanced heat conduction can be achieved by soldering the back surface of the tab to the substrate.
- the present arrangement has the same effect as described in the second embodiment.
- FIG. 7 A cross sectional view of a semiconductor package according to a seventh embodiment is shown in FIG. 7.
- the leads 6 of the lead frame formed of the Cu/Cu 2 O composite alloy are bonded to a circuit forming surface of the semiconductor device 1 with an insulating film 14 therebetween, and the leads 6 are electrically connected to the semiconductor device 1 by lengths of bonding wire 4 .
- the semiconductor device 1 and electric connections are encapsulated by the resin 5 .
- the leads 6 are drawn outside of the resin from the side of the semiconductor device.
- the semiconductor package according to the seventh embodiment is a lead on chip (LOC) structure frequently used in memory devices, and is capable of mounting thereon a large device having an outer shape close to that of the resin.
- LOC lead on chip
- FIG. 8 A cross sectional view of a semiconductor package according to an eighth embodiment is shown in FIG. 8.
- Leads 6 a of a lead frame formed of the Cu/Cu 2 O composite alloy are bonded to a circuit forming surface of a semiconductor device 1 a with an insulating film 14 a therebetween, and the leads 6 a are electrically connected to the semiconductor device 1 by lengths of bonding wire 4 a.
- a semiconductor device 1 b, leads 6 b and lengths of bonding wire 4 b, which are constituted in the same manner as that of the above arrangement, is disposed back to back relative to the device 1 a, and these two semiconductor devices and electric connections are encapsulated by the resin 5 .
- the leads 6 b are connected to the leads 6 a, and electrical connection with the substrate is made by the leads 6 a, which are extended and drawn outside of the resin from the semiconductor package.
- the semiconductor package of the present constitution is applied in the case where memory devices are mounted in high density.
- the present constitution has the same effect as described in the seventh embodiment.
- a resin encapsulated semiconductor package in which reliability on strength is ensured and heat conducting properties are high as well.
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Abstract
Description
- i) Field of the Invention
- The present invention relates to a resin encapsulated semiconductor package using a lead frame.
- ii) Description of Related Art
- Conventionally, a lead frame of a resin encapsulated semiconductor package uses a 42 Ni-Fe alloy or a copper alloy.
- For example, quad flat packages (QFP) such as application specific integrated circuits (ASIC) and microcomputers entail large power dissipation and so use a lead frame of a copper alloy. Thin small outline packages (TSOP) mounting thereon memory devices such as a dynamic random access memory (DRAM), a static random access memory (SRAM) or the like, which are large in generation of heat and size are mounted, use a 42 Ni-Fe alloy. Also, a quad flat nonleaded package (QFN), a SOP and a QFP, which mount thereon an IC for electric power, generally uses a lead frame formed of a copper alloy.
- Linear expansion coefficients of parts constituting a resin encapsulated semiconductor package are significantly different from one another such that a copper alloy used as a frame material has a linear expansion coefficient of 17×10−6/° C., a 42 Ni-Fe alloy has a linear expansion coefficient of 4×10−6 to 5×10−6/° C., silicon as a semiconductor device has a linear expansion coefficient of 3×10−6/° C., and a molding or encapsulating resin has a linear expansion coefficient of 12 to 25×10−6/° C. Thus thermal stresses generate inside the semiconductor package in a cooling process after a resin molding or encapsulating process, in a temperature cycle test for testing reliability. In the temperature cycle test, such thermal stresses apply repeatedly to thereby cause fatigue crack in a resin from an end of a die pad or a lead frame, or a bonding wire is sometimes disconnected due to fatigue. Also, the temperature cycle test after packaging of a substrate or repetition of ON/OFF in electronic equipments may cause fatigue failure in solder joints of leads due to differences in linear expansion coefficient between the semiconductor package and the packaged substrate.
- Differences in linear expansion coefficient between a frame material and a semiconductor device are such that a 42 Ni-Fe alloy has a smaller difference and a smaller thermal stress generated than a copper alloy does. Therefore, only replacement into a copper alloy as a lead frame material with a view to enhancement in heat conduction from a semiconductor package will lead to increased thermal stresses and an increased possibility of generation of the above-mentioned fatigue failure, and so making the sacrifice of heat conduction in some measure a conventional 42 Ni-Fe alloy has been recently used in memory TSOPs having an increased heat dissipation and a large chip size. Also, in microcomputers having a relatively large chip size and a high power dissipation and high pin counts QFPs mounting thereon ASICs, a copper alloy based lead frame has been used which is small in self inductance to be suited to the high frequency operation, and high in heat conducting properties. However, when a solder used in small chips and having a large thermal conductivity is used to bond a device to a lead frame, solder fatigue occurs to deteriorate bonding, so that only an epoxy based bonding material (silver paste or the like) having a low Young's modulus has been used.
- In recent small-sized portable electronic equipments, small-sized semiconductor devices have multiplied which are of a structure called a chip scale package (CSP) and adopt electric connection with solder bumps arranged in a matrix configuration. CSPs have a large volume ratio of a device in a semiconductor package, and an apparent linear expansion coefficient close to that of the device. Therefore, with packaged substrates of small-sized portable equipments with a large number of CSPs mounted thereon, it has become general to use a low thermal expansion substrate, in which a conventional linear expansion coefficient of 15 to 16×10−6/° C. is reduced to about half, that is, 8×10−6/° C. However, with resin encapsulated semiconductor devices for mixed loading on a low expansion substrate and making use of a conventional lead frame using a copper alloy, there is a fear of reduction in life of solder joints and generation of resin crack because of an increased difference in linear expansion coefficient between the devices and the substrate.
- An object of the present invention is to solve at least one of the aforementioned problems, and to provide a resin encapsulated semiconductor package, which ensures reliability on strength and has high heat conducting properties.
- The object of the present invention is attained, for example, by constituting a resin encapsulated semiconductor package in the following manner. That is to say, used as a material for a lead frame is a material composed mainly of a composite alloy of Cu2O and Cu (having largest contents among materials constituting leads), which is sintered to have a thermal conductivity comparable to that of a copper alloy conventionally used and a smaller linear expansion coefficient than that of the copper alloy. A range where physical properties of the Cu/Cu2O composite alloy are examined is 20 to 80 vol. % in terms of a compounding ratio of Cu2O, and involves 280 to 41 W/(mK) of thermal conductivity and 13.8 to 5.5×10−6/° C. of linear expansion coefficient. For example, in the case where there is a need of a thermal conductivity of 150 W/(mK) or more comparable to that of a copper alloy used in semiconductor devices with a view to high heat conduction, the compounding ratio of Cu2O suffices to be set to 20 to 46%. In this case, the linear expansion coefficient of the Cu/Cu2O composite alloy amounts to about 13.8 to 10.5×10−6/° C., and approximates to 3×10−6/° C. of linear expansion coefficient of a chip as compared with 17×10−6/° C. of linear expansion coefficient of a copper alloy. However, in the case where there is a need of a linear expansion coefficient of 4 to 5×10−6/° C. comparable to that of 42 alloy for the sake of stress relaxation, making a compounding ratio of Cu2O in the Cu/Cu2O
composite alloy 80% results in 5.5×10−6/° C. of linear expansion coefficient, and 41 W/(mK) of thermal conductivity. Such value is 2.7 times 15 W/(mK) of thermal conductivity of a 42 alloy. In this manner, it suffices to freely adjust the compounding ratio in accordance with an object. - FIG. 1 is a cross sectional view showing a semiconductor package according to a first embodiment of the present invention, in which a QFN using a Cu/Cu2O composite alloy for a lead frame is mounted on a substrate by soldering.
- FIG. 2 is a cross sectional view showing a semiconductor package according to a second embodiment of the present invention, in which a back surface of a tab of a QFN using a Cu/Cu2O composite alloy for a lead frame is exposed, and the QFN is mounted on a substrate by soldering.
- FIG. 3 is a cross sectional view showing a semiconductor package according to a third embodiment of the present invention, in which a QFP or a SOP using a Cu/Cu2O composite alloy for a lead frame mounted on a substrate by soldering.
- FIG. 4 is a cross sectional view showing a semiconductor package according to a fourth embodiment of the present invention, in which a HQFP or a HSOP includes a lead frame having fused leads using a Cu/Cu2O composite alloy.
- FIG. 5 is a cross sectional view showing a semiconductor package according to a fifth embodiment of the present invention, in which a HQFP or a HSOP uses a Cu/Cu2O composite alloy for a lead frame and a back surface of a tab is exposed.
- FIG. 6 is a cross sectional view showing a semiconductor package according to a sixth embodiment of the present invention, in which a HQFP or a HSOP uses a Cu/Cu2O composite alloy for a lead frame, which has two or more different thicknesses, and a back surface of a tab is exposed.
- FIG. 7 is a cross sectional view showing a semiconductor package according to a seventh embodiment of the present invention, in which a TSOP of LOC structure uses a Cu/Cu2O composite alloy for a lead frame.
- FIG. 8 is a cross sectional view showing a semiconductor package according to an eighth embodiment of the present invention, in which two semiconductor devices are mounted in a TSOP of LOC structure using a Cu/Cu2O composite alloy for a lead frame.
- FIG. 9 is a graph showing changes in Young's modulus, thermal conductivity, and linear expansion coefficient for a compounding ratio of Cu2O in a Cu/Cu2O composite alloy in the present invention.
- A cross sectional view of a semiconductor package according to a first embodiment of the present invention is shown in FIG. 1. A
semiconductor device 1 is bonded to atab 3 of a lead frame formed of a Cu/Cu2O composite alloy by anattachment material 2, and electrically connected to leads 6 of the lead frame of the Cu/Cu2O composite alloy by lengths ofbonding wire 4. Thesemiconductor device 1 and electric connections are encapsulated by aresin 5. Theleads 6 are exposed to a lower surface of the molding or encapsulating resin, and such exposed portions are electrically connected tofoot prints 8 of asubstrate 9 bysolders 7. Thetab 3 andleads 6 are portions of the uniformly thick lead frame of the Cu/Cu2O composite alloy, but thetab 3 is processed by etching a tab back surface to be made thinner than theleads 6. The substrate is provided with multi-layers of trace, and a surface trace is electrically connected to inner layers or a back surface trace by throughholes 10. When the package is mounted on a substrate of low thermal expansion, the present structure is effective in preventing resin crack on the tab back surface. Physical property values for compounding ratios of Cu2O in Cu/Cu2O composite alloy are shown in FIG. 9. When making much account of heat conducting properties, a lead frame material desirably has a compounding ratio of the Cu/Cu2O composite alloy in the range of 20 to 46 vol. % in terms of Cu2O compounding ratio, in which thermal conductivity is obtained to be equal to or more than 150 W/(mK) of a conventional copper alloy lead frame. In FIG. 1, thesemiconductor device 1 is larger than thetab 3, but may be smaller than thetab 3. - A cross sectional view of a semiconductor package according to a second embodiment is shown in FIG. 2. The
semiconductor device 1 is bonded to thetab 3 of the lead frame formed of the Cu/Cu2O composite alloy by means of theattachment material 2, and electrically connected to leads 6 of the lead frame of the Cu/Cu2O composite alloy by lengths ofbonding wire 4. Thesemiconductor device 1 and electric connections are encapsulated by theresin 5. Theleads 6 are electrically connected tofoot prints 8 of asubstrate 9 bysolders 7. Thetab 3 and leads 6 constitute one lead frame of the Cu/Cu2O composite alloy having a uniform thickness, and a back surface of thetab 3 is exposed to an underside of the molding or encapsulating resin in the same manner as theleads 6. Heat conduction can be enhanced by soldering such back surface of the tab to thesubstrate 9. A trace, to which the back surface of the tab is soldered, is provided with athermal via 11, which promotes heat conduction of inner layers to surface-shaped trace. In the case where the semiconductor device is firmly fixed to the substrate as shown in FIG. 2, it is difficult to cause deformation of the leads to accommodate thermal stresses generated by temperature cycle. Therefore, in the same manner as the first embodiment, particularly when a substrate of low thermal expansion is used, the use of the Cu/Cu2O composite alloy in the lead frame of the present structure is effective in reduction of stresses. - A cross sectional view of a semiconductor package according to a third embodiment is shown in FIG. 3. The
semiconductor device 1 is bonded to thetab 3 of the lead frame formed of the Cu/Cu2O composite alloy by means of theattachment material 2, and electrically connected to leads 6 of the lead frame of the Cu/Cu2O composite alloy by lengths ofbonding wire 4. Thesemiconductor device 1 and electric connections are encapsulated by theresin 5. Theleads 6 are drawn outside of the resin from the side of the semiconductor device, and external leads are electrically connected tofoot prints 8 of thesubstrate 9 bysolders 7. Conventional examples of the semiconductor device according to the third embodiment include a quad flat package (QFP) and a small outline package (SOP), in which a copper alloy is used for a lead frame. ASICs, microcomputerds, or the like, which are relatively large in device area, are mounted on a large-sized QFP having an external shape of 28 mm square. In this case, a solder of large rigidity cannot be used for theattachment material 2, and so a soft epoxy based silver paste is used therefor making the sacrifice of heat conducting properties. However, the use of a lead frame material of the Cu/Cu2O composite alloy according to the present invention makes attachment by a solder of good thermal conductivity possible, and further enhanced heat conduction of the semiconductor package is enabled. - A cross sectional view of a semiconductor package according to a fourth embodiment is shown in FIG. 4. The
semiconductor device 1 is bonded to thetab 3 of the lead frame formed of the Cu/Cu2O composite alloy by means of theattachment material 2, and electrically connected toleads 6 of the lead frame of the Cu/Cu2O composite alloy by lengths ofbonding wire 4. Thesemiconductor device 1 and electric connections are encapsulated by theresin 5. The leads 6 for receiving/transmitting electric signals are electrically insulated from thetab 3, but the fused leads 12 contiguous to thetab 3 are provided as shown in FIG. 4. Unlike ASICs, microcomputers and so on, ICs for electric power do not need a large number of signal pins, and so make much use of QFPs with a heatsink (HQFP) or SOPs with the heatsink (HSOP), which are formed by providing fused leads 12 on QFPs and SOPs. Heat conduction can be further enhanced by soldering the fused leads 12 to the substrate. The fused leads 12 have the same width as that of signal leads in some cases, but is formed wide having priority to heat conduction in other cases. In the latter case, the fused leads are firmly soldered to the substrate, so that it is difficult for the fused leads to accommodate thermal deformation, which can lead to breakage of a solder joint. However, the breakage of the solder joint portion can be prevented by using the Cu/Cu2O composite alloy for the lead frame of the present structure. - A cross sectional view of a semiconductor package according to a fifth embodiment is shown in FIG. 5. The
semiconductor device 1 is bonded to thetab 3 formed of the Cu/Cu2O composite alloy by means of theattachment material 2, and electrically connected to leads 6 formed of the Cu/Cu2O composite alloy by lengths ofbonding wire 4. Thesemiconductor device 1 and electric connections are encapsulated by theresin 5. Thetab 3 and leads 6 constitute one lead frame of the Cu/Cu2O composite alloy having a uniform thickness, and a back surface of thetab 3 is exposed to an underside of the molding or encapsulating resin. The present arrangement has the same effect as described in the second embodiment. - A cross sectional view of a semiconductor package according to a sixth embodiment is shown in FIG. 6. The
semiconductor device 1 is bonded to thetabs 3 of the lead frame formed of the Cu/Cu2O composite alloy by means of theattachment material 2, and electrically connected toleads 6 of the lead frame of the Cu/Cu2O composite alloy by lengths ofbonding wire 4. Thesemiconductor device 1 and electric connections are encapsulated by theresin 5. Thetab 13 and leads 6 constitute parts of a single sheet of profile lead frame formed of the Cu/Cu2O composite alloy and having at least two different kinds of thicknesses, thetab 13 is formed to be thicker than theleads 6, and the back surface of the tab is exposed to an underside of the molding or encapsulating resin. Enhanced heat conduction can be achieved by soldering the back surface of the tab to the substrate. The present arrangement has the same effect as described in the second embodiment. - A cross sectional view of a semiconductor package according to a seventh embodiment is shown in FIG. 7. The leads6 of the lead frame formed of the Cu/Cu2O composite alloy are bonded to a circuit forming surface of the
semiconductor device 1 with an insulatingfilm 14 therebetween, and theleads 6 are electrically connected to thesemiconductor device 1 by lengths ofbonding wire 4. Thesemiconductor device 1 and electric connections are encapsulated by theresin 5. The leads 6 are drawn outside of the resin from the side of the semiconductor device. The semiconductor package according to the seventh embodiment is a lead on chip (LOC) structure frequently used in memory devices, and is capable of mounting thereon a large device having an outer shape close to that of the resin. There is a tendency to an increase in power dissipation of memory devices, and so the use of a copper alloy in place of a 42 Ni-Fe alloy conventionally used as a lead frame material has been investigated. However, there is a fear that such use may lead to an increase in thermal stress, reduction in life of solder joints with the substrate and breakage of bonding wire. Provided that the compounding ratio Of CU2O is made 80 vol. %, enhanced heat conduction can be achieved without being prejudicial to low stresses equivalent to those in the 42 Ni-Fe alloy. Provided that the compounding ratio of CU2O is in a range of 20 to 50 vol. %, enhanced heat conduction becomes possible in excess of that obtained with a copper alloy, which is ordinarily used as a lead frame material. - A cross sectional view of a semiconductor package according to an eighth embodiment is shown in FIG. 8.
Leads 6 a of a lead frame formed of the Cu/Cu2O composite alloy are bonded to a circuit forming surface of asemiconductor device 1 a with an insulatingfilm 14 a therebetween, and theleads 6 a are electrically connected to thesemiconductor device 1 by lengths ofbonding wire 4 a. Asemiconductor device 1 b, leads 6 b and lengths ofbonding wire 4 b, which are constituted in the same manner as that of the above arrangement, is disposed back to back relative to thedevice 1 a, and these two semiconductor devices and electric connections are encapsulated by theresin 5. The leads 6 b are connected to theleads 6 a, and electrical connection with the substrate is made by theleads 6 a, which are extended and drawn outside of the resin from the semiconductor package. The semiconductor package of the present constitution is applied in the case where memory devices are mounted in high density. The present constitution has the same effect as described in the seventh embodiment. - According to the present invention, there can be provided a resin encapsulated semiconductor package, in which reliability on strength is ensured and heat conducting properties are high as well.
Claims (4)
Applications Claiming Priority (3)
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JP2000-24693 | 2000-01-28 | ||
JP2000024693A JP3542311B2 (en) | 2000-01-28 | 2000-01-28 | Semiconductor device |
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DE102010044709B4 (en) * | 2010-09-08 | 2015-07-02 | Vincotech Holdings S.à.r.l. | Power semiconductor module with metal sintered connections and manufacturing process |
US9698086B2 (en) | 2012-07-05 | 2017-07-04 | Infineon Technologies Ag | Chip package and method of manufacturing the same |
US20220270984A1 (en) * | 2021-02-25 | 2022-08-25 | Texas Instruments Incorporated | Electronic device with crack arrest structure |
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JP3418373B2 (en) * | 2000-10-24 | 2003-06-23 | エヌ・アール・エス・テクノロジー株式会社 | Surface acoustic wave device and method of manufacturing the same |
JP2002299540A (en) * | 2001-04-04 | 2002-10-11 | Hitachi Ltd | Semiconductor device and manufacturing method therefor |
JP4157715B2 (en) * | 2002-03-20 | 2008-10-01 | 富士通株式会社 | Manufacturing method of semiconductor device |
CN100490140C (en) * | 2003-07-15 | 2009-05-20 | 飞思卡尔半导体公司 | Double gauge lead frame |
US6867072B1 (en) | 2004-01-07 | 2005-03-15 | Freescale Semiconductor, Inc. | Flipchip QFN package and method therefor |
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US20050248028A1 (en) * | 2004-05-05 | 2005-11-10 | Cheng-Yen Huang | Chip-packaging with bonding options connected to a package substrate |
KR20080065153A (en) * | 2007-01-08 | 2008-07-11 | 페어차일드코리아반도체 주식회사 | Power device package comprising metal tab die attach paddle(dap) and method of fabricating the same package |
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CN102575085A (en) * | 2009-10-20 | 2012-07-11 | 住友电木株式会社 | Epoxy resin composition for semiconductor encapsulation, semiconductor device, and release agent |
US9044213B1 (en) | 2010-03-26 | 2015-06-02 | Histologics, LLC | Frictional tissue sampling and collection method and device |
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JP2511289B2 (en) * | 1988-03-30 | 1996-06-26 | 株式会社日立製作所 | Semiconductor device |
JPH0567713A (en) * | 1991-09-06 | 1993-03-19 | Fujitsu Ltd | Manufacture of semiconductor device |
JP3594724B2 (en) * | 1995-09-29 | 2004-12-02 | 大日本印刷株式会社 | Partial precious metal plating method for lead frame |
JPH09148509A (en) * | 1995-11-22 | 1997-06-06 | Goto Seisakusho:Kk | Lead frame for semiconductor device and its surface treatment method |
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Cited By (7)
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DE102010044709B4 (en) * | 2010-09-08 | 2015-07-02 | Vincotech Holdings S.à.r.l. | Power semiconductor module with metal sintered connections and manufacturing process |
US9698086B2 (en) | 2012-07-05 | 2017-07-04 | Infineon Technologies Ag | Chip package and method of manufacturing the same |
US20140346660A1 (en) * | 2013-05-22 | 2014-11-27 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics devices having thermal stress reduction elements |
US9496214B2 (en) * | 2013-05-22 | 2016-11-15 | Toyota Motor Engineering & Manufacturing North American, Inc. | Power electronics devices having thermal stress reduction elements |
US20220270984A1 (en) * | 2021-02-25 | 2022-08-25 | Texas Instruments Incorporated | Electronic device with crack arrest structure |
US11495549B2 (en) * | 2021-02-25 | 2022-11-08 | Texas Instruments Incorporated | Electronic device with crack arrest structure |
US11798900B2 (en) | 2021-02-25 | 2023-10-24 | Texas Instruments Incorporated | Electronic device with crack arrest structure |
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TW476987B (en) | 2002-02-21 |
US6376905B2 (en) | 2002-04-23 |
KR100372587B1 (en) | 2003-02-15 |
KR20010078059A (en) | 2001-08-20 |
JP2001210777A (en) | 2001-08-03 |
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