US12224290B2 - Array substrate, method for fabricating same, and display panel - Google Patents

Array substrate, method for fabricating same, and display panel Download PDF

Info

Publication number
US12224290B2
US12224290B2 US17/764,220 US202217764220A US12224290B2 US 12224290 B2 US12224290 B2 US 12224290B2 US 202217764220 A US202217764220 A US 202217764220A US 12224290 B2 US12224290 B2 US 12224290B2
Authority
US
United States
Prior art keywords
insulating layer
substrate
opening area
interlayer insulating
gate insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/764,220
Other versions
US20240047483A1 (en
Inventor
Wen Yin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Assigned to WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YIN, Wen
Publication of US20240047483A1 publication Critical patent/US20240047483A1/en
Priority to US19/004,514 priority Critical patent/US20250142969A1/en
Application granted granted Critical
Publication of US12224290B2 publication Critical patent/US12224290B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H01L27/1248—
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H01L27/1259—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the technical field of display, and particularly to an array substrate, a method for fabricating the same, and a display panel.
  • the natural light After natural light enters a display panel, the natural light has three main paths: transmission, absorption, and reflection. Ideally, we want light to be completely transmitted or absorbed. However, in reality, the light cannot be completely transmitted or absorbed. A main reason is that there are many layers in the display panel, and refractive indices of these layers are different. Therefore, when the light enters different layers, its angle will change, that is, there will be reflected lights. The reflected lights at different interfaces produce interference effects.
  • a current low temperature polysilicon (LTPS) display panel has multiple insulating layers, so there are many contact surfaces with high reflectivities, so that the display panel has a relatively high reflectivity. When exposed to sunlight or ambient light, the display panel will have strong reflections, which reduces a contrast ratio of the display panel, thereby greatly affecting a display effect of the display panel.
  • LTPS low temperature polysilicon
  • a purpose of the present disclosure is to provide an array substrate, a method for fabricating the same, and a display panel, which can solve a problem that a current display panel has a relatively high reflectivity because the current display panel has many contact surfaces with high reflectivities, resulting in a decrease in a contrast ratio of the display panel, and finally a decrease in a display effect of the display panel.
  • an array substrate comprising an opening area and a non-opening area and further comprising a first substrate, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer.
  • the gate insulating layer is disposed on the first substrate and located in the opening area and the non-opening area.
  • the first interlayer insulating layer is disposed on a side of the gate insulating layer away from the first substrate and located in the non-opening area.
  • the second interlayer insulating layer is disposed on a side of the first interlayer insulating layer away from the first substrate and located in the opening area and the non-opening area.
  • a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate.
  • a surface of a part of the second interlayer insulating layer in the opening area close to the first substrate is attached to a surface of a part of the gate insulating layer in the opening area away from the first substrate.
  • the gate insulating layer and the second interlayer insulating layer are made of a same material.
  • a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the first interlayer insulating layer in the non-opening area.
  • the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer and the part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between the part of the first interlayer insulating layer and a part of the gate insulating layer in the non-opening area.
  • the array substrate further comprises an active layer, a gate electrode layer, and a source/drain electrode layer.
  • the active layer is disposed between the first substrate and the gate insulating layer, is located in the non-opening area, and is made of low temperature polysilicon.
  • the gate electrode layer is disposed between the gate insulating layer and the first interlayer insulating layer, and is located in the non-opening area.
  • the source/drain electrode layer is disposed on a side of the second interlayer insulating layer away from the first substrate, is located in the non-opening area, and is electrically connected to the active layer.
  • the present disclosure further provides a method for fabricating an array substrate, which comprises: defining an opening area and a non-opening area on a first substrate; forming a gate insulating layer on the first substrate in the opening area and the non-opening area; forming a first interlayer insulating layer on a side of a part of the gate insulating layer in the non-opening area away from the first substrate, wherein a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate; and forming a second interlayer insulating layer covering the first interlayer insulating layer in the non-opening area and a part of the gate insulating layer in the opening area.
  • the forming the first interlayer insulating layer on the side of the part of the gate insulating layer in the non-opening area away from the first substrate comprises: forming the first interlayer insulating layer on a side of the gate insulating layer in the opening area and the non-opening area away from the first substrate; and removing a part of the first interlayer insulating layer in the opening area, and retaining a part of the first interlayer insulating layer in the non-opening area.
  • the present disclosure further provides a display panel comprising the aforementioned array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the color filter substrate comprises a second substrate and a black matrix unit disposed on a side of the second substrate close to the first substrate.
  • a projection of the black matrix unit on the first substrate coincides with a projection of the non-opening area on the first substrate.
  • the projection of the first interlayer insulating layer on the first substrate is tangent to or separated from the projection of the opening area on the first substrate, so that the surface of the part of the second interlayer insulating layer in the opening area close to the first substrate is attached to the surface of the part of the gate insulating layer in the opening area away from the first substrate.
  • the gate insulating layer and the second interlayer insulating layer are made of the same material, so as to reduce the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer and the part of the gate insulating layer in the opening area, thereby reducing to reflectivity of the display panel, reducing reflection of the display panel to ambient light, improving a contrast ratio of the display panel, and improving a display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of reflection of light at a contact surface between a part of a second interlayer insulating layer and a part of a first interlayer insulating layer and a contact surface between the part of the first interlayer insulating layer and a part of a gate insulating layer in a non-opening area.
  • FIG. 3 is a schematic diagram of reflection of light at a contact surface between a part of a second interlayer insulating layer and a part of the gate insulating layer in an opening area.
  • FIG. 4 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • the present disclosure provides a display panel 100 .
  • the display panel 100 comprises an array substrate 1 , a color filter substrate 2 , and a liquid crystal layer 3 .
  • the array substrate 1 comprises an opening area 1100 and a non-opening area 1200 .
  • the array substrate 1 further comprises a first substrate 101 , an active layer 102 , a gate insulating layer 103 , a gate electrode layer 104 , a first interlayer insulating layer 105 , a second interlayer insulating layer 106 , a source/drain electrode layer 107 , a planarization layer 108 , a common electrode layer 109 , a passivation layer 110 , and a pixel electrode layer 111 .
  • the first substrate 101 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the first substrate 101 has a better impact resistance, and can effectively protect the display panel 100 .
  • the first substrate 101 is made of glass.
  • the active layer 102 is disposed on a side of the first substrate 101 close to the color filter substrate 2 .
  • the active layer 102 is located in the non-opening area 1200 .
  • the active layer 102 is made of low temperature polysilicon.
  • the gate insulating layer 103 covers a side of the active layer 102 away from the first substrate 101 , and extends to cover the first substrate 101 .
  • the gate insulating layer 103 is located in the opening area 1100 and the non-opening area 1200 .
  • the gate insulating layer 103 is mainly used to prevent short circuit due to contact between the active layer 102 and the gate electrode layer 104 .
  • the gate insulating layer 103 may be made of SiOx, SiNx, Al 2 O 3 , a combined structure of SiNx and SiOx, a combined structure of SiOx, SiNx, and SiOx, or the like. In this embodiment, the gate insulating layer 103 is made of SiOx.
  • the gate electrode layer 104 is disposed on a side of the gate insulating layer 103 away from the first substrate 101 and located in the non-opening area 1200 .
  • the gate electrode layer 104 may be made of Mo, a combined structure of Mo and Al, a combined structure of Mo and Cu, a combined structure of Mo, Cu, and indium zinc oxide (IZO), a combined structure of IZO, Cu, and IZO, a combined structure of Mo, Cu, and indium tin oxide (ITO), a combined structure of Ni, Cu, and Ni, a combined structure of NiCr, Cu, and NiCr, CuNb, or the like.
  • the first interlayer insulating layer 105 covers a side of the gate electrode layer 104 away from the first substrate 101 and extends to cover a surface of a part of the gate insulating layer 103 in the non-opening area 1200 away from the first substrate 101 .
  • the first interlayer insulating layer 105 is made of SiNx as a source of hydrogen atoms.
  • the first interlayer insulating layer 105 is baked at a specific temperature to diffuse hydrogen atoms into the active layer 102 (polysilicon) and the gate insulating layer 103 (the oxide layer).
  • a projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from a projection of the opening area 1100 on the first substrate 101 .
  • the first interlayer insulating layer 105 is only disposed in the non-opening area 1200 , but not disposed in the opening area 1100 .
  • the second interlayer insulating layer 106 covers a side of the first interlayer insulating layer 105 away from the first substrate 101 , and is located in the opening area 1100 and the non-opening area 1200 .
  • the second interlayer insulating layer 106 is made of a same material as the gate insulating layer 103 . That is, in this embodiment, the second interlayer insulating layer 106 is made of SiOx.
  • a surface of a part of the second interlayer insulating layer 106 in the opening area 1100 close to the first substrate 101 is attached to a surface of a part of the gate insulating layer 103 in the opening area 1100 away from the first substrate 101 .
  • the source/drain electrode layer 107 is disposed on a side of the second interlayer insulating layer 106 away from the first substrate 101 , is located in the non-opening area 1200 , and is electrically connected to the active layer 102 .
  • the source/drain electrode layer 107 may be made of Mo, a combined structure of Mo and Al, a combined structure of Mo and Cu, a combined structure of Mo, Cu, and indium zinc oxide (IZO), a combined structure of IZO, Cu, and IZO, a combined structure of Mo, Cu, and indium tin oxide (ITO), a combined structure of Ni, Cu, and Ni, a combined structure of NiCr, Cu, and NiCr, CuNb, or the like.
  • the planarization layer 108 covers a side of the source/drain electrode layer 107 away from the first substrate 101 , and extends to cover a surface of the second interlayer insulating layer 106 away from the first substrate 101 .
  • the planarization layer 108 is located in the opening area 1100 and the non-opening area 1200 .
  • the planarization layer 108 may be made of SiOx, SiNx, SiNOx, a combined structure of SiNx and SiOx, or the like. In this embodiment, the planarization layer 108 is made of SiOx.
  • the common electrode layer 109 is disposed on a surface of the planarization layer 108 away from the first substrate 101 .
  • the common electrode layer 109 is made of indium tin oxide (ITO).
  • the passivation layer 110 is disposed on a surface of the common electrode layer 109 away from the first substrate 101 .
  • the passivation layer 110 is mainly used to prevent short circuit due to contact between the common electrode layer 109 and the pixel electrode layer 111 .
  • the passivation layer 110 may be made of SiOx, SiNx, Al 2 O 3 , a combined structure of SiNx and SiOx, a combined structure of SiOx, SiNx, and SiOx, or the like. In this embodiment, the passivation layer 110 is made of SiOx.
  • the pixel electrode layer 111 is disposed on a surface of the passivation layer 110 away from the first substrate 101 .
  • the pixel electrode layer 111 is made of indium tin oxide (ITO).
  • the second interlayer insulating layer 106 is made of SiOx
  • the first interlayer insulating layer is made of SiNx
  • the gate insulating layer 103 is made of SiOx.
  • a refractive index of the second interlayer insulating layer 106 is 1.47
  • a refractive index of the first interlayer insulating layer 105 is 1.87
  • a refractive index of the gate insulating layer 103 is 1.45.
  • R 3 is less than R 1 +R 2 .
  • the projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from the projection of the opening area 1100 on the first substrate 101 , so that the surface of the part of the second interlayer insulating layer 106 in the opening area 1100 close to the first substrate 101 is attached to the surface of the part of the gate insulating layer 103 in the opening area 1100 away from the first substrate 101 .
  • the gate insulating layer 103 and the second interlayer insulating layer 106 are made of the same material, so as to reduce a reflectivity of light at a contact surface between the part of the second interlayer insulating layer 106 and the part of the gate insulating layer 103 in the opening area 1100 without affecting characteristics of a thin film transistor (TFT) of the array substrate 1 .
  • TFT thin film transistor
  • the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer 106 and the part of the gate insulating layer 103 in the opening area 1100 is less than a reflectivity of light at a contact surface between a part of the second interlayer insulating layer 106 and a part of the first interlayer insulating layer 105 in the non-opening area 1200 .
  • the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer 106 and the part of the gate insulating layer 103 in the opening area 1100 is less than a reflectivity of light at a contact surface between the part of the first interlayer insulating layer 105 and a part of the gate insulating layer 103 in the non-opening area 1200 .
  • the color filter substrate 2 is disposed opposite to the array substrate 1 .
  • the color filter substrate 2 comprises a second substrate 201 , a plurality of color resist units 202 , and a plurality of black matrix units 203 .
  • the second substrate 201 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the second substrate 201 has a better impact resistance, and can effectively protect the display panel 100 .
  • the second substrate 201 is made of glass.
  • the black matrix units 203 are disposed on a surface of the second substrate 201 close to the first substrate 101 at intervals.
  • the black matrix units 203 are configured to prevent cross-color.
  • a projection of one black matrix unit 203 on the first substrate 101 coincides with a projection of one non-opening area 1200 on the first substrate 101 .
  • the color resist units 202 are disposed on surfaces of the black matrix units 203 close to the first substrate 101 , and extends to cover the surface of the second substrate 201 close to the first substrate 101 .
  • the color resist units 202 comprise red color resist units, green color resist units, and blue color resist units.
  • a projection of one color resist unit 202 on the first substrate 101 overlaps with the projection of the opening area 1100 on the first substrate 101 .
  • the color resist units 202 include first color resist parts 2021 and second color resist parts 2022 connected to each other.
  • the first color resist parts 2021 are disposed on surfaces of the black matrix units 203 close to the first substrate 101
  • the second color resist parts 2022 are disposed on a surface of the second substrate 201 close to the first substrate 101 .
  • a projection of one of the first color resist parts 2021 on the first substrate 101 coincides with a corresponding one of the black matrix units 203 on the first substrate 101
  • a projection of one of the second color resist units 2022 on the first substrate 101 coincides with the projection of the opening area 1100 on the first substrate 101 .
  • the liquid crystal layer 3 is disposed between the array substrate 1 and the color filter substrate 2 .
  • Step S 1 defining an opening area 1100 and a non-opening area 1200 on a first substrate 101 , and forming a gate insulating layer 103 on the first substrate 101 in the opening area 1100 and the non-opening area 1200 .
  • Step S 2 forming a first interlayer insulating layer 105 on a side of a part of the gate insulating layer 103 in the non-opening area 1200 away from the first substrate 101 , wherein a projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from a projection of the opening area 1100 on the first substrate 101 .
  • Step S 3 forming a second interlayer insulating layer 106 covering the first interlayer insulating layer 105 in the non-opening area 1200 and a part of the gate insulating layer 103 in the opening area 1100 .
  • Step S 2 comprises: forming the first interlayer insulating layer 105 on a side of the gate insulating layer 103 in the opening area 1100 and the non-opening area 1200 away from the first substrate 101 , removing a part of the first interlayer insulating layer 105 in the opening area 1100 , and retaining a part of the first interlayer insulating layer 105 in the non-opening area 1200 .

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

An array substrate includes an opening area and a non-opening area, and further includes a first substrate, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer. The gate insulating layer is disposed on the first substrate and located in the opening area and the non-opening area. The first interlayer insulating layer is disposed on a side of the gate insulating layer away from the first substrate and located in the non-opening area. The second interlayer insulating layer is disposed on a side of the first interlayer insulating layer away from the first substrate and located in the opening area and the non-opening area. A projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate. A display panel includes the array substrate.

Description

RELATED APPLICATIONS
This application is a National Phase of PCT Patent Application No. PCT/CN2022/080666 having International filing date of Mar. 14, 2022, which claims the benefit of priority of Chinese Patent Application No. 202210185018.8 filed on Feb. 28, 2022. The contents of the above applications are all incorporated by reference as if fully set forth herein in their entirety.
FIELD AND BACKGROUND OF THE INVENTION
The present disclosure relates to the technical field of display, and particularly to an array substrate, a method for fabricating the same, and a display panel.
With continuous popularization of electronic products, an innovation speed of the electronic products is faster, and functional requirements of the electronic products are more stringent. In particular, pursuit of a lower reflectivity of display panels has become a development trend of a future market. The lower reflectivity can bring a more comfortable visual experience to users, especially in an environment with strong external ambient light.
After natural light enters a display panel, the natural light has three main paths: transmission, absorption, and reflection. Ideally, we want light to be completely transmitted or absorbed. However, in reality, the light cannot be completely transmitted or absorbed. A main reason is that there are many layers in the display panel, and refractive indices of these layers are different. Therefore, when the light enters different layers, its angle will change, that is, there will be reflected lights. The reflected lights at different interfaces produce interference effects. A formula for a reflectivity of light entering different layers is: reflectivity (R)=(n1−n2)2/(n1+n2)2 (n1 and n2 are real refractive indices of two media, respectively). According to the formula (R)=(n1−n2)2/(n1+n2)2, it can be known that when refractive indices n of two adjacent layers are closer, a reflectivity at a junction between the two adjacent layers is lower.
A current low temperature polysilicon (LTPS) display panel has multiple insulating layers, so there are many contact surfaces with high reflectivities, so that the display panel has a relatively high reflectivity. When exposed to sunlight or ambient light, the display panel will have strong reflections, which reduces a contrast ratio of the display panel, thereby greatly affecting a display effect of the display panel.
SUMMARY OF THE INVENTION
A purpose of the present disclosure is to provide an array substrate, a method for fabricating the same, and a display panel, which can solve a problem that a current display panel has a relatively high reflectivity because the current display panel has many contact surfaces with high reflectivities, resulting in a decrease in a contrast ratio of the display panel, and finally a decrease in a display effect of the display panel.
In order to solve the above problem, the present disclosure provides an array substrate comprising an opening area and a non-opening area and further comprising a first substrate, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer. The gate insulating layer is disposed on the first substrate and located in the opening area and the non-opening area. The first interlayer insulating layer is disposed on a side of the gate insulating layer away from the first substrate and located in the non-opening area. The second interlayer insulating layer is disposed on a side of the first interlayer insulating layer away from the first substrate and located in the opening area and the non-opening area. A projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate.
In an embodiment, a surface of a part of the second interlayer insulating layer in the opening area close to the first substrate is attached to a surface of a part of the gate insulating layer in the opening area away from the first substrate.
In an embodiment, the gate insulating layer and the second interlayer insulating layer are made of a same material.
In an embodiment, a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the first interlayer insulating layer in the non-opening area.
In an embodiment, the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer and the part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between the part of the first interlayer insulating layer and a part of the gate insulating layer in the non-opening area.
In an embodiment, the array substrate further comprises an active layer, a gate electrode layer, and a source/drain electrode layer. The active layer is disposed between the first substrate and the gate insulating layer, is located in the non-opening area, and is made of low temperature polysilicon. The gate electrode layer is disposed between the gate insulating layer and the first interlayer insulating layer, and is located in the non-opening area. The source/drain electrode layer is disposed on a side of the second interlayer insulating layer away from the first substrate, is located in the non-opening area, and is electrically connected to the active layer.
In order to solve the above problem, the present disclosure further provides a method for fabricating an array substrate, which comprises: defining an opening area and a non-opening area on a first substrate; forming a gate insulating layer on the first substrate in the opening area and the non-opening area; forming a first interlayer insulating layer on a side of a part of the gate insulating layer in the non-opening area away from the first substrate, wherein a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate; and forming a second interlayer insulating layer covering the first interlayer insulating layer in the non-opening area and a part of the gate insulating layer in the opening area.
In an embodiment, the forming the first interlayer insulating layer on the side of the part of the gate insulating layer in the non-opening area away from the first substrate comprises: forming the first interlayer insulating layer on a side of the gate insulating layer in the opening area and the non-opening area away from the first substrate; and removing a part of the first interlayer insulating layer in the opening area, and retaining a part of the first interlayer insulating layer in the non-opening area.
In order to solve the above problem, the present disclosure further provides a display panel comprising the aforementioned array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
In an embodiment, the color filter substrate comprises a second substrate and a black matrix unit disposed on a side of the second substrate close to the first substrate. A projection of the black matrix unit on the first substrate coincides with a projection of the non-opening area on the first substrate.
In the display panel of the present disclosure, the projection of the first interlayer insulating layer on the first substrate is tangent to or separated from the projection of the opening area on the first substrate, so that the surface of the part of the second interlayer insulating layer in the opening area close to the first substrate is attached to the surface of the part of the gate insulating layer in the opening area away from the first substrate. And, the gate insulating layer and the second interlayer insulating layer are made of the same material, so as to reduce the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer and the part of the gate insulating layer in the opening area, thereby reducing to reflectivity of the display panel, reducing reflection of the display panel to ambient light, improving a contrast ratio of the display panel, and improving a display effect of the display panel.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
In order to more clearly illustrate technical solutions in embodiments of the present disclosure, a brief description of accompanying drawings used in a description of the embodiments will be given below. Obviously, the accompanying drawings in the following description are merely some embodiments of the present disclosure. For those skilled in the art, other drawings may be obtained from these accompanying drawings without creative labor.
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
FIG. 2 is a schematic diagram of reflection of light at a contact surface between a part of a second interlayer insulating layer and a part of a first interlayer insulating layer and a contact surface between the part of the first interlayer insulating layer and a part of a gate insulating layer in a non-opening area.
FIG. 3 is a schematic diagram of reflection of light at a contact surface between a part of a second interlayer insulating layer and a part of the gate insulating layer in an opening area.
FIG. 4 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure.
 DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION
Preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, so as to fully introduce a technical content of the present invention to those skilled in the art, to demonstrate that the present invention can be implemented, thereby making the technical content of the present invention clearer, and making it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied by many different embodiments. The claimed scope of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the claimed scope of the present invention.
Directional terms mentioned in the present disclosure, such as “above”, “below”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, are merely used to indicate directions of the accompanying drawings. The directional terms are used for explaining and illustrating the present invention rather than limiting the claimed scope of the present invention.
In the accompanying drawings, components with a same structure are indicated by similar reference numerals. Components that are similar in structure or function are indicated by a same reference numeral. In addition, for ease of understanding and description, a size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the size and thickness of each component are not limited in the present disclosure.
Embodiment 1
Please refer to FIG. 1 , the present disclosure provides a display panel 100. The display panel 100 comprises an array substrate 1, a color filter substrate 2, and a liquid crystal layer 3.
The array substrate 1 comprises an opening area 1100 and a non-opening area 1200. The array substrate 1 further comprises a first substrate 101, an active layer 102, a gate insulating layer 103, a gate electrode layer 104, a first interlayer insulating layer 105, a second interlayer insulating layer 106, a source/drain electrode layer 107, a planarization layer 108, a common electrode layer 109, a passivation layer 110, and a pixel electrode layer 111.
The first substrate 101 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the first substrate 101 has a better impact resistance, and can effectively protect the display panel 100. In this embodiment, the first substrate 101 is made of glass.
The active layer 102 is disposed on a side of the first substrate 101 close to the color filter substrate 2. The active layer 102 is located in the non-opening area 1200. In this embodiment, the active layer 102 is made of low temperature polysilicon.
The gate insulating layer 103 covers a side of the active layer 102 away from the first substrate 101, and extends to cover the first substrate 101. The gate insulating layer 103 is located in the opening area 1100 and the non-opening area 1200. The gate insulating layer 103 is mainly used to prevent short circuit due to contact between the active layer 102 and the gate electrode layer 104. The gate insulating layer 103 may be made of SiOx, SiNx, Al2O3, a combined structure of SiNx and SiOx, a combined structure of SiOx, SiNx, and SiOx, or the like. In this embodiment, the gate insulating layer 103 is made of SiOx.
The gate electrode layer 104 is disposed on a side of the gate insulating layer 103 away from the first substrate 101 and located in the non-opening area 1200. The gate electrode layer 104 may be made of Mo, a combined structure of Mo and Al, a combined structure of Mo and Cu, a combined structure of Mo, Cu, and indium zinc oxide (IZO), a combined structure of IZO, Cu, and IZO, a combined structure of Mo, Cu, and indium tin oxide (ITO), a combined structure of Ni, Cu, and Ni, a combined structure of NiCr, Cu, and NiCr, CuNb, or the like.
The first interlayer insulating layer 105 covers a side of the gate electrode layer 104 away from the first substrate 101 and extends to cover a surface of a part of the gate insulating layer 103 in the non-opening area 1200 away from the first substrate 101. There are grain boundaries among the polysilicon grains, and there is an interface between polysilicon (the active layer 102) and an oxide layer (the gate insulating layer 103), which affects electrical properties of a thin film transistor. Therefore, hydrogenation treatment is generally used to improve conductivity, electron mobility, and threshold voltage uniformity of the thin film transistor. In this embodiment, the first interlayer insulating layer 105 is made of SiNx as a source of hydrogen atoms. The first interlayer insulating layer 105 is baked at a specific temperature to diffuse hydrogen atoms into the active layer 102 (polysilicon) and the gate insulating layer 103 (the oxide layer).
A projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from a projection of the opening area 1100 on the first substrate 101. In other words, the first interlayer insulating layer 105 is only disposed in the non-opening area 1200, but not disposed in the opening area 1100.
The second interlayer insulating layer 106 covers a side of the first interlayer insulating layer 105 away from the first substrate 101, and is located in the opening area 1100 and the non-opening area 1200. The second interlayer insulating layer 106 is made of a same material as the gate insulating layer 103. That is, in this embodiment, the second interlayer insulating layer 106 is made of SiOx.
A surface of a part of the second interlayer insulating layer 106 in the opening area 1100 close to the first substrate 101 is attached to a surface of a part of the gate insulating layer 103 in the opening area 1100 away from the first substrate 101.
The source/drain electrode layer 107 is disposed on a side of the second interlayer insulating layer 106 away from the first substrate 101, is located in the non-opening area 1200, and is electrically connected to the active layer 102. The source/drain electrode layer 107 may be made of Mo, a combined structure of Mo and Al, a combined structure of Mo and Cu, a combined structure of Mo, Cu, and indium zinc oxide (IZO), a combined structure of IZO, Cu, and IZO, a combined structure of Mo, Cu, and indium tin oxide (ITO), a combined structure of Ni, Cu, and Ni, a combined structure of NiCr, Cu, and NiCr, CuNb, or the like.
The planarization layer 108 covers a side of the source/drain electrode layer 107 away from the first substrate 101, and extends to cover a surface of the second interlayer insulating layer 106 away from the first substrate 101. The planarization layer 108 is located in the opening area 1100 and the non-opening area 1200. The planarization layer 108 may be made of SiOx, SiNx, SiNOx, a combined structure of SiNx and SiOx, or the like. In this embodiment, the planarization layer 108 is made of SiOx.
The common electrode layer 109 is disposed on a surface of the planarization layer 108 away from the first substrate 101. In this embodiment, the common electrode layer 109 is made of indium tin oxide (ITO).
The passivation layer 110 is disposed on a surface of the common electrode layer 109 away from the first substrate 101. The passivation layer 110 is mainly used to prevent short circuit due to contact between the common electrode layer 109 and the pixel electrode layer 111. The passivation layer 110 may be made of SiOx, SiNx, Al2O3, a combined structure of SiNx and SiOx, a combined structure of SiOx, SiNx, and SiOx, or the like. In this embodiment, the passivation layer 110 is made of SiOx.
The pixel electrode layer 111 is disposed on a surface of the passivation layer 110 away from the first substrate 101. In this embodiment, the pixel electrode layer 111 is made of indium tin oxide (ITO).
In this embodiment, the second interlayer insulating layer 106 is made of SiOx, the first interlayer insulating layer is made of SiNx, and the gate insulating layer 103 is made of SiOx. In actual measurement, a refractive index of the second interlayer insulating layer 106 is 1.47, a refractive index of the first interlayer insulating layer 105 is 1.87, and a refractive index of the gate insulating layer 103 is 1.45.
Please refer to FIG. 2 , R1=(1.47−1.87)2/(1.47+1.87)2=1.43%, and R2=(1.87−1.45)2/(1.87+1.45)2=1.6%.
Please refer to FIG. 3 , R3=(1.47−1.45)2/(1.47+1.45)2=0.005%. R3 is less than R1+R2. In the display panel 100 of the present disclosure, the projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from the projection of the opening area 1100 on the first substrate 101, so that the surface of the part of the second interlayer insulating layer 106 in the opening area 1100 close to the first substrate 101 is attached to the surface of the part of the gate insulating layer 103 in the opening area 1100 away from the first substrate 101. And, the gate insulating layer 103 and the second interlayer insulating layer 106 are made of the same material, so as to reduce a reflectivity of light at a contact surface between the part of the second interlayer insulating layer 106 and the part of the gate insulating layer 103 in the opening area 1100 without affecting characteristics of a thin film transistor (TFT) of the array substrate 1. Therefore, the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer 106 and the part of the gate insulating layer 103 in the opening area 1100 is less than a reflectivity of light at a contact surface between a part of the second interlayer insulating layer 106 and a part of the first interlayer insulating layer 105 in the non-opening area 1200. The reflectivity of the light at the contact surface between the part of the second interlayer insulating layer 106 and the part of the gate insulating layer 103 in the opening area 1100 is less than a reflectivity of light at a contact surface between the part of the first interlayer insulating layer 105 and a part of the gate insulating layer 103 in the non-opening area 1200. This reduces a reflectivity of the display panel, thereby reducing reflection of the display panel to ambient light, improving a contrast ratio of the display panel, and improving a display effect of the display panel.
The color filter substrate 2 is disposed opposite to the array substrate 1. The color filter substrate 2 comprises a second substrate 201, a plurality of color resist units 202, and a plurality of black matrix units 203.
The second substrate 201 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the second substrate 201 has a better impact resistance, and can effectively protect the display panel 100. In this embodiment, the second substrate 201 is made of glass.
The black matrix units 203 are disposed on a surface of the second substrate 201 close to the first substrate 101 at intervals. The black matrix units 203 are configured to prevent cross-color. A projection of one black matrix unit 203 on the first substrate 101 coincides with a projection of one non-opening area 1200 on the first substrate 101. The color resist units 202 are disposed on surfaces of the black matrix units 203 close to the first substrate 101, and extends to cover the surface of the second substrate 201 close to the first substrate 101. The color resist units 202 comprise red color resist units, green color resist units, and blue color resist units. A projection of one color resist unit 202 on the first substrate 101 overlaps with the projection of the opening area 1100 on the first substrate 101. The color resist units 202 include first color resist parts 2021 and second color resist parts 2022 connected to each other. The first color resist parts 2021 are disposed on surfaces of the black matrix units 203 close to the first substrate 101, and the second color resist parts 2022 are disposed on a surface of the second substrate 201 close to the first substrate 101. A projection of one of the first color resist parts 2021 on the first substrate 101 coincides with a corresponding one of the black matrix units 203 on the first substrate 101, and a projection of one of the second color resist units 2022 on the first substrate 101 coincides with the projection of the opening area 1100 on the first substrate 101.
The liquid crystal layer 3 is disposed between the array substrate 1 and the color filter substrate 2.
Please refer to FIG. 1 and FIG. 4 , the present disclosure further provides a method for fabricating an array substrate 1, which comprises the following steps. Step S1: defining an opening area 1100 and a non-opening area 1200 on a first substrate 101, and forming a gate insulating layer 103 on the first substrate 101 in the opening area 1100 and the non-opening area 1200. Step S2: forming a first interlayer insulating layer 105 on a side of a part of the gate insulating layer 103 in the non-opening area 1200 away from the first substrate 101, wherein a projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from a projection of the opening area 1100 on the first substrate 101. Step S3: forming a second interlayer insulating layer 106 covering the first interlayer insulating layer 105 in the non-opening area 1200 and a part of the gate insulating layer 103 in the opening area 1100.
Step S2 comprises: forming the first interlayer insulating layer 105 on a side of the gate insulating layer 103 in the opening area 1100 and the non-opening area 1200 away from the first substrate 101, removing a part of the first interlayer insulating layer 105 in the opening area 1100, and retaining a part of the first interlayer insulating layer 105 in the non-opening area 1200.
The array substrate, the method for fabricating the same, and the display panel provided by the present disclosure are described in detail above. The present disclosure uses specific embodiments to describe principles and implementations of the present disclosure. The above description of the embodiments is only for helping to understand solutions and core ideas of the present disclosure. Furthermore, those skilled in the art may make modifications to the specific embodiments and applications according to ideas of the present disclosure. In conclusion, the present specification should not be construed as a limitation to the present disclosure.

Claims (20)

What is claimed is:
1. An array substrate, comprising an opening area and a non-opening area, and further comprising:
a first substrate;
an active layer disposed on the first substrate and located in the non-opening area;
a gate insulating layer covering a side of the active layer away from the first substrate and located in the opening area and the non-opening area;
a gate electrode layer disposed on a side of the gate insulating layer away from the first substrate, and located in the non-opening area; and
a first interlayer insulating layer disposed on a side of the gate electrode layer and the gate insulating layer away from the first substrate and located in the non-opening area;
a second interlayer insulating layer disposed on a side of the first interlayer insulating layer away from the first substrate and located in the opening area and the non-opening area; and
a source/drain electrode layer disposed on a side of the second interlayer insulating layer away from the first substrate, located in the non-opening area, and electrically connected to the active layer through via holes going through the second interlayer insulating layer, the first interlayer insulating layer, and the gate insulating layer;
wherein a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate; a surface of a part of the second interlayer insulating layer in the opening area close to the first substrate is attached to a surface of a part of the gate insulating layer in the opening area away from the first substrate.
2. The array substrate according to claim 1, wherein the gate insulating layer and the second interlayer insulating layer are made of a same material.
3. The array substrate according to claim 1, wherein a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the first interlayer insulating layer in the non-opening area.
4. The array substrate according to claim 3, wherein the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer and the part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between the part of the first interlayer insulating layer and a part of the gate insulating layer in the non-opening area.
5. The array substrate according to claim 1,
wherein the active layer is made of low temperature polysilicon.
6. The array substrate according to claim 2, wherein the gate insulating layer and the second interlayer insulating layer are made of SiOx, and the first interlayer insulating layer is made of SiNx.
7. The array substrate according to claim 1, wherein the array substrate further comprises:
a planarization layer covering a side of the source/drain electrode layer away from the first substrate and located in the opening area and the non-opening area, wherein a surface of a part of the planarization layer in the opening area close to the first substrate is attached to the surface of a part of the second interlayer insulating layer in the opening area away from the first substrate.
8. The array substrate according to claim 7, wherein the planarization layer is made of SiOx.
9. The array substrate according to claim 7, wherein a thickness of a part of the planarization layer in the opening area is greater than a thickness of a part of the planarization layer in the non-opening area.
10. A method for fabricating an array substrate, comprising:
defining an opening area and a non-opening area on a first substrate;
forming an active layer disposed on the first substrate and located in the non-opening area;
forming a gate insulating layer covering a side of the active layer away from the first substrate and located in the opening area and the non-opening area;
forming a gate electrode layer disposed on a side of the gate insulating layer away from the first substrate and located in the non-opening area;
forming a first interlayer insulating layer on a side of a part of the gate electrode layer and the gate insulating layer in the non-opening area away from the first substrate, wherein a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate;
forming a second interlayer insulating layer located on a side of the first interlayer insulating layer in the non-opening area away from the first substrate and covering a part of the gate insulating layer in the opening area, wherein a surface of a part of the second interlayer insulating layer in the opening area close to the first substrate is attached to a surface of a part of the gate insulating layer in the opening area away from the first substrate; and
forming a source/drain electrode layer disposed on a side of the second interlayer insulating layer away from the first substrate, located in the non-opening area, and electrically connected to the active layer through via holes going through the second interlayer insulating layer, the first interlayer insulating layer, and the gate insulating layer.
11. The method for fabricating the array substrate according to claim 10, wherein the forming the first interlayer insulating layer on the side of the part of the gate insulating layer in the non-opening area away from the first substrate comprises:
forming the first interlayer insulating layer on a side of the gate insulating layer in the opening area and the non-opening area away from the first substrate; and
removing a part of the first interlayer insulating layer in the opening area, and retaining a part of the first interlayer insulating layer in the non-opening area.
12. A display panel, comprising an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate comprises an opening area and a non-opening area and further comprises:
a first substrate;
an active layer disposed on the first substrate and located in the non-opening area;
a gate insulating layer covering a side of the active layer away from the first substrate and located in the opening area and the non-opening area;
a gate electrode layer disposed on a side of the gate insulating layer away from the first substrate, and located in the non-opening area; and
a first interlayer insulating layer disposed on a side of the gate electrode layer and the gate insulating layer away from the first substrate and located in the non-opening area;
a second interlayer insulating layer disposed on a side of the first interlayer insulating layer away from the first substrate and located in the opening area and the non-opening area; and
a source/drain electrode layer disposed on a side of the second interlayer insulating layer away from the first substrate, located in the non-opening area, and electrically connected to the active layer through via holes going through the second interlayer insulating layer, the first interlayer insulating layer, and the gate insulating layer;
wherein a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate; a surface of a part of the second interlayer insulating layer in the opening area close to the first substrate is attached to a surface of a part of the gate insulating layer in the opening area away from the first substrate.
13. The display panel according to claim 12, wherein the gate insulating layer and the second interlayer insulating layer are made of a same material.
14. The display panel according to claim 12, wherein a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between a part of the second interlayer insulating layer and a part of the first interlayer insulating layer in the non-opening area.
15. The display panel according to claim 14, wherein the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer and the part of the gate insulating layer in the opening area is less than a reflectivity of light at a contact surface between the part of the first interlayer insulating layer and a part of the gate insulating layer in the non-opening area.
16. The display panel according to claim 12,
wherein the active layer is made of low temperature polysilicon.
17. The display panel according to claim 12, wherein the color filter substrate comprises:
a second substrate; and
a plurality of black matrix units disposed at intervals on a side of the second substrate close to the first substrate, wherein a projection of the black matrix unit on the first substrate coincides with a projection of the non-opening area on the first substrate.
18. The display panel according to claim 17, wherein the color filter substrate further comprises:
a plurality of color resist units comprising first color resist parts and second color resist parts connected to each other, the first color resist parts are disposed on surfaces of the black matrix units close to the first substrate, and the second color resist parts are disposed on a surface of the second substrate close to the first substrate;
wherein a projection of one of the first color resist parts on the first substrate coincides with a corresponding one of the black matrix units on the first substrate, and a projection of one of the second color resist units on the first substrate coincides with the projection of the opening area on the first substrate.
19. The display panel according to claim 18, wherein a contact surface is provided between a surface of the second interlayer insulating layer close to the first substrate and a surface of the gate interlayer layer away from the first substrate, and a projection of the contact surface on the first substrate covers a projection of a corresponding one of the second color resist parts on the first substrate.
20. The display panel according to claim 13, wherein the gate insulating layer and the second interlayer insulating layer are made of SiOx, and the first interlayer insulating layer is made of SiNx.
US17/764,220 2022-02-28 2022-03-14 Array substrate, method for fabricating same, and display panel Active US12224290B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US19/004,514 US20250142969A1 (en) 2022-02-28 2024-12-30 Display panel

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN202210185018.8 2022-02-28
CN202210185018.8A CN114566508B (en) 2022-02-28 2022-02-28 Array substrate and preparation method thereof, and display panel
PCT/CN2022/080666 WO2023159688A1 (en) 2022-02-28 2022-03-14 Array substrate and fabricating method therefor, and display panel

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/080666 A-371-Of-International WO2023159688A1 (en) 2022-02-28 2022-03-14 Array substrate and fabricating method therefor, and display panel

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US19/004,514 Continuation US20250142969A1 (en) 2022-02-28 2024-12-30 Display panel

Publications (2)

Publication Number Publication Date
US20240047483A1 US20240047483A1 (en) 2024-02-08
US12224290B2 true US12224290B2 (en) 2025-02-11

Family

ID=81715876

Family Applications (2)

Application Number Title Priority Date Filing Date
US17/764,220 Active US12224290B2 (en) 2022-02-28 2022-03-14 Array substrate, method for fabricating same, and display panel
US19/004,514 Pending US20250142969A1 (en) 2022-02-28 2024-12-30 Display panel

Family Applications After (1)

Application Number Title Priority Date Filing Date
US19/004,514 Pending US20250142969A1 (en) 2022-02-28 2024-12-30 Display panel

Country Status (3)

Country Link
US (2) US12224290B2 (en)
CN (2) CN119815921B (en)
WO (1) WO2023159688A1 (en)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886761A (en) * 1992-01-28 1999-03-23 Hitachi, Ltd. Process for producing actively addressing substrate, and liquid crystal display
US6639244B1 (en) * 1999-01-11 2003-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
CN102830556A (en) 2012-08-31 2012-12-19 北京京东方光电科技有限公司 Touch display panel and display device
CN103531610A (en) 2013-10-28 2014-01-22 京东方科技集团股份有限公司 Bottom emission substrate, display device and manufacturing method of substrate
CN105895581A (en) 2016-06-22 2016-08-24 武汉华星光电技术有限公司 TFT substrate manufacturing method
CN107085337A (en) 2017-06-14 2017-08-22 厦门天马微电子有限公司 Array base palte, display panel and display device
CN107293567A (en) 2016-04-12 2017-10-24 三星显示有限公司 Display device and method of manufacturing display device
US20190189697A1 (en) 2017-12-19 2019-06-20 Lg Display Co., Ltd. Two-way organic light emitting diode display device
CN110828476A (en) 2019-10-16 2020-02-21 武汉华星光电技术有限公司 Array substrate, preparation method thereof and display device
CN111446266A (en) 2020-05-12 2020-07-24 武汉华星光电技术有限公司 Display panel and method for producing the same
CN111725324A (en) 2020-06-11 2020-09-29 武汉华星光电半导体显示技术有限公司 Thin film transistor, array substrate and manufacturing method thereof
CN112054042A (en) 2019-06-07 2020-12-08 三星显示有限公司 Display device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101035914B1 (en) * 2004-07-30 2011-05-23 엘지디스플레이 주식회사 Flat panel display device and manufacturing method thereof
KR20090069828A (en) * 2007-12-26 2009-07-01 엘지디스플레이 주식회사 Double sided reflective liquid crystal display device
JP2017027872A (en) * 2015-07-27 2017-02-02 ソニー株式会社 Display device
KR102753554B1 (en) * 2016-12-28 2025-01-10 엘지디스플레이 주식회사 Display device having an irregular layer
CN106773221A (en) * 2017-02-17 2017-05-31 武汉华星光电技术有限公司 Array base palte and preparation method thereof and In Cell touch-control display panels
KR102836372B1 (en) * 2019-12-17 2025-07-18 엘지디스플레이 주식회사 Display Device And Method Of Fabricating The Same

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886761A (en) * 1992-01-28 1999-03-23 Hitachi, Ltd. Process for producing actively addressing substrate, and liquid crystal display
US6639244B1 (en) * 1999-01-11 2003-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
CN102830556A (en) 2012-08-31 2012-12-19 北京京东方光电科技有限公司 Touch display panel and display device
US9304349B2 (en) 2012-08-31 2016-04-05 Beijing Boe Optoelectronics Technology Co., Ltd. Touch display panel and display device
US9583646B2 (en) 2013-10-28 2017-02-28 Boe Technology Group Co., Ltd. Bottom-emitting substrate, display device and manufacturing method of substrate
CN103531610A (en) 2013-10-28 2014-01-22 京东方科技集团股份有限公司 Bottom emission substrate, display device and manufacturing method of substrate
CN107293567A (en) 2016-04-12 2017-10-24 三星显示有限公司 Display device and method of manufacturing display device
CN105895581A (en) 2016-06-22 2016-08-24 武汉华星光电技术有限公司 TFT substrate manufacturing method
CN107085337A (en) 2017-06-14 2017-08-22 厦门天马微电子有限公司 Array base palte, display panel and display device
US20190189697A1 (en) 2017-12-19 2019-06-20 Lg Display Co., Ltd. Two-way organic light emitting diode display device
CN109950276A (en) 2017-12-19 2019-06-28 乐金显示有限公司 Two-way organic LED display device
CN112054042A (en) 2019-06-07 2020-12-08 三星显示有限公司 Display device
CN110828476A (en) 2019-10-16 2020-02-21 武汉华星光电技术有限公司 Array substrate, preparation method thereof and display device
CN111446266A (en) 2020-05-12 2020-07-24 武汉华星光电技术有限公司 Display panel and method for producing the same
CN111725324A (en) 2020-06-11 2020-09-29 武汉华星光电半导体显示技术有限公司 Thin film transistor, array substrate and manufacturing method thereof
US11817462B2 (en) 2020-06-11 2023-11-14 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor, array substrate, and method for fabricating array substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Birendra Bahadur, Liquid Crystals Applications and Uses, 1990, World Scientific, vol. 1, pp. 171-194 (Year: 1990). *
Notification of Office Action and Search Report Dated Sep. 27, 2024 From The State Intellectual Property Office of the People's Republic of China Re. Application No. 202210185018.8 and Its Translation Into English. (20 Pages).

Also Published As

Publication number Publication date
CN119815921A (en) 2025-04-11
CN114566508B (en) 2024-11-22
CN114566508A (en) 2022-05-31
US20240047483A1 (en) 2024-02-08
WO2023159688A1 (en) 2023-08-31
CN119815921B (en) 2025-09-19
US20250142969A1 (en) 2025-05-01

Similar Documents

Publication Publication Date Title
EP3171214B1 (en) Array substrate, preparation method therefor, and display device
US11199750B2 (en) Display panel having black matrix comprising extension portions
US8212951B2 (en) Liquid crystal display
US20140054581A1 (en) Array substrate, manufacturing method thereof, and display device
US10649301B2 (en) Display panel, manufacturing method thereof and display device
WO2016202060A1 (en) Array substrate and manufacturing method therefor, and display apparatus
US8982303B2 (en) Transflective liquid crystal display and method thereof
JP2025061877A (en) Liquid crystal display device
US10048556B2 (en) Array substrate having multiple common electrode lines
CN104977762A (en) display device
KR20180003662A (en) Display device
JP2024528526A (en) Display substrate and its manufacturing method, display device
WO2023272505A1 (en) Display substrate and preparation method therefor, and display device
CN116224666A (en) Array substrate and manufacturing method thereof, display panel and display device
CN114660862B (en) Array substrate, manufacturing method and display panel
US8767150B2 (en) Liquid crystal display and method of manufacturing the same
CN114527596B (en) Display panels and mobile terminals
CN105990371A (en) Display panel
US12224290B2 (en) Array substrate, method for fabricating same, and display panel
KR20060111261A (en) Semi-transmissive liquid crystal display and manufacturing method thereof
WO2017143660A1 (en) Array substrate, display panel, and liquid crystal display device
KR101765862B1 (en) Liquid crystal display device
US12411386B2 (en) Liquid crystal display device
US11927858B2 (en) Array substrate and display device
CN212033021U (en) TFT substrate and display device

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YIN, WEN;REEL/FRAME:059466/0829

Effective date: 20220325

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

ZAAB Notice of allowance mailed

Free format text: ORIGINAL CODE: MN/=.

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE