US12218238B2 - Growth structure for strained channel, and strained channel using the same and method of manufacturing device using the same - Google Patents

Growth structure for strained channel, and strained channel using the same and method of manufacturing device using the same Download PDF

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US12218238B2
US12218238B2 US17/522,851 US202117522851A US12218238B2 US 12218238 B2 US12218238 B2 US 12218238B2 US 202117522851 A US202117522851 A US 202117522851A US 12218238 B2 US12218238 B2 US 12218238B2
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strained channel
channel layer
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Sanghyeon Kim
Hyeongrak LIM
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Korea Advanced Institute of Science and Technology KAIST
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H01L29/7849—
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • Various embodiments relate to a growth structure for a strained channel, and a strained channel using the same and a method of manufacturing a device using the same.
  • the mobility of electrons and holes in a strained material layer is significantly higher than the mobility thereof in bulk silicon. Accordingly, if a device includes a strained channel, the device will have improved operating performance. For example, the device may operate at a high speed by using low consumption power. Accordingly, there is a need for a technology for implementing a strained channel and a device having the strained channel.
  • Various embodiments provide a growth structure for a strained channel, and a strained channel using the same and a method of manufacturing a device using the same. Specifically, various embodiments provide a growth structure for fabricating a strained channel. Furthermore, various embodiments provide a method of implementing a strained channel by using a growth structure. Furthermore, various embodiments provide a method of fabricating a device by using a growth structure.
  • a growth structure for a strained channel may include a support substrate, a strain-relaxed buffer (SRB) layer disposed on a support substrate, a base growth layer grown to have one composition on the SRB layer, and a strained channel layer grown to have another composition on the base growth layer.
  • SRB strain-relaxed buffer
  • a method of fabricating a strained channel may include preparing a growth structure for the strained channel and a base substrate, rotating the growth structure and bonding a strained channel layer to the top of the base substrate, and removing a base growth layer, an SRB layer, and a support substrate from the top of the strained channel layer by leaving the strained channel layer on the base substrate.
  • a method of manufacturing a device using a strained channel may include forming electrodes on a strained channel layer remained on a base substrate.
  • a device having a strained channel layer can be fabricated by using a monolithic integration method. That is, a growth structure for a strained channel is implemented because a strained channel layer is grown on a support substrate by using a hetero-epitaxy method. The strained channel layer can be easily bonded on a base substrate based on such a growth structure. Moreover, a device having the strained channel layer can be fabricated by using the growth structure. Accordingly, a device having improved operating performance can be fabricated.
  • FIG. 1 is a diagram illustrating a growth structure for a strained channel according to first embodiments.
  • FIGS. 2 A to 2 G are diagrams illustrating a method of fabricating a strained channel according to the first embodiments.
  • FIG. 3 is a diagram illustrating a growth structure for a strained channel according to second embodiments.
  • FIGS. 4 A to 4 H are diagrams illustrating a method of fabricating a strained channel according to the second embodiments.
  • FIGS. 5 A and 5 B are diagrams illustrating a growth structure for a strained channel according to third embodiments.
  • FIGS. 6 A to 6 H are diagrams illustrating a method of fabricating a strained channel according to the third embodiments.
  • FIGS. 7 A to 7 E are diagrams illustrating a method of manufacturing a device according to various embodiments.
  • FIG. 1 is a diagram illustrating a growth structure 100 for a strained channel according to first embodiments.
  • the growth structure 100 for a strained channel may include a support substrate 110 , a strain-relaxed buffer (SRB) layer 120 , a base growth layer 130 and 140 , and a strained channel layer 150 .
  • SRB strain-relaxed buffer
  • the support substrate 110 may support the SRB layer 120 , the base growth layer 130 and 140 , and the strained channel layer 150 .
  • the support substrate 110 may be made of silicon (Si).
  • the SRB layer 120 may be disposed on the support substrate 110 .
  • the SRB layer 120 may be a lattice mismatch with the strained channel layer 150 .
  • a lattice constant of the SRB layer 120 may be different from a lattice constant of the strained channel layer 150 . Accordingly, a stain may be applied to the strained channel layer 150 through the SRB layer 120 .
  • the base growth layer 130 and 140 and the strained channel layer 150 may be grown on the SRB layer 120 by using a hetero-epitaxy method.
  • the base growth layer 130 and 140 and the strained channel layer 150 may be made of a silicon (Si)-germanium (Ge) material.
  • the base growth layer 130 and 140 and the strained channel layer 150 may be grown on the SRB layer 120 based on different etch rates.
  • the base growth layer 130 and 140 may be disposed on the SRB layer 120 .
  • the base growth layer 130 and 140 may be grown to have a first composition (e.g., y) on the SRB layer 120 .
  • the base growth layer 130 and 140 may be made of at least one of silicon (Si 1-y ) or germanium (Ge y ).
  • the base growth layer 130 and 140 may include a plurality of layers.
  • the base growth layer 130 and 140 may include a buffer layer 130 and a p-type layer 140 .
  • the buffer layer 130 may be disposed on the SRB layer 120
  • the p-type layer 140 may be disposed on the buffer layer 130 .
  • the buffer layer 130 may be denoted as a germanium (Ge)-rich silicon-germanium (Si 1-y Ge y ) buffer layer.
  • the p-type layer 140 may be denoted as a p-type germanium (Ge)-rich silicon-germanium (Si 1-y Ge y ) material layer.
  • the strained channel layer 150 may be disposed on the base growth layer 130 and 140 .
  • the strained channel layer 150 may be grown as a single channel structure. That is, as a strain is applied to the strained channel layer 150 by the SRB layer 120 , the strained channel layer 150 may be grown to have a second composition (e.g., z) on the base growth layer 130 and 140 .
  • the strained channel layer 150 may be denoted as a tensile-strained channel layer.
  • the strained channel layer 150 may be made of at least one of silicon (Si 1-z ) or germanium (Ge z ).
  • FIGS. 2 A to 2 G are diagrams illustrating a method of fabricating a strained channel according to the first embodiments.
  • the growth structure 100 for a strained channel, such as that illustrated in FIG. 1 , and a base substrate 220 are prepared, as illustrated in FIGS. 2 A to 2 D .
  • the growth structure 100 may be bonded to the top of the base substrate 220 .
  • the growth structure 100 may be bonded to the top of the base substrate 220 by using a monolithic integration method.
  • a first insulating layer 210 may be formed on the strained channel layer 150 of the growth structure 100 .
  • the first insulating layer 210 may be formed on an strained channel layer 150 by using a thin film deposition technique.
  • the growth structure 100 may be dipped into a bath B containing a solvent.
  • a voltage may be applied to the growth structure 100 through a power source S.
  • the first insulating layer 210 may be formed on the strained channel layer 150 .
  • the growth structure 100 may be rotated. That is, the growth structure 100 may be rotated so that the first insulating layer 210 is directed toward the base substrate 220 , in other words, the base growth layer 130 and 140 and the strained channel layer 150 are inverted.
  • the base substrate 220 may include a support substrate 221 and a second insulating layer 223 disposed on the support substrate 221 . In this case, the second insulating layer 223 may be exposed to the growth structure 100 , that is, the strained channel layer 150 .
  • the first insulating layer 210 may face the second insulating layer 223 , the strained channel layer 150 may be disposed on the first insulating layer 210 , and the base growth layer 130 and 140 may be disposed on the strained channel layer 150 .
  • the p-type layer 140 may be disposed on the strained channel layer 150
  • the buffer layer 130 may be disposed on the p-type layer 140 .
  • the SRB layer 120 may be disposed on the base growth layer 130 and 140
  • the support substrate 110 may be disposed on the SRB layer 120 .
  • the growth structure 100 may be bonded to the top of the base substrate 220 . That is, the strained channel layer 150 may be bonded to the top of the base substrate 220 through the first insulating layer 210 . In this case, as the first insulating layer 210 is combined with the second insulating layer 223 , an insulating layer 225 may be formed between the strained channel layer 150 and the support substrate 221 and the strained channel layer 150 may be bonded to the top of the base substrate 220 .
  • the base growth layer 130 and 140 , the SRB layer 120 , and the support substrate 110 may be removed from the top of the strained channel layer 150 .
  • the base growth layer 130 and 140 , the SRB layer 120 , and the support substrate 110 may be removed from the top of the strained channel layer 150 by using at least one of an anodizing technique, a grinding technique or an etching technique.
  • the p-type layer 140 may be removed on the strained channel layer 150 by using the anodizing technique.
  • a surface of the strained channel layer 150 may be mechanically grinded.
  • the buffer layer 130 , the SRB layer 120 , and the support substrate 110 may be separated from the strained channel layer 150 .
  • the strained channel layer 150 may remain.
  • the support substrate 110 , the SRB layer 120 , and the base growth layer 130 and 140 may be sequentially removed using the grinding technique and the etching technique.
  • the strained channel layer 150 may remain.
  • a strained channel substrate 220 ′ may be fabricated.
  • the strained channel substrate 220 ′ may include the support substrate 221 , the insulating layer 225 disposed on the support substrate 221 , and the strained channel layer 150 disposed on the insulating layer 225 .
  • the strained channel layer 150 may represent a strained channel having a single channel structure.
  • FIG. 3 is a diagram illustrating a growth structure 300 for a strained channel according to second embodiments.
  • the growth structure 300 for a strained channel may include a support substrate 310 , a strain-relaxed buffer (SRB) 320 , a base growth layer 330 and 340 , an etch-stop layer 360 , and a strained channel layer 370 .
  • SRB strain-relaxed buffer
  • the support substrate 310 may support the SRB layer 320 , the base growth layer 330 and 340 , the etch-stop layer 360 , and the strained channel layer 370 .
  • the support substrate 310 may be made of silicon (Si).
  • the SRB layer 320 may be disposed on the support substrate 310 .
  • the SRB layer 320 may be a lattice mismatch with the strained channel layer 370 .
  • a lattice constant of the SRB layer 320 may be different from a lattice constant of the strained channel layer 370 . Accordingly, a strain may be applied to the strained channel layer 370 through the SRB layer 320 .
  • the base growth layer 330 and 340 and the strained channel layer 370 may be grown on the SRB layer 320 by using a hetero-epitaxy method.
  • the base growth layer 330 and 340 and the strained channel layer 370 may be made of a silicon (Si)-germanium (Ge) material.
  • the base growth layer 330 and 340 and the strained channel layer 370 may be grown on the SRB layer 320 based on different etch rates.
  • the base growth layer 330 and 340 may be disposed on the SRB layer 320 .
  • the base growth layer 330 and 340 may be grown to have a first composition (e.g., y) on the SRB layer 320 .
  • the base growth layer 330 and 340 may be made of at least one of silicon (Si 1-y ) or germanium (Ge y ).
  • the base growth layer 330 and 340 may include a plurality of layers.
  • the base growth layer 330 and 340 may include a buffer layer 330 and a p-type layer 340 .
  • the buffer layer 330 may be disposed on the SRB layer 320 .
  • the p-type layer 340 may be disposed on the buffer layer 330 .
  • the buffer layer 330 may be denoted as a germanium (Ge)-rich silicon-germanium (Si 1-y Ge y ) buffer layer.
  • the p-type layer 340 may be denoted as a p-type germanium (Ge)-rich silicon-germanium (Si 1-y Ge y ) material layer.
  • the etch-stop layer 360 may be disposed on the base growth layer 330 and 340 .
  • the strained channel layer 370 may be disposed on the etch-stop layer 360 .
  • the strained channel layer 370 may be grown as a single channel structure. That is, as a strain is applied to the strained channel layer 370 by the SRB layer 320 , the strained channel layer 370 may be grown to have a third composition (e.g., x) on the etch-stop layer 360 .
  • the strained channel layer 370 may be denoted as a compressively-strained channel layer.
  • the strained channel layer 370 may be made of at least one of silicon (Si 1-x ) or germanium (Ge x ).
  • FIGS. 4 A to 4 H are diagrams illustrating a method of fabricating a strained channel according to the second embodiments.
  • the growth structure 300 may be bonded to the top of the base substrate 420 .
  • the growth structure 300 may be bonded to the top of the base substrate 420 by using a monolithic integration method.
  • a first insulating layer 410 may be formed on the strained channel layer 370 of the growth structure 300 .
  • the first insulating layer 410 may be formed on an the strained channel layer 370 by using a thin film deposition technique.
  • the growth structure 300 may be dipped into a bath B containing a solvent, and a voltage may be applied to the growth structure 300 through a power source S.
  • the first insulating layer 410 may be formed on the strained channel layer 370 .
  • the growth structure 300 may be rotated. That is, the growth structure 300 may be rotated so that the first insulating layer 410 is directed toward the base substrate 420 , in other words, the base growth layer 330 and 340 and the strained channel layer 370 are inverted.
  • the base substrate 420 may include a support substrate 421 and a second insulating layer 423 disposed on the support substrate 421 . In this case, the second insulating layer 423 may be exposed to the growth structure 300 , that is, the strained channel layer 370 .
  • the first insulating layer 410 may face the second insulating layer 423 , the strained channel layer 370 may be disposed on the first insulating layer 410 , and the base growth layer 330 and 340 may be disposed on the strained channel layer 370 .
  • the etch-stop layer 360 may be disposed on the strained channel layer 370
  • the p-type layer 340 may be disposed on the etch-stop layer 360
  • the buffer layer 330 may be disposed on the p-type layer 340 .
  • the SRB layer 320 may be disposed on the base growth layer 330 and 340
  • the support substrate 310 may be disposed on the SRB layer 320 .
  • the growth structure 300 may be bonded to the top of the base substrate 420 . That is, the strained channel layer 370 may be bonded to the top of the base substrate 420 through the first insulating layer 410 .
  • an insulating layer 425 may be formed between the strained channel layer 370 and the support substrate 421 , and the strained channel layer 370 may be bonded to the top of the base substrate 420 .
  • the etch-stop layer 360 , the base growth layer 330 and 340 , the SRB layer 320 , and the support substrate 310 may be removed from the top of the strained channel layer 370 .
  • the base growth layer 330 and 340 , the SRB layer 320 , and the support substrate 310 may be removed from the top of the etch-stop layer 360 by using at least one of an anodizing technique, a grinding technique or an etching technique.
  • the p-type layer 340 may be removed on the etch-stop layer 360 by using the anodizing technique.
  • a surface of the etch-stop layer 360 may be mechanically grinded.
  • the buffer layer 330 , the SRB layer 320 , and the support substrate 310 may be separated from the etch-stop layer 360 .
  • the etch-stop layer 360 and the strained channel layer 370 may remain.
  • the support substrate 310 , the SRB layer 320 , and the base growth layer 330 and 340 may be sequentially removed by using the grinding technique and the etching technique.
  • the etch-stop layer 360 and the strained channel layer 370 may remain.
  • the etch-stop layer 360 may be removed from the top of the strained channel layer 370 .
  • a strained channel substrate 420 ′ may be fabricated.
  • the strained channel substrate 420 ′ may include the support substrate 421 , the insulating layer 425 disposed on the support substrate 421 , and the strained channel layer 370 disposed on the insulating layer 425 .
  • the strained channel layer 370 may represent a strained channel having a single channel structure.
  • FIGS. 5 A and 5 B are diagrams illustrating a growth structure 500 for a strained channel according to third embodiments.
  • the growth structure 500 for a strained channel may include a support substrate 510 , an SRB layer 520 , a base growth layer 530 and 540 , and a strained channel layer 550 , 560 , 570 , and 580 .
  • the support substrate 510 may support the SRB layer 520 , the base growth layer 530 and 540 , and the strained channel layer 550 , 560 , 570 , and 580 .
  • the support substrate 510 may be made of silicon (Si).
  • the SRB layer 520 may be disposed on the support substrate 510 .
  • the SRB layer 520 may be a lattice mismatch with the strained channel layer 570 .
  • a lattice constant of the SRB layer 520 may be different from a lattice constant of the strained channel layer 570 . Accordingly, a strain may be applied to the strained channel layer 570 through the SRB layer 520 .
  • the base growth layer 530 and 540 and the strained channel layer 570 may be grown on the SRB layer 520 by using a hetero-epitaxy method.
  • the base growth layer 530 and 540 and the strained channel layer 570 may be made of a silicon (Si)-germanium (Ge) material.
  • the base growth layer 530 and 540 and the strained channel layer 570 may be grown on the SRB layer 520 based on different etch rates.
  • the base growth layer 530 and 540 may be disposed on the SRB layer 520 .
  • the base growth layer 530 and 540 may be grown to have a first composition (e.g., y) on the SRB layer 520 .
  • the base growth layer 530 and 540 may be made of at least one of silicon (Si 1-y ) or germanium (Ge y ).
  • the base growth layer 530 and 540 may include a plurality of layers.
  • the base growth layer 530 and 540 may include a buffer layer 530 and a p-type layer 540 .
  • the buffer layer 530 may be disposed on the SRB layer 520 .
  • the p-type layer 540 may be disposed on the buffer layer 530 .
  • the buffer layer 530 may be denoted as a germanium (Ge)-rich silicon-germanium (Si 1-y Ge y ) buffer layer.
  • the p-type layer 540 may be denoted as a p-type germanium (Ge)-rich silicon-germanium (Si 1-y Ge y ) material layer.
  • the strained channel layer 550 , 560 , 570 , and 580 may be disposed on the base growth layer 530 and 540 .
  • the strained channel layer 550 , 560 , 570 , and 580 may be grown as a dual channel structure. That is, as a strain is applied to the strained channel layer 550 , 560 , 570 , and 580 by the SRB layer 220 , the strained channel layer 550 , 560 , 570 , and 580 may be grown to have a second composition (e.g., z) and a third composition (e.g., x) on the base growth layer 530 and 540 .
  • a second composition e.g., z
  • a third composition e.g., x
  • the strained channel layer 550 , 560 , 570 , and 580 may include a first strained channel layer 550 , an etch-stop layer 560 , and a second strained channel layer 570 .
  • the strained channel layer 550 , 560 , 570 , and 580 may further include an insulating member 580 .
  • the first strained channel layer 550 may be disposed on some area of the base growth layer 530 and 540 .
  • the first strained channel layer 550 may be grown to have a second composition (e.g., z) on some area of the base growth layer 530 and 540 .
  • the first strained channel layer 550 may be denoted as a tensile-strained channel layer.
  • the first strained channel layer 550 may be made of at least one of silicon (Si 1-z ) or germanium (Ge z ).
  • the etch-stop layer 560 may be disposed on another area of the base growth layer 530 and 540 .
  • the second strained channel layer 570 may be disposed on the etch-stop layer 560 .
  • the second strained channel layer 570 may be grown to have a third composition (e.g., x) on the etch-stop layer 560 .
  • the second strained channel layer 570 may be denoted as a compressively strained channel layer.
  • the second strained channel layer 570 may be made of at least one of silicon (Si 1-x ) or germanium (Ge x ).
  • the insulating member 580 may be interposed between the first strained channel layer 550 and the etch-stop layer 560 and between the first strained channel layer 550 and the second strained channel layer 570 on the base growth layer 530 and 540 .
  • FIGS. 6 A to 6 H are diagrams illustrating a method of fabricating a strained channel according to the third embodiments.
  • the growth structure 500 may be bonded to the top of the base substrate 620 .
  • the growth structure 500 may be bonded to the top of the base substrate 620 by using a monolithic integration method.
  • a first insulating layer 610 may be formed on the strained channel layer 550 , 560 , 570 , and 580 of the growth structure 500 .
  • the first insulating layer 610 may be formed on an strained channel layer 550 , 560 , 570 , and 580 by using a thin film deposition technique.
  • the growth structure 500 may be dipped into a bath B containing a solvent, and a voltage may be applied to the growth structure 500 through a power source S. Accordingly, as illustrated in FIG.
  • the first insulating layer 610 may be formed on the strained channel layer 550 , 560 , 570 , and 580 .
  • the first insulating layer 610 may be formed on surfaces of the first strained channel layer 550 and the second strained channel layer 570 .
  • the first insulating layer 610 may be formed on surfaces of the first strained channel layer 550 , the insulating member 580 , and the second strained channel layer 570 .
  • the growth structure 500 may be rotated. That is, the growth structure 500 may be rotated so that the first insulating layer 610 is directed toward the base substrate 620 , in other words, the base growth layer 530 and 540 and the strained channel layer 550 , 560 , 570 , and 580 are inverted.
  • the base substrate 620 may include a support substrate 621 and a second insulating layer 623 disposed on the support substrate 621 . In this case, the second insulating layer 623 may be exposed to the growth structure 500 , that is, the strained channel layer 550 , 560 , 570 , and 580 .
  • the first insulating layer 610 may face the second insulating layer 623 , the strained channel layer 550 , 560 , 570 , and 580 may be disposed on the first insulating layer 610 , and the base growth layer 530 and 540 may be disposed on the strained channel layer 550 , 560 , 570 , and 580 .
  • the etch-stop layer 560 may be disposed on the second strained channel layer 570
  • the p-type layer 540 may be disposed on the etch-stop layer 560 and the first strained channel layer 550
  • the buffer layer 530 may be disposed on the p-type layer 540 .
  • the p-type layer 540 may be disposed on the etch-stop layer 560 , the insulating member 580 , and the first strained channel layer 550 , and the buffer layer 530 may be disposed on the p-type layer 540 .
  • the SRB layer 520 may be disposed on the base growth layer 530 and 540 , and the support substrate 510 may be disposed on the SRB layer 520 .
  • the growth structure 500 may be bonded to the top of the base substrate 620 . That is, the strained channel layer 550 , 560 , 570 , and 580 may be bonded to the top of the base substrate 620 through the first insulating layer 610 .
  • an insulating layer 625 may be formed between the strained channel layer 550 , 560 , 570 , and 580 and the support substrate 621 , and the strained channel layer 550 , 560 , 570 , and 580 may be bonded to the top of the base substrate 620 .
  • the etch-stop layer 560 , the base growth layer 530 and 540 , the SRB layer 520 and the support substrate 510 may be removed from the top of the strained channel layer 550 , 560 , 570 , and 580 .
  • the base growth layer 530 and 540 , the SRB layer 520 , and the support substrate 510 may be removed from the top of the strained channel layer 550 , 560 , 570 , and 580 by using at least one of an anodizing technique, a grinding technique or an etching technique.
  • the p-type layer 540 may be removed from the top of the etch-stop layer 560 by using the anodizing technique.
  • a surface of the etch-stop layer 560 may be mechanically grinded. Accordingly, the buffer layer 530 , the SRB layer 520 , and the support substrate 510 may be separated from the strained channel layer 550 , 560 , 570 , and 580 . As a result, as illustrated in FIG. 6 G , the etch-stop layer 560 and the second strained channel layer 570 may remain. According to another embodiment, as illustrated in FIG. 6 F , the support substrate 510 , the SRB layer 520 , and the base growth layer 530 and 540 may be sequentially removed using the grinding technique and the etching technique. As a result, as illustrated in FIG.
  • the etch-stop layer 560 and the second strained channel layer 570 may remain. Thereafter, as illustrated in FIG. 6 H , the etch-stop layer 560 may be removed from the top of the second strained channel layer 570 . In this case, a part of the first strained channel layer 550 may be removed along with the etch-stop layer 560 so that the first strained channel layer 550 has the same height as the second strained channel layer 570 .
  • a part of the insulating member 580 may be further removed along with the etch-stop layer 560 so that the insulating member 580 has the same height as the second strained channel layer 570 .
  • a strained channel substrate 620 ′ may be fabricated.
  • the strained channel substrate 620 ′ may include the support substrate 621 , the insulating layer 625 disposed on the support substrate 621 , and the strained channel layers 550 , 570 , and 580 disposed on the insulating layer 625 .
  • the strained channel layers 550 , 570 , and 580 may represent strained channels having a dual channel structure. That is, the strained channel layers 550 , 570 , and 580 may include the first strained channel layer 550 and the second strained channel layer 570 disposed on the insulating layer 625 .
  • the strained channel layers 550 , 570 , and 580 may further include the insulating member 580 interposed between the first strained channel layer 550 and the second strained channel layer 570 on the insulating layer 625 .
  • FIGS. 7 A to 7 E are diagrams illustrating a method of manufacturing a device 700 according to various embodiments.
  • a strained channel substrate 720 (e.g., 220 ′ in FIG. 2 F, 420 ′ in FIG. 4 G , or 620 ′ in FIG. 6 G ) is fabricated, as illustrated in FIGS. 7 A to 7 E , electrodes 740 , 770 , and 780 may be formed on a strained channel layer 727 (e.g., 150 in FIG. 2 F, 370 in FIG. 4 G, 550 and 570 in FIG. 6 F ).
  • the strained channel substrate 720 may include a base substrate 721 and 725 , that is, a support substrate 721 (e.g., 221 in FIG. 2 F, 421 in FIG. 4 G, 621 in FIG.
  • the electrodes 740 , 770 , and 780 may include a gate 740 , a source 770 , and a drain 780 . According to the first embodiments and the second embodiments, if the strained channel layer 727 has the single channel structure, the gate 740 , the source 770 , and the drain 780 may be formed on the strained channel layer 727 .
  • the gate 740 , the source 770 , and the drain 780 may be formed on each of the first strained channel layer (e.g., 550 in FIG. 6 G ) and second strained channel layer (e.g., 570 in FIG. 6 G ) of the strained channel layer 727 .
  • the gate 740 may be formed over the strained channel layer 727 .
  • the strained channel layer 727 may be divided into a first area and a second area for the gate 740 .
  • the gate 740 may be formed on the insulating material layer 730 in accordance with the first area of the strained channel layer 727 .
  • the insulating material layer 730 may be made of silicon (Si).
  • a spacer 750 may be formed on the insulating material layer 730 in a way to surround the gate 740 . In this case, the spacer 750 may expose the top of the gate 740 .
  • the source 770 and the drain 780 may be formed on the strained channel layer 727 .
  • the source 770 and the drain 780 may be formed to be isolated from the gate 740 , and may be formed to be isolated from each other.
  • contact material layers 761 and 763 may be formed within the recesses, respectively.
  • the contact material layers 761 may be formed using ion implantation and an activation technique.
  • the contact material layers 763 may be formed using an embedded technique.
  • the embedded technique may indicate an embedded SiGe SD (eSD) technique.
  • some of the contact material layers 763 may be formed using the ion implantation and the activation technique, and the remainder of the contact material layers 763 may be formed using the embedded technique.
  • the contact material layers 761 of a tensile-strained channel layer may be formed using the ion implantation and the activation technique, and the contact material layer 763 of a compressively strained channel layer may be formed using the embedded technique.
  • the device 700 may be fabricated.
  • the device 700 having the strained channel layer 727 may be fabricated using a monolithic integration method. That is, as the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 is grown on the support substrate 110 , 310 , 510 by using the hetero-epitaxy method, the growth structure 100 , 300 , 500 for a strained channel is implemented. Accordingly, the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 can be easily bonded to the top of the base substrate 220 , 420 , 620 based on the growth structure 100 , 300 , 500 . Moreover, the device 700 having the strained channel layer 727 can be easily fabricated using the growth structure 100 , 300 , 500 . Accordingly, the device 700 having improved operating performance can be fabricated.
  • the growth structure 100 , 300 , 500 for a strained channel may include the support substrate 110 , 310 , 510 , the SRB layer 120 , 320 , 520 disposed on the support substrate 110 , 310 , 510 , the base growth layer 130 , 140 , 330 , 340 , 530 , 540 grown to have one composition on the SRB layer 120 , 320 , 520 , and the strained channel layer 150 , 370 , 550 , 570 grown to have another composition on the base growth layer 130 , 140 , 330 , 340 , 530 , 540 .
  • the strained channel layer 150 , 370 , 550 , 570 may include at least one of a tensile-strained channel layer or a compressively strained channel layer.
  • the tensile-strained channel layer and the compressively strained channel layer may be disposed on the base growth layer 130 , 140 , 330 , 340 , 530 , 540 .
  • the base growth layer 130 , 140 , 330 , 340 , 530 , 540 and the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 may be made of at least one of silicon or germanium, and may be grown based on different etch rates.
  • the strained channel layer 550 , 560 , 570 , and 580 may further include the insulating member 580 interposed between the tensile-strained channel layer and the compressively strained channel layer.
  • the strained channel layer 370 , 550 , 560 , 570 , 580 may further include the etch-stop layer 360 , 560 interposed between the base growth layer 330 , 340 , 530 , 540 and the compressively strained channel layer.
  • the base growth layer 130 , 140 , 330 , 340 , 530 , 540 may include the buffer layer 130 , 330 , 430 disposed on the SRB layer 120 , 320 , 520 and the p-type layer 140 , 340 , 440 disposed on the buffer layer 130 , 330 , 430 .
  • a method of fabricating a strained channel may include steps of preparing the growth structure 100 , 300 , 500 for a strained channel and the base substrate 220 , 420 , 620 , rotating the growth structure 100 , 300 , 500 and bonding the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 to the top of the base substrate 220 , 420 , 620 , and removing the base growth layer 130 , 140 , 330 , 340 , 530 , 540 , the SRB layer 120 , 320 , 520 , and the support substrate 110 , 310 , 510 from the top of the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 by leaving the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 on the base substrate.
  • the step of bonding the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 to the top of the base substrate 220 , 420 , 620 may include steps of forming the first insulating layer 210 , 410 , 610 on the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 of the growth structure 100 , 300 , 500 , and rotating the growth structure 100 , 300 , 500 so that the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 and the first insulating layer 210 , 410 , 610 are inverted and bonding the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 to the top of the base substrate 220 , 420 , 620 through the first insulating layer 210 , 410 , 610 .
  • the base substrate 220 , 420 , 620 may include the second insulating layer 223 , 423 , 623 exposed to the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 .
  • the step of bonding the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 to the top of the base substrate 220 , 420 , 620 through the first insulating layer 210 , 410 , 610 may include the step of bonding the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 to the top of the base substrate 220 , 420 , 620 by combining the first insulating layer 210 , 410 , 610 with the second insulating layer 223 , 423 , 623 .
  • the step of forming the first insulating layer 210 , 410 , 610 may include forming the first insulating layer 210 , 410 , 610 by using a thin film deposition technique.
  • the step of removing the base growth layer 130 , 140 , 330 , 340 , 530 , 540 , the SRB layer 120 , 320 , 520 , and the support substrate 110 , 310 , 510 may be performed by using at least one of an anodizing technique, a grinding technique or an etching technique.
  • the base growth layer 130 , 140 , 330 , 340 , 530 , 540 may include the buffer layer 130 , 330 , 530 disposed on the SRB layer 120 , 320 , 520 , and the p-type layer 140 , 340 , 540 disposed on the buffer layer 130 , 330 , 530 .
  • the step of removing the base growth layer 130 , 140 , 330 , 340 , 530 , 540 , the SRB layer 120 , 320 , 520 , and the support substrate 110 , 310 , 510 may include removing the p-type layer 140 , 340 , 540 by using the anodizing technique so that the buffer layer 130 , 330 , 530 , the SRB layer 120 , 320 , 520 , and the support substrate 110 , 310 , 510 are separated from the strained channel layer 150 , 370 , 550 , 560 , 570 , 580 .
  • a method of fabricating the device 700 may include a step of forming the electrodes 740 , 770 , and 780 on the strained channel layer 727 remained on the base substrate 721 and 725 .
  • the step of forming the electrodes 740 , 770 , and 780 may include steps of forming the gate 740 on the strained channel layer 727 , and forming the source 770 and the drain 780 on the strained channel layer 727 so that the source 770 and the drain 780 are isolated from the gate 740 .
  • the strained channel layer 727 may be divided into a first area for the gate 740 and a second area for the remainder.
  • the step of forming the gate 740 may include steps of forming the insulating material layer 730 on the strained channel layer 727 , forming the gate 740 on the insulating material layer 730 in accordance with the first area, and forming, on the insulating material layer 730 , the spacer 750 surrounding the side of the gate 740 .
  • the step of forming the source 770 and the drain 780 may include steps of forming, in the second area, recesses isolated from each other, forming the contact material layers 761 and 763 within the recesses, respectively, and forming the source 770 and the drain 780 on the contact material layers 761 and 763 , respectively.
  • the step of forming the contact material layers 761 and 763 may include forming the contact material layers 761 and 763 by using at least one of ion implantation and an activation technique or an embedded technique.
  • the step of forming the contact material layers 761 and 763 may include forming at least some of the contact material layers 761 by using the ion implantation and the activation technique if the strained channel layer 727 includes a tensile-strained channel layer, and forming at least some of the contact material layers 763 by using the embedded technique if the strained channel layer 727 includes a compressively strained channel layer.
  • Expressions such as “a first,” “a second,” “the first” and “the second”, may modify corresponding elements regardless of the sequence and/or importance, and are used to only distinguish one element from the other element and do not limit corresponding elements.
  • one element e.g., a first element is “(operatively or communicatively) connected to” or “coupled with” the other (e.g., a second) element, one element may be directly connected to the other element or may be connected to the other element through another element (e.g., a third element).
  • each (e.g., module or program) of the described elements may include a single entity or a plurality of entities.
  • one or more elements or operations of the aforementioned elements may be omitted or one or more other elements or operations may be added.
  • a plurality of elements e.g., modules or programs
  • the integrated element may perform a function performed by a corresponding one of the plurality of elements before at least one function of each of the plurality of elements is integrated identically or similarly.
  • operations performed by a module, a program or another element may be executed sequentially, in parallel, iteratively or heuristically, or one or more of the operations may be executed in different order or may be omitted, or one or more other operations may be added.

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Abstract

Disclosed are a growth structure for a strained channel, and a strained channel using the same and a method of manufacturing a device using the same. The growth structure for a strained channel includes a support substrate, a strain-relaxed buffer (SRB) layer disposed on a support substrate, a base growth layer grown to have one composition on the SRB layer, and a strained channel layer grown to have another composition on the base growth layer. The strained channel layer may include at least one of a tensile-strained channel layer or a compressively strained channel layer.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
This application is based on and claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2021-0000429, filed on Jan. 4, 2021 in the Korean intellectual property office, the disclosure of which is herein incorporated by reference in its entirety.
TECHNICAL FIELD
Various embodiments relate to a growth structure for a strained channel, and a strained channel using the same and a method of manufacturing a device using the same.
BACKGROUND OF THE INVENTION
The mobility of electrons and holes in a strained material layer is significantly higher than the mobility thereof in bulk silicon. Accordingly, if a device includes a strained channel, the device will have improved operating performance. For example, the device may operate at a high speed by using low consumption power. Accordingly, there is a need for a technology for implementing a strained channel and a device having the strained channel.
SUMMARY
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Various embodiments provide a growth structure for a strained channel, and a strained channel using the same and a method of manufacturing a device using the same. Specifically, various embodiments provide a growth structure for fabricating a strained channel. Furthermore, various embodiments provide a method of implementing a strained channel by using a growth structure. Furthermore, various embodiments provide a method of fabricating a device by using a growth structure.
According to various embodiments, a growth structure for a strained channel may include a support substrate, a strain-relaxed buffer (SRB) layer disposed on a support substrate, a base growth layer grown to have one composition on the SRB layer, and a strained channel layer grown to have another composition on the base growth layer.
According to various embodiments, a method of fabricating a strained channel may include preparing a growth structure for the strained channel and a base substrate, rotating the growth structure and bonding a strained channel layer to the top of the base substrate, and removing a base growth layer, an SRB layer, and a support substrate from the top of the strained channel layer by leaving the strained channel layer on the base substrate.
According to various embodiments, a method of manufacturing a device using a strained channel may include forming electrodes on a strained channel layer remained on a base substrate.
According to various embodiments, a device having a strained channel layer can be fabricated by using a monolithic integration method. That is, a growth structure for a strained channel is implemented because a strained channel layer is grown on a support substrate by using a hetero-epitaxy method. The strained channel layer can be easily bonded on a base substrate based on such a growth structure. Moreover, a device having the strained channel layer can be fabricated by using the growth structure. Accordingly, a device having improved operating performance can be fabricated.
DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a diagram illustrating a growth structure for a strained channel according to first embodiments.
FIGS. 2A to 2G are diagrams illustrating a method of fabricating a strained channel according to the first embodiments.
FIG. 3 is a diagram illustrating a growth structure for a strained channel according to second embodiments.
FIGS. 4A to 4H are diagrams illustrating a method of fabricating a strained channel according to the second embodiments.
FIGS. 5A and 5B are diagrams illustrating a growth structure for a strained channel according to third embodiments.
FIGS. 6A to 6H are diagrams illustrating a method of fabricating a strained channel according to the third embodiments.
FIGS. 7A to 7E are diagrams illustrating a method of manufacturing a device according to various embodiments.
 DETAILED DESCRIPTION
While illustrative embodiments have been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.
Hereinafter, various embodiments of this document are described with reference to the accompanying drawings.
FIG. 1 is a diagram illustrating a growth structure 100 for a strained channel according to first embodiments.
Referring to FIG. 1 , the growth structure 100 for a strained channel according to the first embodiments may include a support substrate 110, a strain-relaxed buffer (SRB) layer 120, a base growth layer 130 and 140, and a strained channel layer 150.
The support substrate 110 may support the SRB layer 120, the base growth layer 130 and 140, and the strained channel layer 150. For example, the support substrate 110 may be made of silicon (Si).
The SRB layer 120 may be disposed on the support substrate 110. In this case, the SRB layer 120 may be a lattice mismatch with the strained channel layer 150. In other words, a lattice constant of the SRB layer 120 may be different from a lattice constant of the strained channel layer 150. Accordingly, a stain may be applied to the strained channel layer 150 through the SRB layer 120.
The base growth layer 130 and 140 and the strained channel layer 150 may be grown on the SRB layer 120 by using a hetero-epitaxy method. For example, the base growth layer 130 and 140 and the strained channel layer 150 may be made of a silicon (Si)-germanium (Ge) material. In this case, the base growth layer 130 and 140 and the strained channel layer 150 may be grown on the SRB layer 120 based on different etch rates.
The base growth layer 130 and 140 may be disposed on the SRB layer 120. In this case, the base growth layer 130 and 140 may be grown to have a first composition (e.g., y) on the SRB layer 120. For example, the base growth layer 130 and 140 may be made of at least one of silicon (Si1-y) or germanium (Gey). Furthermore, the base growth layer 130 and 140 may include a plurality of layers. For example, the base growth layer 130 and 140 may include a buffer layer 130 and a p-type layer 140. The buffer layer 130 may be disposed on the SRB layer 120, and the p-type layer 140 may be disposed on the buffer layer 130. For example, the buffer layer 130 may be denoted as a germanium (Ge)-rich silicon-germanium (Si1-yGey) buffer layer. The p-type layer 140 may be denoted as a p-type germanium (Ge)-rich silicon-germanium (Si1-yGey) material layer.
The strained channel layer 150 may be disposed on the base growth layer 130 and 140. In this case, the strained channel layer 150 may be grown as a single channel structure. That is, as a strain is applied to the strained channel layer 150 by the SRB layer 120, the strained channel layer 150 may be grown to have a second composition (e.g., z) on the base growth layer 130 and 140. In this case, the strained channel layer 150 may be denoted as a tensile-strained channel layer. For example, the strained channel layer 150 may be made of at least one of silicon (Si1-z) or germanium (Gez).
FIGS. 2A to 2G are diagrams illustrating a method of fabricating a strained channel according to the first embodiments.
First, after the growth structure 100 for a strained channel, such as that illustrated in FIG. 1 , and a base substrate 220 are prepared, as illustrated in FIGS. 2A to 2D, the growth structure 100 may be bonded to the top of the base substrate 220. In this case, the growth structure 100 may be bonded to the top of the base substrate 220 by using a monolithic integration method.
As illustrated in FIGS. 2A and 2B, a first insulating layer 210 may be formed on the strained channel layer 150 of the growth structure 100. In this case, the first insulating layer 210 may be formed on an strained channel layer 150 by using a thin film deposition technique. Specifically, as illustrated in FIG. 2A, the growth structure 100 may be dipped into a bath B containing a solvent. A voltage may be applied to the growth structure 100 through a power source S. Accordingly, as illustrated in FIG. 2B, the first insulating layer 210 may be formed on the strained channel layer 150.
Next, as illustrated in FIG. 2C, the growth structure 100 may be rotated. That is, the growth structure 100 may be rotated so that the first insulating layer 210 is directed toward the base substrate 220, in other words, the base growth layer 130 and 140 and the strained channel layer 150 are inverted. The base substrate 220 may include a support substrate 221 and a second insulating layer 223 disposed on the support substrate 221. In this case, the second insulating layer 223 may be exposed to the growth structure 100, that is, the strained channel layer 150. Accordingly, the first insulating layer 210 may face the second insulating layer 223, the strained channel layer 150 may be disposed on the first insulating layer 210, and the base growth layer 130 and 140 may be disposed on the strained channel layer 150. In this case, the p-type layer 140 may be disposed on the strained channel layer 150, and the buffer layer 130 may be disposed on the p-type layer 140. Furthermore, the SRB layer 120 may be disposed on the base growth layer 130 and 140, and the support substrate 110 may be disposed on the SRB layer 120.
Next, as illustrated in FIG. 2D, the growth structure 100 may be bonded to the top of the base substrate 220. That is, the strained channel layer 150 may be bonded to the top of the base substrate 220 through the first insulating layer 210. In this case, as the first insulating layer 210 is combined with the second insulating layer 223, an insulating layer 225 may be formed between the strained channel layer 150 and the support substrate 221 and the strained channel layer 150 may be bonded to the top of the base substrate 220.
Finally, the base growth layer 130 and 140, the SRB layer 120, and the support substrate 110 may be removed from the top of the strained channel layer 150. In this case, the base growth layer 130 and 140, the SRB layer 120, and the support substrate 110 may be removed from the top of the strained channel layer 150 by using at least one of an anodizing technique, a grinding technique or an etching technique. According to an embodiment, as illustrated in FIG. 2E, the p-type layer 140 may be removed on the strained channel layer 150 by using the anodizing technique. Optionally, a surface of the strained channel layer 150 may be mechanically grinded. Accordingly, the buffer layer 130, the SRB layer 120, and the support substrate 110 may be separated from the strained channel layer 150. As a result, as illustrated in FIG. 2G, the strained channel layer 150 may remain. According to another embodiment, as illustrated in FIG. 2F, the support substrate 110, the SRB layer 120, and the base growth layer 130 and 140 may be sequentially removed using the grinding technique and the etching technique. As a result, as illustrated in FIG. 2G, the strained channel layer 150 may remain.
According to the first embodiments, as illustrated in FIG. 2G, a strained channel substrate 220′ may be fabricated. The strained channel substrate 220′ may include the support substrate 221, the insulating layer 225 disposed on the support substrate 221, and the strained channel layer 150 disposed on the insulating layer 225. In this case, the strained channel layer 150 may represent a strained channel having a single channel structure.
FIG. 3 is a diagram illustrating a growth structure 300 for a strained channel according to second embodiments.
Referring to FIG. 3 , the growth structure 300 for a strained channel according to the second embodiments may include a support substrate 310, a strain-relaxed buffer (SRB) 320, a base growth layer 330 and 340, an etch-stop layer 360, and a strained channel layer 370.
The support substrate 310 may support the SRB layer 320, the base growth layer 330 and 340, the etch-stop layer 360, and the strained channel layer 370. For example, the support substrate 310 may be made of silicon (Si).
The SRB layer 320 may be disposed on the support substrate 310. In this case, the SRB layer 320 may be a lattice mismatch with the strained channel layer 370. In other words, a lattice constant of the SRB layer 320 may be different from a lattice constant of the strained channel layer 370. Accordingly, a strain may be applied to the strained channel layer 370 through the SRB layer 320.
The base growth layer 330 and 340 and the strained channel layer 370 may be grown on the SRB layer 320 by using a hetero-epitaxy method. For example, the base growth layer 330 and 340 and the strained channel layer 370 may be made of a silicon (Si)-germanium (Ge) material. In this case, the base growth layer 330 and 340 and the strained channel layer 370 may be grown on the SRB layer 320 based on different etch rates.
The base growth layer 330 and 340 may be disposed on the SRB layer 320. In this case, the base growth layer 330 and 340 may be grown to have a first composition (e.g., y) on the SRB layer 320. For example, the base growth layer 330 and 340 may be made of at least one of silicon (Si1-y) or germanium (Gey). Furthermore, the base growth layer 330 and 340 may include a plurality of layers. For example, the base growth layer 330 and 340 may include a buffer layer 330 and a p-type layer 340. The buffer layer 330 may be disposed on the SRB layer 320. The p-type layer 340 may be disposed on the buffer layer 330. For example, the buffer layer 330 may be denoted as a germanium (Ge)-rich silicon-germanium (Si1-yGey) buffer layer. The p-type layer 340 may be denoted as a p-type germanium (Ge)-rich silicon-germanium (Si1-yGey) material layer.
The etch-stop layer 360 may be disposed on the base growth layer 330 and 340.
The strained channel layer 370 may be disposed on the etch-stop layer 360. In this case, the strained channel layer 370 may be grown as a single channel structure. That is, as a strain is applied to the strained channel layer 370 by the SRB layer 320, the strained channel layer 370 may be grown to have a third composition (e.g., x) on the etch-stop layer 360. In this case, the strained channel layer 370 may be denoted as a compressively-strained channel layer. For example, the strained channel layer 370 may be made of at least one of silicon (Si1-x) or germanium (Gex).
FIGS. 4A to 4H are diagrams illustrating a method of fabricating a strained channel according to the second embodiments.
First, after the growth structure 300 for a strained channel, such as that illustrated in FIG. 3 , and a base substrate 420 are prepared, as illustrated in FIGS. 4A to 4D, the growth structure 300 may be bonded to the top of the base substrate 420. In this case, the growth structure 300 may be bonded to the top of the base substrate 420 by using a monolithic integration method.
As illustrated in FIGS. 4A and 4B, a first insulating layer 410 may be formed on the strained channel layer 370 of the growth structure 300. In this case, the first insulating layer 410 may be formed on an the strained channel layer 370 by using a thin film deposition technique. Specifically, as illustrated in FIG. 4A, the growth structure 300 may be dipped into a bath B containing a solvent, and a voltage may be applied to the growth structure 300 through a power source S. Accordingly, as illustrated in FIG. 4B, the first insulating layer 410 may be formed on the strained channel layer 370.
Next, as illustrated in FIG. 4C, the growth structure 300 may be rotated. That is, the growth structure 300 may be rotated so that the first insulating layer 410 is directed toward the base substrate 420, in other words, the base growth layer 330 and 340 and the strained channel layer 370 are inverted. The base substrate 420 may include a support substrate 421 and a second insulating layer 423 disposed on the support substrate 421. In this case, the second insulating layer 423 may be exposed to the growth structure 300, that is, the strained channel layer 370. Accordingly, the first insulating layer 410 may face the second insulating layer 423, the strained channel layer 370 may be disposed on the first insulating layer 410, and the base growth layer 330 and 340 may be disposed on the strained channel layer 370. In this case, the etch-stop layer 360 may be disposed on the strained channel layer 370, the p-type layer 340 may be disposed on the etch-stop layer 360, and the buffer layer 330 may be disposed on the p-type layer 340. Furthermore, the SRB layer 320 may be disposed on the base growth layer 330 and 340, and the support substrate 310 may be disposed on the SRB layer 320.
Next, as illustrated in FIG. 4D, the growth structure 300 may be bonded to the top of the base substrate 420. That is, the strained channel layer 370 may be bonded to the top of the base substrate 420 through the first insulating layer 410. In this case, as the first insulating layer 410 is combined with the second insulating layer 423, an insulating layer 425 may be formed between the strained channel layer 370 and the support substrate 421, and the strained channel layer 370 may be bonded to the top of the base substrate 420.
Finally, the etch-stop layer 360, the base growth layer 330 and 340, the SRB layer 320, and the support substrate 310 may be removed from the top of the strained channel layer 370. In this case, the base growth layer 330 and 340, the SRB layer 320, and the support substrate 310 may be removed from the top of the etch-stop layer 360 by using at least one of an anodizing technique, a grinding technique or an etching technique. According to an embodiment, as illustrated in FIG. 4E, the p-type layer 340 may be removed on the etch-stop layer 360 by using the anodizing technique. Optionally, a surface of the etch-stop layer 360 may be mechanically grinded. Accordingly, the buffer layer 330, the SRB layer 320, and the support substrate 310 may be separated from the etch-stop layer 360. As a result, as illustrated in FIG. 4G, the etch-stop layer 360 and the strained channel layer 370 may remain. According to another embodiment, as illustrated in FIG. 4F, the support substrate 310, the SRB layer 320, and the base growth layer 330 and 340 may be sequentially removed by using the grinding technique and the etching technique. As a result, as illustrated in FIG. 4G, the etch-stop layer 360 and the strained channel layer 370 may remain. Thereafter, as illustrated in FIG. 4H, the etch-stop layer 360 may be removed from the top of the strained channel layer 370.
According to the second embodiments, as illustrated in FIG. 4H, a strained channel substrate 420′ may be fabricated. The strained channel substrate 420′ may include the support substrate 421, the insulating layer 425 disposed on the support substrate 421, and the strained channel layer 370 disposed on the insulating layer 425. In this case, the strained channel layer 370 may represent a strained channel having a single channel structure.
FIGS. 5A and 5B are diagrams illustrating a growth structure 500 for a strained channel according to third embodiments.
Referring to FIGS. 5A and 5B, the growth structure 500 for a strained channel according to the third embodiments may include a support substrate 510, an SRB layer 520, a base growth layer 530 and 540, and a strained channel layer 550, 560, 570, and 580.
The support substrate 510 may support the SRB layer 520, the base growth layer 530 and 540, and the strained channel layer 550, 560, 570, and 580. For example, the support substrate 510 may be made of silicon (Si).
The SRB layer 520 may be disposed on the support substrate 510. In this case, the SRB layer 520 may be a lattice mismatch with the strained channel layer 570. In other words, a lattice constant of the SRB layer 520 may be different from a lattice constant of the strained channel layer 570. Accordingly, a strain may be applied to the strained channel layer 570 through the SRB layer 520.
The base growth layer 530 and 540 and the strained channel layer 570 may be grown on the SRB layer 520 by using a hetero-epitaxy method. For example, the base growth layer 530 and 540 and the strained channel layer 570 may be made of a silicon (Si)-germanium (Ge) material. In this case, the base growth layer 530 and 540 and the strained channel layer 570 may be grown on the SRB layer 520 based on different etch rates.
The base growth layer 530 and 540 may be disposed on the SRB layer 520. In this case, the base growth layer 530 and 540 may be grown to have a first composition (e.g., y) on the SRB layer 520. For example, the base growth layer 530 and 540 may be made of at least one of silicon (Si1-y) or germanium (Gey). Furthermore, the base growth layer 530 and 540 may include a plurality of layers. For example, the base growth layer 530 and 540 may include a buffer layer 530 and a p-type layer 540. The buffer layer 530 may be disposed on the SRB layer 520. The p-type layer 540 may be disposed on the buffer layer 530. For example, the buffer layer 530 may be denoted as a germanium (Ge)-rich silicon-germanium (Si1-yGey) buffer layer. The p-type layer 540 may be denoted as a p-type germanium (Ge)-rich silicon-germanium (Si1-yGey) material layer.
The strained channel layer 550, 560, 570, and 580 may be disposed on the base growth layer 530 and 540. In this case, the strained channel layer 550, 560, 570, and 580 may be grown as a dual channel structure. That is, as a strain is applied to the strained channel layer 550, 560, 570, and 580 by the SRB layer 220, the strained channel layer 550, 560, 570, and 580 may be grown to have a second composition (e.g., z) and a third composition (e.g., x) on the base growth layer 530 and 540. The strained channel layer 550, 560, 570, and 580 may include a first strained channel layer 550, an etch-stop layer 560, and a second strained channel layer 570. In some embodiments, the strained channel layer 550, 560, 570, and 580 may further include an insulating member 580.
The first strained channel layer 550 may be disposed on some area of the base growth layer 530 and 540. In this case, the first strained channel layer 550 may be grown to have a second composition (e.g., z) on some area of the base growth layer 530 and 540. In this case, the first strained channel layer 550 may be denoted as a tensile-strained channel layer. For example, the first strained channel layer 550 may be made of at least one of silicon (Si1-z) or germanium (Gez).
The etch-stop layer 560 may be disposed on another area of the base growth layer 530 and 540. The second strained channel layer 570 may be disposed on the etch-stop layer 560. In this case, the second strained channel layer 570 may be grown to have a third composition (e.g., x) on the etch-stop layer 560. In this case, the second strained channel layer 570 may be denoted as a compressively strained channel layer. For example, the second strained channel layer 570 may be made of at least one of silicon (Si1-x) or germanium (Gex).
The insulating member 580 may be interposed between the first strained channel layer 550 and the etch-stop layer 560 and between the first strained channel layer 550 and the second strained channel layer 570 on the base growth layer 530 and 540.
FIGS. 6A to 6H are diagrams illustrating a method of fabricating a strained channel according to the third embodiments.
First, after the growth structure 500 for a strained channel, such as that illustrated in FIG. 5A or 5B, and a base substrate 620 are prepared, as illustrated in FIGS. 6A to 6D, the growth structure 500 may be bonded to the top of the base substrate 620. In this case, the growth structure 500 may be bonded to the top of the base substrate 620 by using a monolithic integration method.
As illustrated in FIGS. 6A and 6B, a first insulating layer 610 may be formed on the strained channel layer 550, 560, 570, and 580 of the growth structure 500. In this case, the first insulating layer 610 may be formed on an strained channel layer 550, 560, 570, and 580 by using a thin film deposition technique. Specifically, as illustrated in FIG. 6A, the growth structure 500 may be dipped into a bath B containing a solvent, and a voltage may be applied to the growth structure 500 through a power source S. Accordingly, as illustrated in FIG. 6B, the first insulating layer 610 may be formed on the strained channel layer 550, 560, 570, and 580. In this case, the first insulating layer 610 may be formed on surfaces of the first strained channel layer 550 and the second strained channel layer 570. In some embodiments, if the strained channel layer 550, 560, 570, and 580 further includes the insulating member 580, the first insulating layer 610 may be formed on surfaces of the first strained channel layer 550, the insulating member 580, and the second strained channel layer 570.
Next, as illustrated in FIG. 6C, the growth structure 500 may be rotated. That is, the growth structure 500 may be rotated so that the first insulating layer 610 is directed toward the base substrate 620, in other words, the base growth layer 530 and 540 and the strained channel layer 550, 560, 570, and 580 are inverted. The base substrate 620 may include a support substrate 621 and a second insulating layer 623 disposed on the support substrate 621. In this case, the second insulating layer 623 may be exposed to the growth structure 500, that is, the strained channel layer 550, 560, 570, and 580. Accordingly, the first insulating layer 610 may face the second insulating layer 623, the strained channel layer 550, 560, 570, and 580 may be disposed on the first insulating layer 610, and the base growth layer 530 and 540 may be disposed on the strained channel layer 550, 560, 570, and 580. In this case, the etch-stop layer 560 may be disposed on the second strained channel layer 570, the p-type layer 540 may be disposed on the etch-stop layer 560 and the first strained channel layer 550, and the buffer layer 530 may be disposed on the p-type layer 540. In some embodiments, if the strained channel layer 550, 560, 570, and 580 further includes the insulating member 580, the p-type layer 540 may be disposed on the etch-stop layer 560, the insulating member 580, and the first strained channel layer 550, and the buffer layer 530 may be disposed on the p-type layer 540. Furthermore, the SRB layer 520 may be disposed on the base growth layer 530 and 540, and the support substrate 510 may be disposed on the SRB layer 520.
Next, as illustrated in FIG. 6D, the growth structure 500 may be bonded to the top of the base substrate 620. That is, the strained channel layer 550, 560, 570, and 580 may be bonded to the top of the base substrate 620 through the first insulating layer 610. In this case, as the first insulating layer 610 is combined with the second insulating layer 623, an insulating layer 625 may be formed between the strained channel layer 550, 560, 570, and 580 and the support substrate 621, and the strained channel layer 550, 560, 570, and 580 may be bonded to the top of the base substrate 620.
Finally, the etch-stop layer 560, the base growth layer 530 and 540, the SRB layer 520 and the support substrate 510 may be removed from the top of the strained channel layer 550, 560, 570, and 580. In this case, the base growth layer 530 and 540, the SRB layer 520, and the support substrate 510 may be removed from the top of the strained channel layer 550, 560, 570, and 580 by using at least one of an anodizing technique, a grinding technique or an etching technique. According to an embodiment, as illustrated in FIG. 6E, the p-type layer 540 may be removed from the top of the etch-stop layer 560 by using the anodizing technique. Optionally, a surface of the etch-stop layer 560 may be mechanically grinded. Accordingly, the buffer layer 530, the SRB layer 520, and the support substrate 510 may be separated from the strained channel layer 550, 560, 570, and 580. As a result, as illustrated in FIG. 6G, the etch-stop layer 560 and the second strained channel layer 570 may remain. According to another embodiment, as illustrated in FIG. 6F, the support substrate 510, the SRB layer 520, and the base growth layer 530 and 540 may be sequentially removed using the grinding technique and the etching technique. As a result, as illustrated in FIG. 6G, the etch-stop layer 560 and the second strained channel layer 570 may remain. Thereafter, as illustrated in FIG. 6H, the etch-stop layer 560 may be removed from the top of the second strained channel layer 570. In this case, a part of the first strained channel layer 550 may be removed along with the etch-stop layer 560 so that the first strained channel layer 550 has the same height as the second strained channel layer 570. In some embodiments, if the strained channel layer 550, 560, 570, and 580 further includes the insulating member 580, a part of the insulating member 580 may be further removed along with the etch-stop layer 560 so that the insulating member 580 has the same height as the second strained channel layer 570.
According to the third embodiments, as illustrated in FIG. 6H, a strained channel substrate 620′ may be fabricated. The strained channel substrate 620′ may include the support substrate 621, the insulating layer 625 disposed on the support substrate 621, and the strained channel layers 550, 570, and 580 disposed on the insulating layer 625. In this case, the strained channel layers 550, 570, and 580 may represent strained channels having a dual channel structure. That is, the strained channel layers 550, 570, and 580 may include the first strained channel layer 550 and the second strained channel layer 570 disposed on the insulating layer 625. In some embodiments, the strained channel layers 550, 570, and 580 may further include the insulating member 580 interposed between the first strained channel layer 550 and the second strained channel layer 570 on the insulating layer 625.
FIGS. 7A to 7E are diagrams illustrating a method of manufacturing a device 700 according to various embodiments.
As in the aforementioned embodiments, after a strained channel substrate 720 (e.g., 220′ in FIG. 2F, 420 ′ in FIG. 4G, or 620′ in FIG. 6G) is fabricated, as illustrated in FIGS. 7A to 7E, electrodes 740, 770, and 780 may be formed on a strained channel layer 727 (e.g., 150 in FIG. 2F, 370 in FIG. 4G, 550 and 570 in FIG. 6F). In this case, the strained channel substrate 720 may include a base substrate 721 and 725, that is, a support substrate 721 (e.g., 221 in FIG. 2F, 421 in FIG. 4G, 621 in FIG. 6F), an insulating layer 725 (e.g., 225 in FIG. 2F, 425 in FIG. 4G, 625 in FIG. 6F) disposed on the support substrate 721, and the strained channel layer 727. The electrodes 740, 770, and 780 may include a gate 740, a source 770, and a drain 780. According to the first embodiments and the second embodiments, if the strained channel layer 727 has the single channel structure, the gate 740, the source 770, and the drain 780 may be formed on the strained channel layer 727. According to the third embodiments, if the strained channel layer 727 has the dual channel structure, the gate 740, the source 770, and the drain 780 may be formed on each of the first strained channel layer (e.g., 550 in FIG. 6G) and second strained channel layer (e.g., 570 in FIG. 6G) of the strained channel layer 727.
First, as illustrated in FIGS. 7A and 7B, the gate 740 may be formed over the strained channel layer 727. In this case, the strained channel layer 727 may be divided into a first area and a second area for the gate 740. Specifically, as illustrated in FIG. 7A, after an insulating material layer 730 is formed on the strained channel layer 727, the gate 740 may be formed on the insulating material layer 730 in accordance with the first area of the strained channel layer 727. For example, the insulating material layer 730 may be made of silicon (Si). Thereafter, as illustrated in FIG. 7B, a spacer 750 may be formed on the insulating material layer 730 in a way to surround the gate 740. In this case, the spacer 750 may expose the top of the gate 740.
Next, as illustrated in one of FIG. 7C, 7D or 7E, the source 770 and the drain 780 may be formed on the strained channel layer 727. In this case, the source 770 and the drain 780 may be formed to be isolated from the gate 740, and may be formed to be isolated from each other. Specifically, after recesses isolated from each other are formed in the second area of the strained channel layer 727, contact material layers 761 and 763 may be formed within the recesses, respectively. According to an embodiment, as illustrated in FIG. 7C, the contact material layers 761 may be formed using ion implantation and an activation technique. According to another embodiment, as illustrated in FIG. 7D, the contact material layers 763 may be formed using an embedded technique. For example, the embedded technique may indicate an embedded SiGe SD (eSD) technique. According to still another embodiment, as illustrated in FIG. 7E, some of the contact material layers 763 may be formed using the ion implantation and the activation technique, and the remainder of the contact material layers 763 may be formed using the embedded technique. Specifically, if the strained channel layer 727 has a dual channel structure, the contact material layers 761 of a tensile-strained channel layer may be formed using the ion implantation and the activation technique, and the contact material layer 763 of a compressively strained channel layer may be formed using the embedded technique.
According to various embodiments, as illustrated in one of FIG. 7C, 7D or 7E, the device 700 may be fabricated.
According to various embodiments, the device 700 having the strained channel layer 727 may be fabricated using a monolithic integration method. That is, as the strained channel layer 150, 370, 550, 560, 570, 580 is grown on the support substrate 110, 310, 510 by using the hetero-epitaxy method, the growth structure 100, 300, 500 for a strained channel is implemented. Accordingly, the strained channel layer 150, 370, 550, 560, 570, 580 can be easily bonded to the top of the base substrate 220, 420, 620 based on the growth structure 100, 300, 500. Moreover, the device 700 having the strained channel layer 727 can be easily fabricated using the growth structure 100, 300, 500. Accordingly, the device 700 having improved operating performance can be fabricated.
The growth structure 100, 300, 500 for a strained channel according to various embodiments may include the support substrate 110, 310, 510, the SRB layer 120, 320, 520 disposed on the support substrate 110, 310, 510, the base growth layer 130, 140, 330, 340, 530, 540 grown to have one composition on the SRB layer 120, 320, 520, and the strained channel layer 150, 370, 550, 570 grown to have another composition on the base growth layer 130, 140, 330, 340, 530, 540.
According to various embodiments, the strained channel layer 150, 370, 550, 570 may include at least one of a tensile-strained channel layer or a compressively strained channel layer.
According to various embodiments, the tensile-strained channel layer and the compressively strained channel layer may be disposed on the base growth layer 130, 140, 330, 340, 530, 540.
According to various embodiments, the base growth layer 130, 140, 330, 340, 530, 540 and the strained channel layer 150, 370, 550, 560, 570, 580 may be made of at least one of silicon or germanium, and may be grown based on different etch rates.
According to various embodiments, the strained channel layer 550, 560, 570, and 580 may further include the insulating member 580 interposed between the tensile-strained channel layer and the compressively strained channel layer.
According to various embodiments, the strained channel layer 370, 550, 560, 570, 580 may further include the etch- stop layer 360, 560 interposed between the base growth layer 330, 340, 530, 540 and the compressively strained channel layer.
According to various embodiments, the base growth layer 130, 140, 330, 340, 530, 540 may include the buffer layer 130, 330, 430 disposed on the SRB layer 120, 320, 520 and the p- type layer 140, 340, 440 disposed on the buffer layer 130, 330, 430.
A method of fabricating a strained channel according to various embodiments may include steps of preparing the growth structure 100, 300, 500 for a strained channel and the base substrate 220, 420, 620, rotating the growth structure 100, 300, 500 and bonding the strained channel layer 150, 370, 550, 560, 570, 580 to the top of the base substrate 220, 420, 620, and removing the base growth layer 130, 140, 330, 340, 530, 540, the SRB layer 120, 320, 520, and the support substrate 110, 310, 510 from the top of the strained channel layer 150, 370, 550, 560, 570, 580 by leaving the strained channel layer 150, 370, 550, 560, 570, 580 on the base substrate.
According to various embodiments, the step of bonding the strained channel layer 150, 370, 550, 560, 570, 580 to the top of the base substrate 220, 420, 620 may include steps of forming the first insulating layer 210, 410, 610 on the strained channel layer 150, 370, 550, 560, 570, 580 of the growth structure 100, 300, 500, and rotating the growth structure 100, 300, 500 so that the strained channel layer 150, 370, 550, 560, 570, 580 and the first insulating layer 210, 410, 610 are inverted and bonding the strained channel layer 150, 370, 550, 560, 570, 580 to the top of the base substrate 220, 420, 620 through the first insulating layer 210, 410, 610.
According to various embodiments, the base substrate 220, 420, 620 may include the second insulating layer 223, 423, 623 exposed to the strained channel layer 150, 370, 550, 560, 570, 580.
According to various embodiments, the step of bonding the strained channel layer 150, 370, 550, 560, 570, 580 to the top of the base substrate 220, 420, 620 through the first insulating layer 210, 410, 610 may include the step of bonding the strained channel layer 150, 370, 550, 560, 570, 580 to the top of the base substrate 220, 420, 620 by combining the first insulating layer 210, 410, 610 with the second insulating layer 223, 423, 623.
According to various embodiments, the step of forming the first insulating layer 210, 410, 610 may include forming the first insulating layer 210, 410, 610 by using a thin film deposition technique.
According to various embodiments, the step of removing the base growth layer 130, 140, 330, 340, 530, 540, the SRB layer 120, 320, 520, and the support substrate 110, 310, 510 may be performed by using at least one of an anodizing technique, a grinding technique or an etching technique.
According to various embodiments, the base growth layer 130, 140, 330, 340, 530, 540 may include the buffer layer 130, 330, 530 disposed on the SRB layer 120, 320, 520, and the p- type layer 140, 340, 540 disposed on the buffer layer 130, 330, 530.
According to various embodiments, the step of removing the base growth layer 130, 140, 330, 340, 530, 540, the SRB layer 120, 320, 520, and the support substrate 110, 310, 510 may include removing the p- type layer 140, 340, 540 by using the anodizing technique so that the buffer layer 130, 330, 530, the SRB layer 120, 320, 520, and the support substrate 110, 310, 510 are separated from the strained channel layer 150, 370, 550, 560, 570, 580.
A method of fabricating the device 700 according to various embodiments may include a step of forming the electrodes 740, 770, and 780 on the strained channel layer 727 remained on the base substrate 721 and 725.
According to various embodiments, the step of forming the electrodes 740, 770, and 780 may include steps of forming the gate 740 on the strained channel layer 727, and forming the source 770 and the drain 780 on the strained channel layer 727 so that the source 770 and the drain 780 are isolated from the gate 740.
According to various embodiments, the strained channel layer 727 may be divided into a first area for the gate 740 and a second area for the remainder.
According to various embodiments, the step of forming the gate 740 may include steps of forming the insulating material layer 730 on the strained channel layer 727, forming the gate 740 on the insulating material layer 730 in accordance with the first area, and forming, on the insulating material layer 730, the spacer 750 surrounding the side of the gate 740.
According to various embodiments, the step of forming the source 770 and the drain 780 may include steps of forming, in the second area, recesses isolated from each other, forming the contact material layers 761 and 763 within the recesses, respectively, and forming the source 770 and the drain 780 on the contact material layers 761 and 763, respectively.
According to various embodiments, the step of forming the contact material layers 761 and 763 may include forming the contact material layers 761 and 763 by using at least one of ion implantation and an activation technique or an embedded technique.
According to various embodiments, the step of forming the contact material layers 761 and 763 may include forming at least some of the contact material layers 761 by using the ion implantation and the activation technique if the strained channel layer 727 includes a tensile-strained channel layer, and forming at least some of the contact material layers 763 by using the embedded technique if the strained channel layer 727 includes a compressively strained channel layer.
Various embodiments of this document and the terms used in the embodiments are not intended to limit the technology described in this document to a specific embodiment, but should be construed as including various changes, equivalents and/or alternatives of a corresponding embodiment. Regarding the description of the drawings, similar reference numerals may be used in similar elements. An expression of the singular number may include an expression of the plural number unless clearly defined otherwise in the context. In this document, an expression, such as “A or B”, “at least one of A and/or B”, “A, B or C” or “at least one of A, B and/or C”, may include all of possible combinations of listed items together. Expressions, such as “a first,” “a second,” “the first” and “the second”, may modify corresponding elements regardless of the sequence and/or importance, and are used to only distinguish one element from the other element and do not limit corresponding elements. When it is described that one (e.g., a first) element is “(operatively or communicatively) connected to” or “coupled with” the other (e.g., a second) element, one element may be directly connected to the other element or may be connected to the other element through another element (e.g., a third element).
According to various embodiments, each (e.g., module or program) of the described elements may include a single entity or a plurality of entities. According to various embodiments, one or more elements or operations of the aforementioned elements may be omitted or one or more other elements or operations may be added. Alternatively or additionally, a plurality of elements (e.g., modules or programs) may be integrated into a single element. In such a case, the integrated element may perform a function performed by a corresponding one of the plurality of elements before at least one function of each of the plurality of elements is integrated identically or similarly. According to various embodiments, operations performed by a module, a program or another element may be executed sequentially, in parallel, iteratively or heuristically, or one or more of the operations may be executed in different order or may be omitted, or one or more other operations may be added.

Claims (7)

The invention claimed is:
1. A growth structure for a strained channel, comprising: a support substrate;
a strain-relaxed buffer (SRB) layer disposed on a support substrate;
a base growth layer grown to have a first composition on the SRB layer, wherein the base growth layer comprises: a buffer layer disposed on the SRB layer and a p-type layer disposed on the buffer layer,
a first strained channel layer grown to have a second composition on the base growth layer;
a first etch-stop layer adjacent to the first strained channel layer; and
a second strained channel layer grown to have a third composition on the first etch-stop layer, wherein the second strained channel layer is adjacent to the first strained channel layer.
2. The growth structure of claim 1, wherein the first strained channel layer comprises at least one of a tensile-strained channel layer or a compressively strained channel layer.
3. The growth structure of claim 2, wherein the tensile-strained channel layer and the compressively strained channel layer are disposed on the base growth layer.
4. The growth structure of claim 1, wherein the base growth layer and the first strained channel layer are made of at least one of silicon or germanium and are grown based on different etch rates.
5. The growth structure of claim 3, wherein the first strained channel layer further comprises an insulating member interposed between the tensile-strained channel layer and the compressively strained channel layer.
6. The growth structure of claim 2, wherein the first strained channel layer further comprises a second etch-stop layer interposed between the base growth layer and the compressively strained channel layer.
7. The growth structure of claim 1,
further comprising an insulating member interposed between the first strained channel layer and the first etch stop layer, and between the first strained channel layer and the second strained channel layer on the base growth layer.
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