US12212325B2 - Low power quadrature phase detector - Google Patents

Low power quadrature phase detector Download PDF

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Publication number
US12212325B2
US12212325B2 US17/857,161 US202217857161A US12212325B2 US 12212325 B2 US12212325 B2 US 12212325B2 US 202217857161 A US202217857161 A US 202217857161A US 12212325 B2 US12212325 B2 US 12212325B2
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clock signal
switch
transistor
node
electrode
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US20230113143A1 (en
Inventor
Fong-Wen Lee
Wen-Chieh Wang
Yu-Hsin Lin
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MediaTek Inc
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MediaTek Inc
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Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, FONG-WEN, LIN, YU-HSIN, WANG, WEN-CHIEH
Priority to EP22186206.3A priority patent/EP4167487A1/en
Priority to TW111131905A priority patent/TWI858381B/en
Priority to CN202211028023.4A priority patent/CN115967378A/en
Publication of US20230113143A1 publication Critical patent/US20230113143A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
    • H03D3/009—Compensating quadrature phase or amplitude imbalances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
    • G01R25/005—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0082—Quadrature arrangements

Definitions

  • a quadrature phase detector is usually provided to detect a phase difference between an in-phase clock signal and a quadrature clock signal, and a detection result of the quadrature phase detector may be used by a clock signal generator or a delay element to adjust the phase of the in-phase clock signal or the quadrature clock signal.
  • the conventional quadrature phase detector is usually implemented by using active devices such as XOR gates, however, using XOR gates may increase the power consumption.
  • the quadrature phase detector is designed to detect four clock signals whose phases are 0 degree, 90 degrees, 180 degrees and 270 degrees
  • four sets of circuits are designed to detect the phase difference between clock signals with 0 degree and 90 degrees, the phase difference between clock signals with 90 degrees and 180 degrees, the phase difference between clock signals with 180 degrees and 270 degrees, and the phase difference between clock signals with 270 degrees and 0 degree.
  • a quadrature phase detector comprising a detection circuit.
  • the detection circuit comprises a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.
  • a circuitry comprising a clock signal generator, a detection circuit and a control circuit.
  • the clock signal generator is configured to generate a first clock signal and a second clock signal.
  • the detection circuit comprises a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.
  • the control circuit is configured to generate a control signal to adjust a phase of the first clock signal or the second clock signal according to the first detection result.
  • FIG. 1 is a diagram illustrating a circuitry according to one embodiment of the present invention.
  • FIG. 2 is a diagram illustrating the first detection circuit according to one embodiment of the present invention.
  • FIG. 3 is a diagram illustrating the second detection circuit according to one embodiment of the present invention.
  • FIG. 4 is a diagram illustrating the third detection circuit according to one embodiment of the present invention.
  • FIG. 5 is a diagram illustrating the fourth detection circuit according to one embodiment of the present invention.
  • FIG. 6 is a diagram illustrating the first detection circuit according to one embodiment of the present invention.
  • FIG. 7 is a diagram illustrating the second detection circuit according to one embodiment of the present invention.
  • FIG. 8 is a diagram illustrating the third detection circuit according to one embodiment of the present invention.
  • FIG. 9 is a diagram illustrating the fourth detection circuit according to one embodiment of the present invention.
  • FIG. 1 is a diagram illustrating a circuitry 100 according to one embodiment of the present invention.
  • the circuitry 100 comprises a quadrature phase detector 110 , a control circuit 120 and a clock signal generator 130 , wherein the quadrature phase detector 110 comprises a first detection circuit 112 , a second detection circuit 114 , a third detection circuit 116 and a fourth detection circuit 118 .
  • the circuitry 100 is configured to generate four clock signals CK 0 , CK 90 , CK 180 and CK 270 with ideal phases of 0 degree, 90 degrees, 180 degrees and 270 degrees, respectively.
  • the quadrature phase detector 110 is configured to detect phase differences between any two adjacent clock signals to generate detection results.
  • the first detection circuit 112 is configured to detect a phase difference between the clock signals CK 0 and CK 90 to generate a first detection result V 1
  • the second detection circuit 114 is configured to detect a phase difference between the clock signals CK 90 and CK 180 to generate a second detection result V 2
  • the third detection circuit 116 is configured to detect a phase difference between the clock signals CK 180 and CK 270 to generate a third detection result V 3
  • the fourth detection circuit 118 is configured to detect a phase difference between the clock signals CK 270 and CK 0 to generate a fourth detection result V 4 .
  • the control circuit 120 refers to the first detection result V 1 , the second detection result V 2 , the third detection result V 3 and the fourth detection result V 4 to determine if any one of the clock signals CK 0 CK 90 , CK 180 and CK 270 needs to adjust the phase, and at least one control signal Vc is generated accordingly.
  • the control circuit 120 can refer to the first detection result V 1 to determine if the phase difference between the clock signals CK 0 and CK 90 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK 90 .
  • the control circuit 120 can refer to the second detection result V 2 to determine if the phase difference between the clock signals CK 90 and CK 180 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK 180 .
  • the control circuit 120 can refer to the third detection result V 3 to determine if the phase difference between the clock signals CK 180 and CK 270 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK 270 .
  • the control circuit 120 can refer to the fourth detection result V 4 to determine if the phase difference between the clock signals CK 270 and CK 0 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK 0 .
  • At least a portion of the first detection circuit 112 , the second detection circuit 114 and the third detection circuit 116 and the fourth detection circuit 118 are designed so that most of the components are implemented by using passive components, to lower power consumption and improve the phase detection mismatches.
  • FIG. 2 is a diagram illustrating the first detection circuit 112 according to one embodiment of the present invention.
  • the first detection circuit 112 comprises transistors M 11 , M 12 , resistors R 11 , R 12 and a low-pass filter 210 , wherein the low-pass filter 210 comprises a resistor R 13 and a capacitor C 11 .
  • the transistor M 11 is a P-type transistor while the transistor M 12 is an N-type transistor, a gate electrode of the transistor M 11 is coupled to the clock signal CK 90 , a first electrode of the M 11 is coupled to a first electrode of the transistor M 12 via the node N 1 and the resistor R 12 , a second electrode of the transistor M 11 is coupled to the clock signal CK 0 via the resistor R 11 , and a second electrode of the transistor M 12 is coupled to a ground voltage.
  • the transistor M 11 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 90 to selectively connect the clock signal CK 0 to the node N 1 .
  • the transistor M 12 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 90 to selectively connect the node N 1 to the ground voltage.
  • the node N 1 when the clock signal CK 90 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK 0 has a high voltage such as a supply voltage VDD of the clock signal generator 130 , the node N 1 will have the high voltage (e.g. VDD); when both the clock signals CK 90 and CK 0 have the low voltage, the node N 1 will have the low voltage; and when the clock signal CK 90 has the high voltage, the node N 1 will always have the low voltage because the transistor M 12 with larger driving ability discharges the node N 1 .
  • VDD supply voltage
  • the first detection result V 1 generated by filtering the voltage of the node N 1 should be equal to (1 ⁇ 4)*VDD if the phase difference between the clock signals CK 0 and CK 90 is exactly equal to 90 degrees.
  • the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK 90 .
  • the first detection result V 1 is greater than (1 ⁇ 4)*VDD, it means that the phase difference between the clock signals CK 0 and CK 90 is greater than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK 90 .
  • the first detection circuit 112 is configured to detect the phase difference based on rising edges of the clock signals CK 0 and CK 90 .
  • the transistor M 11 may be implemented by an N-type transistor while the transistor M 12 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK 0 and CK 90 .
  • FIG. 3 is a diagram illustrating the second detection circuit 114 according to one embodiment of the present invention.
  • the second detection circuit 114 comprises transistors M 21 , M 22 , resistors R 21 , R 22 and a low-pass filter 310 , wherein the low-pass filter 310 comprises a resistor R 23 and a capacitor C 21 .
  • the transistor M 21 is a P-type transistor while the transistor M 22 is an N-type transistor, a gate electrode of the transistor M 21 is coupled to the clock signal CK 180 , a first electrode of the M 21 is coupled to a first electrode of the transistor M 22 via the node N 2 and the resistor R 22 , a second electrode of the transistor M 21 is coupled to the clock signal CK 90 via the resistor R 21 , and a second electrode of the transistor M 22 is coupled to the ground voltage.
  • the transistor M 21 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 180 to selectively connect the clock signal CK 90 to the node N 2 .
  • the transistor M 22 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 180 to selectively connect the node N 2 to the ground voltage.
  • the node N 2 when the clock signal CK 180 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK 90 has a high voltage such as a supply voltage VDD of the clock signal generator 130 , the node N 2 will have the high voltage (e.g. VDD); when both the clock signals CK 180 and CK 90 have the low voltage, the node N 2 will have the low voltage; and when the clock signal CK 180 has the high voltage, the node N 2 will always have the low voltage because the transistor M 22 with larger driving ability discharges the node N 2 .
  • VDD supply voltage
  • the clock signal CK 180 and CK 90 when both the clock signals CK 180 and CK 90 have the low voltage, the node N 2 will have the low voltage; and when the clock signal CK 180 has the high voltage, the node N 2 will always have the low voltage because the transistor M 22 with larger driving ability discharges the node N 2 .
  • the second detection result V 2 generated by filtering the voltage of the node N 2 should be equal to (1 ⁇ 4)*VDD if the phase difference between the clock signals CK 90 and CK 180 is exactly equal to 90 degrees.
  • the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK 180 .
  • the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK 180 .
  • the second detection circuit 114 is configured to detect the phase difference based on rising edges of the clock signals CK 90 and CK 180 .
  • the transistor M 21 may be implemented by the N-type transistor while the transistor M 22 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK 90 and CK 180 .
  • FIG. 4 is a diagram illustrating the third detection circuit 116 according to one embodiment of the present invention.
  • the third detection circuit 116 comprises transistors M 31 , M 32 , resistors R 31 , R 32 and a low-pass filter 410 , wherein the low-pass filter 410 comprises a resistor R 33 and a capacitor C 31 .
  • the transistor M 31 is the P-type transistor while the transistor M 32 is the N-type transistor, a gate electrode of the transistor M 31 is coupled to the clock signal CK 270 , a first electrode of the M 31 is coupled to a first electrode of the transistor M 32 via the node N 3 and the resistor R 32 , a second electrode of the transistor M 31 is coupled to the clock signal CK 180 via the resistor R 31 , and a second electrode of the transistor M 32 is coupled to the ground voltage.
  • the transistor M 31 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 270 to selectively connect the clock signal CK 180 to the node N 3 .
  • the transistor M 32 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 270 to selectively connect the node N 3 to the ground voltage.
  • the node N 3 when the clock signal CK 270 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK 180 has a high voltage such as a supply voltage VDD of the clock signal generator 130 , the node N 3 will have the high voltage (e.g. VDD); when both the clock signals CK 270 and CK 180 have the low voltage, the node N 3 will have the low voltage; and when the clock signal CK 270 has the high voltage, the node N 3 will always have the low voltage because the transistor M 32 with larger driving ability discharges the node N 3 .
  • VDD supply voltage
  • the third detection result V 3 generated by filtering the voltage of the node N 3 should be equal to (1 ⁇ 4)*VDD if the phase difference between the clock signals CK 180 and CK 270 is exactly equal to 90 degrees.
  • the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK 270 .
  • the third detection result V 3 is greater than (1 ⁇ 4)*VDD, it means that the phase difference between the clock signals CK 180 and CK 270 is greater than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK 270 .
  • the third detection circuit 116 is configured to detect the phase difference based on rising edges of the clock signals CK 180 and CK 270 .
  • the transistor M 31 may be implemented by the N-type transistor while the transistor M 32 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK 180 and CK 270 .
  • FIG. 5 is a diagram illustrating the fourth detection circuit 118 according to one embodiment of the present invention.
  • the fourth detection circuit 118 comprises transistors M 41 , M 42 , resistors R 41 , R 42 and a low-pass filter 510 , wherein the low-pass filter 510 comprises a resistor R 43 and a capacitor C 41 .
  • the transistor M 41 is the P-type transistor while the transistor M 42 is the N-type transistor, a gate electrode of the transistor M 41 is coupled to the clock signal CK 0 , a first electrode of the M 41 is coupled to a first electrode of the transistor M 42 via the node N 4 and the resistor R 42 , a second electrode of the transistor M 41 is coupled to the clock signal CK 270 via the resistor R 41 , and a second electrode of the transistor M 42 is coupled to the ground voltage.
  • the transistor M 41 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 0 to selectively connect the clock signal CK 270 to the node N 4 .
  • the transistor M 42 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK 0 to selectively connect the node N 4 to the ground voltage.
  • the node N 4 when the clock signal CK 0 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK 270 has a high voltage such as a supply voltage VDD of the clock signal generator 130 , the node N 4 will have the high voltage (e.g. VDD); when both the clock signals CK 0 and CK 270 have the low voltage, the node N 4 will have the low voltage; and when the clock signal CK 0 has the high voltage, the node N 4 will always have the low voltage because the transistor M 42 with larger driving ability discharges the node N 4 .
  • the fourth detection result V 4 generated by filtering the voltage of the node N 4 should be equal to (1 ⁇ 4)*VDD if the phase difference between the clock signals CK 270 and CK 0 is exactly equal to 90 degrees.
  • the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK 0 .
  • the fourth detection result V 4 is greater than (1 ⁇ 4)*VDD, it means that the phase difference between the clock signals CK 270 and CK 0 is greater than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK 0 .
  • the fourth detection circuit 118 is configured to detect the phase difference based on rising edges of the clock signals CK 270 and CK 0 .
  • the transistor M 41 may be implemented by the N-type transistor while the transistor M 42 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK 270 and CK 180 .
  • the components within the first detection circuit 112 , the second detection circuit 114 , the third detection circuit 116 and the fourth detection circuit 118 do not need to be powered by the supply voltage VDD, power consumption of the circuitry 100 can be greatly reduced.
  • the passive devices such as resistors R 11 , R 21 , R 31 and R 41 have small errors in process, phase detection mismatches of the first detection circuit 112 , the second detection circuit 114 , the third detection circuit 116 and the fourth detection circuit 118 can be improved.
  • the node N 1 may not exactly have the ground voltage or 0V when both the clock signals CK 0 and CK 90 have the low voltage due to large turn-on resistance of the transistor M 11 , causing the first detection result V 1 has error.
  • the first detection circuit 112 can be modified to have a compensation circuit to control the node N 1 to have the ground voltage or 0V when both the clock signals CK 0 and CK 90 have the low voltage. Referring to FIG.
  • the first detection circuit 112 ′ further comprises the compensation circuit including a transistor M 13 , a resistor R 14 and a NOR gate 610 , wherein the NOR gate 610 receives the clock signals CK 0 and CK 90 .
  • the compensation circuit shown in FIG. 6 when both the clock signals CK 0 and CK 90 have the low voltage, an output signal of the NOR gate 610 will enable the transistor M 13 to discharge the node N 1 , so that the node N 1 can have the ground voltage. Therefore, the first detection result V 1 can reflect the phase difference of the clock signals CK 0 and CK 90 more accurately.
  • the compensation circuit shown in FIG. 6 is for illustrative, not a limitation of the present invention. As long as the compensation circuit can discharge the node N 1 when the transistor M 11 is enabled and the clock signal CK 0 has the low voltage (i.e., both the clock signals CK 0 and CK 90 have the low voltage), the compensation circuit can have any other suitable design. In one embodiment, the compensation circuit discharges the node N 1 only when the transistor M 11 is enabled and the clock signal CK 0 has the low voltage.
  • the compensation circuit is designed so that the node N 1 is discharged when the clock signal CK 0 has the low voltage and the clock signal CK 90 have the high voltage.
  • the node N 2 may not exactly have the ground voltage or 0V when both the clock signals CK 90 and CK 180 have the low voltage due to large turn-on resistance of the transistor M 21 , causing the second detection result V 2 has error.
  • the second detection circuit 114 can be modified to have a compensation circuit to control the node N 2 to have the ground voltage or 0V when both the clock signals CK 90 and CK 180 have the low voltage.
  • the second detection circuit 114 ′ further comprises the compensation circuit including a transistor M 23 , a resistor R 24 and a NOR gate 710 , wherein the NOR gate 710 receives the clock signals CK 90 and CK 180 .
  • the node N 3 may not exactly have the ground voltage or 0V when both the clock signals CK 180 and CK 270 have the low voltage due to large turn-on resistance of the transistor M 31 , causing the second detection result V 3 has error.
  • the third detection circuit 116 can be modified to have a compensation circuit to control the node N 3 to have the ground voltage or 0V when both the clock signals CK 180 and CK 270 have the low voltage. Referring to FIG.
  • the third detection circuit 116 ′ further comprises the compensation circuit including a transistor M 33 , a resistor R 34 and a NOR gate 810 , wherein the NOR gate 810 receives the clock signals CK 180 and CK 270 .
  • the compensation circuit shown in FIG. 8 when both the clock signals CK 180 and CK 270 have the low voltage, an output signal of the NOR gate 810 will enable the transistor M 33 to discharge the node N 3 , so that the node N 3 can have the ground voltage. Therefore, the second detection result V 3 can reflect the phase difference of the clock signals CK 180 and CK 270 more accurately.
  • the node N 4 may not exactly have the ground voltage or 0V when both the clock signals CK 270 and CK 0 have the low voltage due to large turn-on resistance of the transistor M 41 , causing the second detection result V 4 has error.
  • the third detection circuit 118 can be modified to have a compensation circuit to control the node N 4 to have the ground voltage or 0V when both the clock signals CK 270 and CK 0 have the low voltage. Referring to FIG.
  • the fourth detection circuit 118 ′ further comprises the compensation circuit including a transistor M 43 , a resistor R 44 and a NOR gate 910 , wherein the NOR gate 910 receives the clock signals CK 270 and CK 0 .
  • the compensation circuit shown in FIG. 9 when both the clock signals CK 270 and CK 0 have the low voltage, an output signal of the NOR gate 910 will enable the transistor M 43 to discharge the node N 4 , so that the node N 4 can have the ground voltage. Therefore, the second detection result V 4 can reflect the phase difference of the clock signals CK 270 and CK 0 more accurately.
  • the quadrature phase detector 110 may have the first detection circuit 112 only, or the quadrature phase detector 110 may have the first detection circuit 112 and the second detection circuit 114 only, or the quadrature phase detector 110 may have the first detection circuit 112 , the second detection circuit 114 and the third detection circuit 116 only.
  • the quadrature phase detector 110 may have the first detection circuit 112 , the second detection circuit 114 and the third detection circuit 116 only.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 63/255,030, filed on Oct. 13, 2021. The content of the application is incorporated herein by reference.
BACKGROUND
A quadrature phase detector is usually provided to detect a phase difference between an in-phase clock signal and a quadrature clock signal, and a detection result of the quadrature phase detector may be used by a clock signal generator or a delay element to adjust the phase of the in-phase clock signal or the quadrature clock signal. The conventional quadrature phase detector is usually implemented by using active devices such as XOR gates, however, using XOR gates may increase the power consumption. In addition, if the quadrature phase detector is designed to detect four clock signals whose phases are 0 degree, 90 degrees, 180 degrees and 270 degrees, four sets of circuits are designed to detect the phase difference between clock signals with 0 degree and 90 degrees, the phase difference between clock signals with 90 degrees and 180 degrees, the phase difference between clock signals with 180 degrees and 270 degrees, and the phase difference between clock signals with 270 degrees and 0 degree. However, there may be mismatches between the four sets of circuits due to the semiconductor process, causing phase detection mismatches or phase detection errors.
SUMMARY
It is therefore an objective of the present invention to provide a quadrature phase detector in which most of the components are implemented by using passive components, to lower power consumption and improve the phase detection mismatches.
According to one embodiment of the present invention, a quadrature phase detector comprising a detection circuit is disclosed. The detection circuit comprises a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.
According to one embodiment of the present invention, a circuitry comprising a clock signal generator, a detection circuit and a control circuit is disclosed. The clock signal generator is configured to generate a first clock signal and a second clock signal. The detection circuit comprises a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result. The control circuit is configured to generate a control signal to adjust a phase of the first clock signal or the second clock signal according to the first detection result.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a circuitry according to one embodiment of the present invention.
FIG. 2 is a diagram illustrating the first detection circuit according to one embodiment of the present invention.
FIG. 3 is a diagram illustrating the second detection circuit according to one embodiment of the present invention.
FIG. 4 is a diagram illustrating the third detection circuit according to one embodiment of the present invention.
FIG. 5 is a diagram illustrating the fourth detection circuit according to one embodiment of the present invention.
FIG. 6 is a diagram illustrating the first detection circuit according to one embodiment of the present invention.
FIG. 7 is a diagram illustrating the second detection circuit according to one embodiment of the present invention.
FIG. 8 is a diagram illustrating the third detection circuit according to one embodiment of the present invention.
FIG. 9 is a diagram illustrating the fourth detection circuit according to one embodiment of the present invention.
 DETAILED DESCRIPTION
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
FIG. 1 is a diagram illustrating a circuitry 100 according to one embodiment of the present invention. As shown in FIG. 1 , the circuitry 100 comprises a quadrature phase detector 110, a control circuit 120 and a clock signal generator 130, wherein the quadrature phase detector 110 comprises a first detection circuit 112, a second detection circuit 114, a third detection circuit 116 and a fourth detection circuit 118. In this embodiment, the circuitry 100 is configured to generate four clock signals CK0, CK90, CK180 and CK270 with ideal phases of 0 degree, 90 degrees, 180 degrees and 270 degrees, respectively.
In the operation of the circuitry 100, the quadrature phase detector 110 is configured to detect phase differences between any two adjacent clock signals to generate detection results.
Specifically, the first detection circuit 112 is configured to detect a phase difference between the clock signals CK0 and CK90 to generate a first detection result V1, the second detection circuit 114 is configured to detect a phase difference between the clock signals CK90 and CK180 to generate a second detection result V2, the third detection circuit 116 is configured to detect a phase difference between the clock signals CK180 and CK270 to generate a third detection result V3, and the fourth detection circuit 118 is configured to detect a phase difference between the clock signals CK270 and CK0 to generate a fourth detection result V4. Then, the control circuit 120 refers to the first detection result V1, the second detection result V2, the third detection result V3 and the fourth detection result V4 to determine if any one of the clock signals CK0 CK90, CK180 and CK270 needs to adjust the phase, and at least one control signal Vc is generated accordingly. Specifically, the control circuit 120 can refer to the first detection result V1 to determine if the phase difference between the clock signals CK0 and CK90 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK90. The control circuit 120 can refer to the second detection result V2 to determine if the phase difference between the clock signals CK90 and CK180 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK180. The control circuit 120 can refer to the third detection result V3 to determine if the phase difference between the clock signals CK180 and CK270 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK270. The control circuit 120 can refer to the fourth detection result V4 to determine if the phase difference between the clock signals CK270 and CK0 is not equal to 90 degrees, and to generate the control signal Vc to the clock signal generator 130 to adjust the phase of the clock signal CK0.
In this embodiment, at least a portion of the first detection circuit 112, the second detection circuit 114 and the third detection circuit 116 and the fourth detection circuit 118 are designed so that most of the components are implemented by using passive components, to lower power consumption and improve the phase detection mismatches.
FIG. 2 is a diagram illustrating the first detection circuit 112 according to one embodiment of the present invention. As shown in FIG. 2 , the first detection circuit 112 comprises transistors M11, M12, resistors R11, R12 and a low-pass filter 210, wherein the low-pass filter 210 comprises a resistor R13 and a capacitor C11. In this embodiment, the transistor M11 is a P-type transistor while the transistor M12 is an N-type transistor, a gate electrode of the transistor M11 is coupled to the clock signal CK90, a first electrode of the M11 is coupled to a first electrode of the transistor M12 via the node N1 and the resistor R12, a second electrode of the transistor M11 is coupled to the clock signal CK0 via the resistor R11, and a second electrode of the transistor M12 is coupled to a ground voltage.
In another embodiment, the transistor M11 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK90 to selectively connect the clock signal CK0 to the node N1. In addition, the transistor M12 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK90 to selectively connect the node N1 to the ground voltage.
In the operation of the first detection circuit 112, when the clock signal CK90 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK0 has a high voltage such as a supply voltage VDD of the clock signal generator 130, the node N1 will have the high voltage (e.g. VDD); when both the clock signals CK90 and CK0 have the low voltage, the node N1 will have the low voltage; and when the clock signal CK90 has the high voltage, the node N1 will always have the low voltage because the transistor M12 with larger driving ability discharges the node N1. Therefore, because the node N1 has the high voltage only during quarter-cycle of the clock signal CK0/CK90, the first detection result V1 generated by filtering the voltage of the node N1 should be equal to (¼)*VDD if the phase difference between the clock signals CK0 and CK90 is exactly equal to 90 degrees.
In one embodiment, if the first detection result V1 is lower than (¼)*VDD, it means that the phase difference between the clock signals CK0 and CK90 is less than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK90. Similarly, if the first detection result V1 is greater than (¼)*VDD, it means that the phase difference between the clock signals CK0 and CK90 is greater than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK90.
In the embodiment shown in FIG. 2 , the first detection circuit 112 is configured to detect the phase difference based on rising edges of the clock signals CK0 and CK90. In another embodiment, the transistor M11 may be implemented by an N-type transistor while the transistor M12 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK0 and CK90.
FIG. 3 is a diagram illustrating the second detection circuit 114 according to one embodiment of the present invention. As shown in FIG. 3 , the second detection circuit 114 comprises transistors M21, M22, resistors R21, R22 and a low-pass filter 310, wherein the low-pass filter 310 comprises a resistor R23 and a capacitor C21. In this embodiment, the transistor M21 is a P-type transistor while the transistor M22 is an N-type transistor, a gate electrode of the transistor M21 is coupled to the clock signal CK180, a first electrode of the M21 is coupled to a first electrode of the transistor M22 via the node N2 and the resistor R22, a second electrode of the transistor M21 is coupled to the clock signal CK90 via the resistor R21, and a second electrode of the transistor M22 is coupled to the ground voltage.
In another embodiment, the transistor M21 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK180 to selectively connect the clock signal CK90 to the node N2. In addition, the transistor M22 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK180 to selectively connect the node N2 to the ground voltage.
In the operation of the second detection circuit 114, when the clock signal CK180 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK90 has a high voltage such as a supply voltage VDD of the clock signal generator 130, the node N2 will have the high voltage (e.g. VDD); when both the clock signals CK180 and CK90 have the low voltage, the node N2 will have the low voltage; and when the clock signal CK180 has the high voltage, the node N2 will always have the low voltage because the transistor M22 with larger driving ability discharges the node N2. Therefore, because the node N2 has the high voltage only during quarter-cycle of the clock signal CK90/CK180, the second detection result V2 generated by filtering the voltage of the node N2 should be equal to (¼)*VDD if the phase difference between the clock signals CK90 and CK180 is exactly equal to 90 degrees.
In one embodiment, if the second detection result V2 is lower than (¼)*VDD, it means that the phase difference between the clock signals CK90 and CK180 is less than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK180.
Similarly, if the second detection result V2 is greater than (¼)*VDD, it means that the phase difference between the clock signals CK90 and CK180 is greater than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK180.
In the embodiment shown in FIG. 3 , the second detection circuit 114 is configured to detect the phase difference based on rising edges of the clock signals CK90 and CK180. In another embodiment, the transistor M21 may be implemented by the N-type transistor while the transistor M22 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK90 and CK180.
FIG. 4 is a diagram illustrating the third detection circuit 116 according to one embodiment of the present invention. As shown in FIG. 4 , the third detection circuit 116 comprises transistors M31, M32, resistors R31, R32 and a low-pass filter 410, wherein the low-pass filter 410 comprises a resistor R33 and a capacitor C31. In this embodiment, the transistor M31 is the P-type transistor while the transistor M32 is the N-type transistor, a gate electrode of the transistor M31 is coupled to the clock signal CK270, a first electrode of the M31 is coupled to a first electrode of the transistor M32 via the node N3 and the resistor R32, a second electrode of the transistor M31 is coupled to the clock signal CK180 via the resistor R31, and a second electrode of the transistor M32 is coupled to the ground voltage.
In another embodiment, the transistor M31 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK270 to selectively connect the clock signal CK180 to the node N3. In addition, the transistor M32 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK270 to selectively connect the node N3 to the ground voltage.
In the operation of the third detection circuit 116, when the clock signal CK270 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK180 has a high voltage such as a supply voltage VDD of the clock signal generator 130, the node N3 will have the high voltage (e.g. VDD); when both the clock signals CK270 and CK180 have the low voltage, the node N3 will have the low voltage; and when the clock signal CK270 has the high voltage, the node N3 will always have the low voltage because the transistor M32 with larger driving ability discharges the node N3. Therefore, because the node N3 has the high voltage only during quarter-cycle of the clock signal CK180/CK270, the third detection result V3 generated by filtering the voltage of the node N3 should be equal to (¼)*VDD if the phase difference between the clock signals CK180 and CK270 is exactly equal to 90 degrees.
In one embodiment, if the third detection result V3 is lower than (¼)*VDD, it means that the phase difference between the clock signals CK180 and CK270 is less than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK270. Similarly, if the third detection result V3 is greater than (¼)*VDD, it means that the phase difference between the clock signals CK180 and CK270 is greater than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK270.
In the embodiment shown in FIG. 4 , the third detection circuit 116 is configured to detect the phase difference based on rising edges of the clock signals CK180 and CK270. In another embodiment, the transistor M31 may be implemented by the N-type transistor while the transistor M32 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK180 and CK270.
FIG. 5 is a diagram illustrating the fourth detection circuit 118 according to one embodiment of the present invention. As shown in FIG. 5 , the fourth detection circuit 118 comprises transistors M41, M42, resistors R41, R42 and a low-pass filter 510, wherein the low-pass filter 510 comprises a resistor R43 and a capacitor C41. In this embodiment, the transistor M41 is the P-type transistor while the transistor M42 is the N-type transistor, a gate electrode of the transistor M41 is coupled to the clock signal CK0, a first electrode of the M41 is coupled to a first electrode of the transistor M42 via the node N4 and the resistor R42, a second electrode of the transistor M41 is coupled to the clock signal CK270 via the resistor R41, and a second electrode of the transistor M42 is coupled to the ground voltage.
In another embodiment, the transistor M41 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK0 to selectively connect the clock signal CK270 to the node N4. In addition, the transistor M42 can be replaced by a switch with any different type, and this switch is controlled by the clock signal CK0 to selectively connect the node N4 to the ground voltage.
In the operation of the fourth detection circuit 118, when the clock signal CK0 has a low voltage (e.g. ground voltage or 0V) and the clock signal CK270 has a high voltage such as a supply voltage VDD of the clock signal generator 130, the node N4 will have the high voltage (e.g. VDD); when both the clock signals CK0 and CK270 have the low voltage, the node N4 will have the low voltage; and when the clock signal CK0 has the high voltage, the node N4 will always have the low voltage because the transistor M42 with larger driving ability discharges the node N4. Therefore, because the node N4 has the high voltage only during quarter-cycle of the clock signal CK270/CK0, the fourth detection result V4 generated by filtering the voltage of the node N4 should be equal to (¼)*VDD if the phase difference between the clock signals CK270 and CK0 is exactly equal to 90 degrees.
In one embodiment, if the fourth detection result V4 is lower than (¼)*VDD, it means that the phase difference between the clock signals CK270 and CK0 is less than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to delay the phase of the clock signal CK0. Similarly, if the fourth detection result V4 is greater than (¼)*VDD, it means that the phase difference between the clock signals CK270 and CK0 is greater than 90 degrees, and the control circuit 120 may generate the control signal Vc to control the clock signal generator 130 to advance the phase of the clock signal CK0.
In the embodiment shown in FIG. 5 , the fourth detection circuit 118 is configured to detect the phase difference based on rising edges of the clock signals CK270 and CK0. In another embodiment, the transistor M41 may be implemented by the N-type transistor while the transistor M42 is implemented by the P-type transistor, for detecting the phase difference based on falling edges of the clock signals CK270 and CK180.
In the embodiment shown in FIGS. 2-5 , because the components within the first detection circuit 112, the second detection circuit 114, the third detection circuit 116 and the fourth detection circuit 118 do not need to be powered by the supply voltage VDD, power consumption of the circuitry 100 can be greatly reduced. In addition, because the passive devices such as resistors R11, R21, R31 and R41 have small errors in process, phase detection mismatches of the first detection circuit 112, the second detection circuit 114, the third detection circuit 116 and the fourth detection circuit 118 can be improved.
In the first detection circuit 112 shown in FIG. 2 , the node N1 may not exactly have the ground voltage or 0V when both the clock signals CK0 and CK90 have the low voltage due to large turn-on resistance of the transistor M11, causing the first detection result V1 has error. To solve this problem, the first detection circuit 112 can be modified to have a compensation circuit to control the node N1 to have the ground voltage or 0V when both the clock signals CK0 and CK90 have the low voltage. Referring to FIG. 6 , the first detection circuit 112′ further comprises the compensation circuit including a transistor M13, a resistor R14 and a NOR gate 610, wherein the NOR gate 610 receives the clock signals CK0 and CK90. In the operation of the compensation circuit shown in FIG. 6 , when both the clock signals CK0 and CK90 have the low voltage, an output signal of the NOR gate 610 will enable the transistor M13 to discharge the node N1, so that the node N1 can have the ground voltage. Therefore, the first detection result V1 can reflect the phase difference of the clock signals CK0 and CK90 more accurately.
It is noted that the compensation circuit shown in FIG. 6 is for illustrative, not a limitation of the present invention. As long as the compensation circuit can discharge the node N1 when the transistor M11 is enabled and the clock signal CK0 has the low voltage (i.e., both the clock signals CK0 and CK90 have the low voltage), the compensation circuit can have any other suitable design. In one embodiment, the compensation circuit discharges the node N1 only when the transistor M11 is enabled and the clock signal CK0 has the low voltage.
In addition, for the case that the transistor M11 is implemented by the N-type transistor, the compensation circuit is designed so that the node N1 is discharged when the clock signal CK0 has the low voltage and the clock signal CK90 have the high voltage.
In the second detection circuit 114 shown in FIG. 3 , the node N2 may not exactly have the ground voltage or 0V when both the clock signals CK90 and CK180 have the low voltage due to large turn-on resistance of the transistor M21, causing the second detection result V2 has error. To solve this problem, the second detection circuit 114 can be modified to have a compensation circuit to control the node N2 to have the ground voltage or 0V when both the clock signals CK90 and CK180 have the low voltage. Referring to FIG. 7 , the second detection circuit 114′ further comprises the compensation circuit including a transistor M23, a resistor R24 and a NOR gate 710, wherein the NOR gate 710 receives the clock signals CK90 and CK180. In the operation of the compensation circuit shown in FIG. 7 , when both the clock signals CK90 and CK180 have the low voltage, an output signal of the NOR gate 710 will enable the transistor M23 to discharge the node N2, so that the node N2 can have the ground voltage. Therefore, the second detection result V2 can reflect the phase difference of the clock signals CK90 and CK180 more accurately.
In the third detection circuit 116 shown in FIG. 4 , the node N3 may not exactly have the ground voltage or 0V when both the clock signals CK180 and CK270 have the low voltage due to large turn-on resistance of the transistor M31, causing the second detection result V3 has error. To solve this problem, the third detection circuit 116 can be modified to have a compensation circuit to control the node N3 to have the ground voltage or 0V when both the clock signals CK180 and CK270 have the low voltage. Referring to FIG. 8 , the third detection circuit 116′ further comprises the compensation circuit including a transistor M33, a resistor R34 and a NOR gate 810, wherein the NOR gate 810 receives the clock signals CK180 and CK270. In the operation of the compensation circuit shown in FIG. 8 , when both the clock signals CK180 and CK270 have the low voltage, an output signal of the NOR gate 810 will enable the transistor M33 to discharge the node N3, so that the node N3 can have the ground voltage. Therefore, the second detection result V3 can reflect the phase difference of the clock signals CK180 and CK270 more accurately.
In the fourth detection circuit 118 shown in FIG. 5 , the node N4 may not exactly have the ground voltage or 0V when both the clock signals CK270 and CK0 have the low voltage due to large turn-on resistance of the transistor M41, causing the second detection result V4 has error. To solve this problem, the third detection circuit 118 can be modified to have a compensation circuit to control the node N4 to have the ground voltage or 0V when both the clock signals CK270 and CK0 have the low voltage. Referring to FIG. 9 , the fourth detection circuit 118′ further comprises the compensation circuit including a transistor M43, a resistor R44 and a NOR gate 910, wherein the NOR gate 910 receives the clock signals CK270 and CK0. In the operation of the compensation circuit shown in FIG. 9 , when both the clock signals CK270 and CK0 have the low voltage, an output signal of the NOR gate 910 will enable the transistor M43 to discharge the node N4, so that the node N4 can have the ground voltage. Therefore, the second detection result V4 can reflect the phase difference of the clock signals CK270 and CK0 more accurately.
In the embodiment shown in FIGS. 6-9 , because most of the components within the first detection circuit 112′, the second detection circuit 114′, the third detection circuit 116′ and the fourth detection circuit 118′ do not need to be powered by the supply voltage VDD, power consumption of the circuitry 100 can be greatly reduced. In addition, because the passive devices such as resistors R11, R21, R31 and R41 have small errors in process, phase detection mismatches of the first detection circuit 112′, the second detection circuit 114′, the third detection circuit 116′ and the fourth detection circuit 118′ can be improved.
It is noted that quantity of the detection circuits within the quadrature phase detector 110 is for illustrative, not a limitation of the present invention. In other embodiments, the quadrature phase detector 110 may have the first detection circuit 112 only, or the quadrature phase detector 110 may have the first detection circuit 112 and the second detection circuit 114 only, or the quadrature phase detector 110 may have the first detection circuit 112, the second detection circuit 114 and the third detection circuit 116 only. These alternative designs should fall within the scope of the present invention.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

What is claimed is:
1. A quadrature phase detector, comprising:
a first detection circuit configured to detect a phase difference between a first clock signal and a second clock signal, comprising:
a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a ground voltage, wherein the second switch and the first switch are controlled by the second clock signal with a same phase; and
a first filter, configured to filter voltages at the first node to generate a first detection result, wherein the first detection result indicates the phase difference between the first clock signal and the second clock signal.
2. The quadrature phase detector of claim 1, wherein the first switch is a first transistor comprising a gate electrode, a first electrode and a second electrode, wherein the first transistor receives the first clock signal at the second electrode, and receives the second clock signal at the gate electrode; and the second switch is a second transistor comprising a gate electrode, a first electrode and a second electrode, wherein the first electrode of the second transistor is coupled to the first electrode of the first transistor at the first node, the second transistor receives the second clock signal at the gate electrode, and the second electrode of the second transistor is coupled to the ground voltage.
3. The quadrature phase detector of claim 2, wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
4. The quadrature phase detector of claim 2, wherein the first transistor is an N-type transistor, and the second transistor is a P-type transistor.
5. The quadrature phase detector of claim 1, wherein the first detection circuit further comprises:
a compensation circuit, configured to selectively provide a discharging path for discharging the first node.
6. The quadrature phase detector of claim 5, wherein the compensation circuit is configured to provide the discharging path to discharge the first node when the first switch is enabled and the first clock signal has a low voltage level.
7. A quadrature phase detector, comprising:
a first detection circuit configured to detect a phase difference between a first clock signal and a second clock signal, comprising:
a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a reference voltage; and
a first filter, configured to filter voltages at the first node to generate a first detection result;
wherein ideally a phase difference between the first clock signal and the second clock signal is equal to 90 degrees, and the quadrature phase detector further comprises:
a second detection circuit, comprising:
a third switch, wherein the third switch is controlled by a third clock signal to selectively couple the second clock signal to a second node;
a fourth switch, wherein the fourth switch is controlled by the third clock signal to selectively coupled the second node to the reference voltage; and
a second filter, configured to filter voltages at the second node to generate a second detection result.
8. The quadrature phase detector of claim 7, wherein the third switch is a third transistor comprising a gate electrode, a first electrode and a second electrode, wherein the third transistor receives the second clock signal at the second electrode, and receives a third clock signal at the gate electrode; and the fourth switch is a fourth transistor comprising a gate electrode, a first electrode and a second electrode, wherein the first electrode of the fourth transistor is coupled to the first electrode of the third transistor at the second node, the fourth transistor receives the third clock signal at the gate electrode, and the second electrode of the fourth transistor is coupled to the reference voltage.
9. The quadrature phase detector of claim 7, wherein ideally a phase difference between the second clock signal and the third clock signal is equal to 90 degrees, and the quadrature phase detector further comprises:
a third detection circuit, comprising:
a fifth switch, wherein the fifth switch is controlled by a fourth clock signal to selectively couple the third clock signal to a third node;
a sixth switch, wherein the sixth switch is controlled by the fourth clock signal to selectively coupled the third node to the reference voltage; and
a third filter, configured to filter voltages at the third node to generate a third detection result.
10. The quadrature phase detector of claim 9, wherein the fifth switch is a fifth transistor comprising a gate electrode, a first electrode and a second electrode, wherein the fifth transistor receives the third clock signal at the second electrode, and receives the fourth clock signal at the gate electrode; and the sixth switch is a sixth transistor comprising a gate electrode, a first electrode and a second electrode, wherein the first electrode of the sixth transistor is coupled to the first electrode of the fifth transistor at the third node, the sixth transistor receives the fourth clock signal at the gate electrode, and the second electrode of the sixth transistor is coupled to the reference voltage.
11. The quadrature phase detector of claim 9, wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are with phases 0 degree, 90 degrees, 180 degrees and 270 degrees, respectively, and the quadrature phase detector further comprises:
a fourth detection circuit, comprising:
a seventh switch, wherein the seventh switch is controlled by the first clock signal to selectively couple the fourth clock signal to a fourth node;
an eighth switch, wherein the eighth switch is controlled by the first clock signal to selectively coupled the fourth node to the reference voltage; and
a fourth filter, configured to filter voltages at the fourth node to generate a fourth detection result.
12. A circuitry, comprising:
a clock signal generator, configured to generate a first clock signal and a second clock signal,
a first detection circuit configured to detect a phase difference between the first clock signal and the second clock signal, comprising:
a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a ground voltage, wherein the second switch and the first switch are controlled by the second clock signal with a same phase; and
a first filter, configured to filter voltages at the first node to generate a first detection result, wherein the first detection result indicates the phase difference between the first clock signal and the second clock signal;
a control circuit, coupled to the first detection circuit, configured to generate a control signal to adjust a phase of the first clock signal or the second clock signal according to the first detection result.
13. The circuitry of claim 12, wherein the first switch is a first transistor comprising a gate electrode, a first electrode and a second electrode, wherein the first transistor receives the first clock signal at the second electrode, and receives the second clock signal at the gate electrode; and the second switch is a second transistor comprising a gate electrode, a first electrode and a second electrode, wherein the first electrode of the second transistor is coupled to the first electrode of the first transistor at the first node, the second transistor receives the second clock signal at the gate electrode, and the second electrode of the second transistor is coupled to the ground voltage.
14. The circuitry of claim 13, wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
15. The circuitry of claim 13, wherein the first transistor is an N-type transistor, and the second transistor is a P-type transistor.
16. The circuitry of claim 12, wherein the first detection circuit further comprises:
a compensation circuit, configured to selectively provide a discharging path for discharging the first node.
17. The circuitry of claim 16, wherein the compensation circuit is configured to provide the discharging path to discharge the first node when the first switch is enabled and the first clock signal has a low voltage level.
18. A circuitry, comprising:
a clock signal generator, configured to generate a first clock signal and a second clock signal,
a first detection circuit configured to detect a phase difference between the first clock signal and the second clock signal, comprising:
a first switch, wherein the first switch is controlled by the second clock signal to selectively couple the first clock signal to a first node;
a second switch, wherein the second switch is controlled by the second clock signal to selectively couple the first node to a reference voltage; and
a first filter, configured to filter voltages at the first node to generate a first detection result;
a control circuit, coupled to the first detection circuit, configured to generate a control signal to adjust a phase of the first clock signal or the second clock signal according to the first detection result;
wherein ideally a phase difference between the first clock signal and the second clock signal is equal to 90 degrees, and the quadrature phase detector further comprises:
a second detection circuit, comprising:
a third switch, wherein the third switch is controlled by a third clock signal to selectively couple the second clock signal to a second node;
a fourth switch, wherein the fourth switch is controlled by the third clock signal to selectively coupled the second node to the reference voltage; and
a second filter, configured to filter voltages at the second node to generate a second detection result.
19. The circuitry of claim 18, wherein ideally a phase difference between the second clock signal and the third clock signal is equal to 90 degrees, and the quadrature phase detector further comprises:
a third detection circuit, comprising:
a fifth switch, wherein the fifth switch is controlled by a fourth clock signal to selectively couple the third clock signal to a third node;
a sixth switch, wherein the sixth switch is controlled by the fourth clock signal to selectively coupled the third node to the reference voltage; and
a third filter, configured to filter voltages at the third node to generate a third detection result.
20. The circuitry of claim 19, wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are with phases 0 degree, 90 degrees, 180 degrees and 270 degrees, respectively, and the quadrature phase detector further comprises:
a fourth detection circuit, comprising:
a seventh switch, wherein the seventh switch is controlled by the first clock signal to selectively couple the fourth clock signal to a fourth node;
an eighth switch, wherein the eighth switch is controlled by the first clock signal to selectively coupled the fourth node to the reference voltage; and
a fourth filter, configured to filter voltages at the fourth node to generate a fourth detection result.
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TW111131905A TWI858381B (en) 2021-10-13 2022-08-24 Quadrature phase detector and quadrature phase detection circuit
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US20230113143A1 (en) 2023-04-13
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EP4167487A1 (en) 2023-04-19
TW202316786A (en) 2023-04-16

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