TWI516893B - Voltage clamper - Google Patents

Description

Clamping device

The present invention relates to an electronic circuit; and more particularly to a clamping device.

In the prior art, the manner in which the circuit components are damaged by high voltage is avoided, and the digital logic circuit 100 of the high voltage component is used as shown in FIG. When the components of the digital logic circuit are designed between a first voltage V _PP and a second voltage V _NN , and the first voltage V _PP minus the second voltage V _{NN is} less than the supply voltage V _DD , V _PP -V _NN <V _DD A high voltage component such as the transistors MHP1 and MHN1 in the figure can be used. However, the additional use of high voltage components is associated with higher costs associated with the process.

Another way to avoid damage to the circuit components due to high voltage is as shown in FIG. 2A, which can be implemented in a stacked manner using a transistor of a general standard process. The spliced transistor 200 includes transistors MP1, MP2, MN2, MN1. Among them, MP1, MP2, MN2, and MN1 are components of a standard process. Splicing transistor 200 receives the voltage V _H and V _L, and the bias crystals MP1 MN1, and receives a reference voltage _V CLP_H, V CLP_L bias crystals were MP2, MN2. The waveform corresponding to the circuit operation is as shown in Fig. 2B.

Taking N-type metal oxide semiconductor (NMOS) MN2 and MN1 as an example, during operation, the Drain-Source voltages shared by the transistors MN2 and MN1 are V _{DS_N2} and V _{DS_N1} , and the two voltages are crossed. design is less than V _DD, i.e. as shown in Figure 2B, the voltage V _PP -V _NN <V _DD, the voltage V across _{the DSN2} pressure equal to V V V _{DSN2 PP} and of _{a C1} = V _PP -V _C1, cross voltage V _DSN1 V _C1 is equal to the pressure difference V _NN V _DSN1 = V _C1 -V _NN, ensuring that this transistor MN1 and MN2 can operate normally. However, when a drain or source of a metal oxide semiconductor (MOS) is used for high-speed switching operation, or when a gate of a biased metal oxide semiconductor performs a high-speed switching operation, or a voltage of an output node V _sw is switched at a high speed. At this time, one of the bias voltages of the _MOS gate bias may deviate from VC _{LP_H} and V _{CLP_L} due to the coupling and effect of the parasitic capacitance. For example, the bias voltage V _CLP shown in FIG. 2C deviates, and the _levels V _{CLP_a} and V _{CLP_b} oscillate up and down, and at the same time, the node voltage V _{C1 is} oscillated up and down at the _levels V _{C1_a} and V _{C1_p} . The disturbed bias voltages V _{CLP_H} , V _{CLP_L} may cause the originally designed transistor voltage to be higher than the maximum voltage limit V _DD that can be tolerated, causing component damage.

One of the objects of the present invention is to provide a clamping device for stabilizing the bias voltage of a stacked circuit switch.

One embodiment of the present invention provides a clamping device including a stacking circuit and at least one voltage clamping circuit. The splicing circuit includes a plurality of switches and at least one output node, and the plurality of switches are controlled according to the plurality of biases to generate an output voltage at the output node. The first end of the first switch is coupled to the output node of the splicing circuit, the control end is a second node, and the second end is a first node, and the second node receives a bias voltage. Each voltage clamping circuit is coupled to one of the switches of the splicing circuit. Each voltage clamping circuit includes at least one detecting unit, and the detecting unit is configured to detect the voltage level of the second node. When the detecting unit detects the level increase of the second node, the detecting unit provides a discharging path for discharging the second node to stabilize the bias level of the second node.

One embodiment of the present invention provides a clamping device including a stacking circuit and at least one voltage clamping circuit. The splicing circuit includes a first P-type transistor, a second P-type transistor, a second N-type transistor, and a first N-type transistor The body, wherein the second P-type transistor is overlapped with the second N-type transistor as an output node, and the second node of the second N-type transistor receives a bias voltage. The voltage clamping circuit is coupled to the second N-type transistor for detecting the voltage level of the second node. When the voltage level of the second node is detected to be increased, a discharge path is provided to discharge the second node. To clamp the bias level of the second node.

The clamping device of the embodiment of the invention detects the end bias state of the stacked circuit switch by using the detecting unit, stabilizes the bias state of the switch, and eliminates the coupling effect of the high-speed switching of the switch, thereby achieving the function of the protection circuit and solving the technical problem. problem.

100‧‧‧Logical Circuit

300‧‧‧Clamping device

200, 301‧‧‧ spliced circuit

302P, 302N‧‧‧ voltage clamp circuit

RD‧‧‧resistance

MP1, MP2, MN2, MN1, M3, M4, M41, M42, M5, MC‧‧‧ transistors

C, Cm1, Cm2‧‧‧ capacitor

Ibias‧‧‧current source

602a‧‧‧buffer

Figure 1 shows a schematic diagram of a digital logic circuit of a conventional high voltage component.

Figure 2A shows a schematic diagram of a conventional splicing circuit.

Figure 2B shows the operational waveform of a conventional splicing circuit.

Figure 2C shows an operational waveform diagram of a conventional stacked circuit.

Fig. 3A is a view showing a clamp device according to an embodiment of the present invention.

Fig. 3B is a view showing the coupling effect of the clamping device of Fig. 3A.

Figure 4 is a schematic view showing a clamping device according to another embodiment of the present invention.

Fig. 5 is a view showing a clamp device according to another embodiment of the present invention.

Fig. 6 is a view showing a clamp device according to another embodiment of the present invention.

Fig. 7 is a view showing a clamp device according to another embodiment of the present invention.

Fig. 8 is a view showing a clamp device according to another embodiment of the present invention.

Fig. 9 is a view showing a clamp device according to another embodiment of the present invention.

Fig. 10 is a view showing a clamp device according to another embodiment of the present invention.

Figure 11 is a view showing a clamp device according to another embodiment of the present invention.

Figure 12 is a view showing a clamp device according to another embodiment of the present invention.

Figure 13 is a view showing a clamp device according to another embodiment of the present invention.

Figure 3A shows a schematic view of a clamping device 300 in accordance with one embodiment of the present invention. The clamping device 300 includes a stacking circuit 301 and at least one voltage clamping circuit 302 coupled to the stacking circuit 301. As an example of the figure, the clamping device 300 includes two voltage clamping circuits 302. Above the drawing is a P-type voltage clamping circuit 302P, and below the drawing is an N-type voltage clamping circuit 302N.

The Cascode circuit 301 includes a plurality of switches and an output node, and controls a plurality of switches according to the plurality of biases to generate an output voltage at the output node. As an example of the figure, the splicing circuit 301 includes four stacked transistors MP1, MP2, MN2, MN1 as switches, and the switches MP1, MP2, MN2, MN1 are respectively according to the bias voltages V _H , V _{CLP_H} , V _{CLP_L} and V _{L operate} . Taking the switch MN2 as an example, the first end of the switch MN2 is coupled to the output node V _{SW of the} splicing circuit 301, the second end is a first node V _{C1_L} , the control end is a second node V _{C2_L} , and the second node V _{C2_L} A bias voltage V _{CLP — L is} received through the resistor RD, and the switch MN2 _{operates in accordance with} the control of the bias voltage V _{CLP — L} .

It should be noted that, in the above embodiment, the splicing circuit 301 is to connect the transistor MN1 (or MP1) to one transistor MN2 (or MP2), and the present invention is not limited thereto. In another embodiment, two or two may be stacked. More than two transistors, and a voltage clamping circuit can be selectively designed to design a transistor at a preset position.

P-type voltage clamping circuit 302P, N-type voltage clamping circuit 302N The way of operation is roughly the same as the principle. The operation of the voltage clamping circuit 302 will be described below with an N-type voltage clamping circuit 302N.

In one embodiment, the voltage clamping circuit 302N includes a detection unit DU. The detecting unit DU is configured to detect the voltage level of the first node V _{C1_L} and the second node V _{C2_L} . When the detecting unit DU detects that the level of the first node V _{C1_L} and the second node V _{C2_L} increases, the detecting unit DU provides a discharging path to discharge the first node V _CL1 and the second node V _CL2 to stabilize the first The bias level of a node V _{C1_L} and the second node V _C . In one embodiment, the detecting unit DU includes a compensation unit 302a and a reaction unit 302b.

The compensation unit 302a is coupled to the second node V _{C2_L} and receives a bias voltage V _{CLP — L} to control the control terminal of the first switch MN2 via the second node V _{C2_L} . The compensation unit 302a includes a resistor RD and a capacitor C. The first end of the resistor RD is coupled to the second node V _{C2_L} , and the first end of the second end coupled to the capacitor C forms an input node to receive the bias voltage V _{CLP — L} . The second end of the capacitor C is coupled to a low voltage level V _NN . The compensation unit 302a provides a reference voltage level of the bias voltage V _{CLP — L} to the second node V _{C2 — L} . It should be noted that the resistor RD and the capacitor C in the embodiment of the present invention may be selectively implemented by using a transistor or other components, and are not limited thereto. For example, the clamping device 700 shown in FIG. 7 replaces the capacitor C with a transistor MC.

The reaction unit 302b is coupled to the compensation unit 302a, the first node V _{C1_L} , and the second node V _{C2_L} . The reaction unit 302b is configured to reflect the state of the first node V _{C1_L} and the second node V _{C2_L} and provide a discharge path. In one embodiment, the reaction unit 302b includes a current mirror (Mirror Mirror) and a reaction element M5. The transistors M3, M4 form a current mirror with the current source Ibias. The reaction element M5 is implemented as a transistor. The first end of the transistor M3 in the current mirror is coupled to the first end of the resistor RD. The first end of the transistor M4 is coupled to the second end of the resistor RD, which is coupled to the second node V _{C2_L of the} splicing circuit 301. The control terminals of the transistors M3 and M4 are coupled to each other to form a receiving node, and the receiving node is coupled to the control end of the transistor M5 and the first end of the current source Ibias. The second end of the transistor M3 is coupled to the receiving node, and the second end of the transistor M4 is coupled to the second end of the transistor M5 to the low voltage level V _NN . The first end of the transistor M5 is coupled to the first node V _{C1_L of the} splicing circuit 301 to detect the state of the first node V _{C1_L} .

During operation, the detecting unit DU detects the state of the first node V _{C1_L} and the second node V _{C2_L} by using the reaction unit 302b. When the level of the first node V _{C1_L} or the second node V _{C2_L} increases, the reaction unit 302b supplies the first node V _{C1_L} and the second node V _{C2_L} discharge path according to the reference voltage level of the bias voltage V _{CLP — L} to discharge Clamp the highest potential of these two nodes V _{C1_L} and V _{C2_L} .

This is illustrated by the example of Figs. 3A and 3B. If there is no voltage clamping circuit 302N, the rapid change of the signal on the output node V _SW may cause the first switch MN2 to have the coupling effect of the stray capacitance Cm1 and Cm2, resulting in the first node V _{C1_L of the} first switch MN1 and the second node V. The voltage of _{C2_L} shifts or changes upward. As shown in FIG. 3B, when the first switch MN2 cascade of high-speed switching circuit 301, or rapidly changing the output node V _SW signal, the output signal on node V _SW rapid changes cause the first switch MN2 possible stray capacitances Cm1 The effect of coupling with Cm2 causes the voltage of the first node V _{C1_L of the} first switch MN1 and the voltage of the second node V _{C2_L} to shift upward. However, at this time, the reaction unit 302b detects the upward offset state of the voltage of the first node V _{C1_L} and the second node V _{C2_L} . The reaction element M5 changes the current I1 of the transistor M5 _{according to} the voltage offset of the first node V _{C1_L} , and reacts this change to the current mirror. The transistor M4 of the current mirror also detects that the voltage of the second node V _{C2_L} is shifted upward. According to the voltage offset of the second node V _{C2_L} , the current I2 flowing through the fourth transistor M4 also correspondingly changes. According to the principle of the current mirror, the current I3 flowing through the third transistor M3 is correspondingly affected. When the level of the first node V _{C1_L} and the second node V _{C2_L} are shifted, the currents I1 and I2 flowing through the transistors M5 and M4 are increased. To maintain the balance, the reaction unit 302b provides the first using the transistors M4 and M5. A node V _{C1_L} and the second node V _{C2_L} fast discharge path discharge, reducing the voltages of the nodes V _{C1_L} , V _{C2_L} to stabilize or clamp the voltages of the nodes V _{C1_L} , V _{C2_L} . In this manner, the clamping device 300 of the embodiment of the present invention can stabilize the bias of the switch when the splicing circuit 301 switches the switch at a high speed, thereby eliminating the voltage offset caused by the stray capacitance coupling effect, and solving the problems of the prior art.

Figure 4 shows a schematic view of a clamping device 400 in accordance with another embodiment of the present invention. The clamping device 400 includes a stacking circuit 401 and a plurality of voltage clamping circuits 402. The N-type voltage clamping circuit 402 includes an amplifier 401a, a transistor M4, and a resistor R, as illustrated by the N-type voltage clamping circuit 402N. N-type voltage clamping circuit 402 for controlling the switch terminal MN2 of stable - i.e., the voltage of the second node _V C2_L, according upwardly offset voltage _V C2_L node, providing a fast discharge path by a resistance R and the discharging transistor M4 . In this manner, the clamping device 400 can stabilize the bias of the second node V _{C2_L} when the switch MN2 is switched at a high speed, without being affected by the coupling effect when the switch MN2 switches at high speed or the signal on the output node V _SW changes rapidly.

Figure 5 shows a schematic view of a clamping device 500 in accordance with another embodiment of the present invention. The clamping device 500 includes a stacking circuit 501 and a plurality of voltage clamping circuits 502. The N-type voltage clamping circuit 502 includes two detecting units DU1 and DU2, as illustrated by the N-type voltage clamping circuit 502N. The first detecting unit DU1 and the second detecting unit DU2 are configured to respectively detect and stabilize the voltages of the first node V _{C1_L} and the second node V _{C2_L} . The configuration of the first detecting unit DU1 and the second detecting unit DU2 are the same. Therefore, only the first detecting unit DU1 is taken as an example. The first detecting unit DU1 includes a transistor M41 and a resistor R. The transistor M41 receives the bias voltage V _{CLP — L. When} the voltage of the first node V _{C1_L} is shifted upward, the resistor R and the transistor M41 provide a fast discharge. The path is discharged to lock or clamp the voltage at node V _{C1_L} . In this way, the first node V _{C1_L} and the second node V _{C2_L} have a stable voltage and are not affected by the coupling effect when the switch MN2 switches at high speed or the signal on the output node V _SW changes rapidly.

Figure 6 shows a schematic view of a clamping device 600 in accordance with another embodiment of the present invention. The clamping device 600 includes a stacking circuit 601 and a plurality of voltage clamping circuits 602. The N-type voltage clamping circuit 602 includes a capacitor C and a buffer 602a. The buffer 602a receives the bias voltage V _{CLP — L} for locking or clamping the voltage of the first node V _{C1_L of the} switch MN2 and the second node V _{C2_L} . Accordingly, the clamping device 600 can stabilize the voltages of the first node V _{C1_L} and the second node V _{C2_L} when the switch MN2 is switched at a high speed, without being affected by the coupling effect when the switch MN2 switches at a high speed or the signal on the output node V _SW changes rapidly.

It should be noted that the N-type voltage clamping circuit of the embodiment of the present invention may be other implementation manners, as shown in the control modes of the control terminal node V _{C2_L} of the first switch MN2 as shown in FIGS. 8 and 9 . In addition, in the embodiment of the P-type voltage clamping circuit of the embodiment of the present invention, as shown in FIGS. 10 to 13, the difference from the N-type voltage clamping circuit is that the first switch is replaced by the transistor MN2 into the transistor MP2. One node V _{C1_L is} replaced by V _{C1_H} , and the second node V _{C2_L is} replaced by V _{C2_H} . Those skilled in the art can understand the operation mode of the clamping device of Figures 10 to 13 according to the above description, and the details thereof will not be described.

It should be noted that the current mirror of the embodiment of the present invention is not limited to the illustrated current mirror, and may be a cascade form, a wide-swing form, etc., and various current mirrors currently available or developed in the future. The transistors of the embodiments are not limited to metal oxide semiconductors (MOS), and may be in the form of bipolar or other currently existing or future developed components.

The clamping device of the embodiment of the invention detects the end bias state of the stacked circuit switch by using the detecting unit, stabilizes the bias state of the switch, and eliminates the coupling effect of the high-speed switching of the switch, thereby achieving the function of the protection circuit and solving the technical problem. problem.

The present invention has been described above by way of examples, and the scope of the invention is not limited thereto, and various modifications and changes may be made without departing from the scope of the invention.

300‧‧‧Clamping device

301‧‧‧Stacked circuit

302P, 302N‧‧‧ voltage clamp circuit

RD‧‧‧resistance

MP1, MP2, MN2, MN1, M3, M4, M5‧‧‧ transistors

C‧‧‧ capacitor

Ibias‧‧‧current source

Claims (15)

A clamping device comprising: a stacking circuit comprising a plurality of switches and at least one output node, controlling the plurality of switches according to a plurality of biases to generate an output voltage at the output node, wherein the first end of the first switch The output node coupled to the splicing circuit is a second node, the second end is a first node, the second node receives a bias voltage, and at least one voltage clamping circuit, each of the voltage clamping circuit coupling Connected to one of the switches of the stacking circuit, each of the voltage clamping circuits includes at least one detecting unit, wherein the detecting unit is configured to detect a voltage level of the second node; wherein, when the detecting unit detects the When the voltage level of the second node is increased, the detecting unit provides a discharge path for discharging the second node to stabilize the bias level of the second node; wherein the discharge path includes a transistor having a discharge path. One end of the transistor of the discharge path is coupled to the second node, and the other end is coupled to a first voltage level. The device of claim 1, wherein the detecting unit comprises: a compensation unit coupled to the second node, receiving the bias to control a control end of the first switch via the second node And a reaction unit coupled to the compensation unit and the second node; wherein, when the voltage level of the second node is increased, the reaction unit provides the discharge path for discharging to stabilize the second node Pressure level. The device of claim 2, wherein the compensation unit comprises: a resistor, the first end of which is coupled to the second node; a capacitor, the first end of the capacitor coupled to the second end of the resistor forms an input node to receive the bias voltage, and the second end of the capacitor is coupled to a low voltage level; wherein the compensation unit provides the The reference voltage of the bias voltage is leveled to the second node. The apparatus of claim 3, wherein the reaction unit comprises: a current mirror comprising a first transistor, a transistor of the discharge path, and a current source; wherein the first transistor The first end of the resistor is coupled to the first end of the resistor; the first end of the transistor of the discharge path is coupled to the second end of the resistor to detect a bias state of the second node of the first switch; The control end of the first transistor is coupled to the second end of the transistor of the discharge path, and the second end of the transistor of the discharge path is coupled to the first voltage level. The device of claim 1, wherein the detecting unit further detects a voltage level of the first node, and when the detecting unit detects that the voltage level of the first node is increased, The detecting unit discharges the first node. The device of claim 5, wherein the detecting unit comprises: a compensation unit coupled to the second node, receiving the bias to control a control end of the first switch via the second node And a reaction unit coupled to the compensation unit, the first node, and the second node; wherein, when the voltage level of the first node and the second node is increased, the reaction unit provides the first node Discharging with the second node discharge path to stabilize the bias level of the second node. The device of claim 6, wherein the compensation unit comprises: a resistor having a first end coupled to the second node; and a capacitor coupled to the first end of the capacitor The second end forms an input node for receiving the bias voltage, and the second end of the capacitor is coupled to a low voltage level; wherein the compensation unit provides a reference voltage level of the bias voltage to the second node. The apparatus of claim 7, wherein the reaction unit comprises: a current mirror comprising a first transistor, a transistor of the discharge path, and a current source; wherein the first transistor The first end of the resistor is coupled to the first end of the resistor; the first end of the transistor of the discharge path is coupled to the second end of the resistor to detect a bias state of the second node of the first switch; The first transistor is coupled to the control end of the transistor of the discharge path to form a receiving node, the second end of the first transistor is coupled to the receiving node, and a reactive component includes a third transistor. The control terminal of the third transistor is coupled to the first end of the current source and coupled to the receiving node, and the second end of the third transistor is coupled to a low voltage level and a second transistor of the discharge path The first end of the third transistor is coupled to the first node of the first switch to detect a bias state of the first node. The device of claim 1, wherein at least one of the voltage clamping circuits is a P-type voltage clamping circuit for clamping a bias level of a switching control terminal of a P-type transistor of the stacked circuit. . The device of claim 1, wherein at least one of the voltage clamping circuits is an N-type voltage clamping circuit for clamping a bias level of a switch control terminal of the N-type transistor of the stacked circuit. . The device of claim 1, wherein the detecting unit comprises: a resistor; a transistor of the discharging path coupled to the resistor to form the second node to couple the first switch; An amplifier for controlling a current flowing through the resistor of the transistor of the discharge path, and controlling a transistor of the discharge path according to an offset of the bias of the second node to provide a voltage of the discharge path to the second node. The device of claim 5, wherein the voltage clamping circuit comprises: a first detecting unit that detects and stabilizes a bias voltage of the first node; wherein the first detecting unit includes a first detecting unit a transistor, a resistor coupled to the transistor, the transistor receiving the bias voltage, and when the voltage of the first node is shifted upward, the resistor is used to provide a discharge path to the transistor for discharging to lock the first The voltage of the node. The device of claim 12, wherein the voltage clamping circuit comprises: a second detecting unit that detects and stabilizes a bias voltage of the second node; wherein the second detecting unit includes a transistor of the discharge path, a resistor coupled to the transistor of the discharge path, the transistor of the discharge path receives the bias voltage, and when the voltage of the second node is shifted upward, the resistor and the discharge path are electrically The crystal provides a discharge path for discharging to lock the voltage of the second node. The device of claim 5, wherein the detecting unit comprises: a capacitor; a buffer coupled to the capacitor, the buffer receiving the biasing for locking the first switch The voltage of the first node and the second node. A clamping device comprising: a stacking circuit comprising: a first P-type transistor, a second P-type transistor, a second N-type transistor, and a first N-type transistor; The second P-type transistor is overlapped with the second N-type transistor as an output node, and the second node of the second N-type transistor receives a bias voltage; and a voltage clamping circuit coupled to the second An N-type transistor is configured to detect a voltage level of the second node. When the voltage level of the second node is detected to be increased, a discharge path is provided to discharge the second node to clamp the first Two nodes The biasing path includes a transistor having a discharge path, one end of the transistor of the discharging path is coupled to the second node, and the other end is coupled to a first voltage level.