US12094709B2 - Plasma treatment process to densify oxide layers - Google Patents

Plasma treatment process to densify oxide layers Download PDF

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US12094709B2
US12094709B2 US17/390,151 US202117390151A US12094709B2 US 12094709 B2 US12094709 B2 US 12094709B2 US 202117390151 A US202117390151 A US 202117390151A US 12094709 B2 US12094709 B2 US 12094709B2
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oxide layer
plasma
wer
plasma treatment
densified
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US20230030436A1 (en
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Jung Chan LEE
Mun Kyu Park
Jun Lee
Euhngi Lee
Kyu-Ha Shim
Deven Matthew Raj MITTAL
Sungho Jo
Timothy Miller
Jingmei Liang
Praket Prakash JHA
Sanjay G. KAMATH
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Applied Materials Inc
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Applied Materials Inc
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Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, JUNG CHAN, LIANG, JINGMEI, JHA, Praket Prakash, JO, SUNGHO, KAMATH, Sanjay G., LEE, EUHNGI, LEE, JUN, MILLER, TIMOTHY, MITTAL, Deven Matthew Raj, PARK, MUN KYU, SHIM, KYU-HA
Priority to KR1020247006733A priority patent/KR20240036685A/en
Priority to PCT/US2022/036882 priority patent/WO2023009311A1/en
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Definitions

  • Embodiments of the present disclosure generally relate to fabrication of microelectronic devices, and more specifically, relate to gap fill deposition and film densification during the fabrication of microelectronic devices.
  • Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produce devices with feature sizes of 10 nm and sub-10 nm, and new equipment is being developed and implemented to make devices with even smaller geometries.
  • the decreasing feature sizes result in structural features on the device having decreased spatial dimensions.
  • the widths of gaps and trenches on the device narrow to a point where the aspect ratio of gap depth to its width becomes high enough to make it challenging to fill the gap with dielectric material.
  • the depositing dielectric material is prone to clog at the top before the gap completely fills, producing a void or seam in the middle of the gap.
  • the hardening includes a heat treatment to remove components from the deposited material to leave behind a solid dielectric material, such as silicon oxide. Some of these components were necessary to make the initially deposited film flowable. Departing components increase the density of the hardened dielectric material. The hardening dielectric material tends to shrink in volume, which can leave cracks and spaces at the interlace of the dielectric material and the surrounding substrate.
  • SOD Spin-on dielectrics
  • Oxygen from the environment displaces other atoms to produce a silicon oxide layer.
  • High temperature exposure to oxygen environments can ruin underlying layers for some circuit architectures.
  • This consideration results in the need to stay within a “thermal budget” during a manufacturing process flow.
  • Thermal budget considerations have largely limited SOD to process flows incorporating an underlying silicon nitride layer which can protect underlying features from oxidation (e.g., DRAM applications).
  • Alternative methods have been developed which deposit silicon-nitrogen layers by radical-component chemical vapor deposition (CVD). Radical-component CVD can produce a silicon-nitrogen layer by exciting and combining one precursor with an unexcited silicon-containing precursor in the plasma-free substrate processing region.
  • CVD radical-component chemical vapor deposition
  • GAA gate all around
  • the desired properties of the GAA transistors include improved direct current (DC) performance and short channel controllability over previous transistors.
  • DC direct current
  • the Si/SiGe layers within the GAA transistor are susceptible to oxidation and film damage, as well as dopant diffusion, and intermixing of neighboring layers (e.g., between Si-layers and SiGe-layers).
  • STI shallow trench isolation
  • Embodiments of the present disclosure generally relate to methods for processing substrates during the fabrication of microelectronic devices, where the methods include gap fill deposition and film densification.
  • a gate all around (GAA) transistor is one exemplary type of microelectronic device which can be fabricated with the methods described and discussed herein.
  • a method for processing a substrate includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer while maintaining the substrate at a first temperature of less than 600° C.
  • the first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias.
  • the method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer while maintaining the substrate at a second temperature of less than 600° C.
  • the second plasma treatment includes generating a second plasma by a top RF source and a side RF source and directing the second plasma to the treated oxide layer without a bias.
  • the densified oxide layer has a final WER of less than one-half of the initial WER.
  • a method for processing a substrate includes forming an oxide layer containing silicon oxide and having an initial WER over features disposed on the substrate.
  • the oxide layer is formed by depositing a flowable film containing one or more polysilazanes on the features, curing the polysilazane to produce a solidified film containing silicon, nitrogen, and hydrogen, and converting the solidified film to the oxide layer containing silicon oxide during an oxidation process.
  • the method also includes exposing the oxide layer to a first plasma treatment to produce a treated oxide layer.
  • the first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias.
  • the method further includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, where the densified oxide layer has a final WER of less than one-half of the initial WER.
  • the second plasma treatment includes generating a second plasma by a top RF source and a side RF source and directing the second plasma to the treated oxide layer without a bias.
  • a method for processing a substrate includes forming an oxide layer containing silicon oxide and having an initial WER over a plurality of fins disposed on the substrate.
  • Each of the fins contains a film stack having alternating pairs of layers, where each of the pairs of layers contains a silicon-germanium layer and a silicon layer disposed on one another.
  • the method also includes exposing the oxide layer to a first plasma treatment to produce a treated oxide layer.
  • the first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias.
  • the method further includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, where the densified oxide layer has a final WER of less than one-half of the initial WER.
  • the second plasma treatment includes generating a second plasma by a top RF source and a side RF source and directing the second plasma to the treated oxide layer without a bias.
  • FIG. 1 is a flow chart of an exemplary method for processing a substrate which includes gap fill deposition and film densification during the fabrication of a microelectronic device, according to one or more embodiments described and discussed herein.
  • FIGS. 2 A- 2 B depict cross-sectional views of an exemplary microelectronic device prepared by the method illustrated in the flow chart of FIG. 1 , according to one or more embodiments described and discussed herein.
  • Embodiments of the present disclosure generally relate to methods for processing substrates during the fabrication of microelectronic devices, where the methods include gap fill deposition and film densification.
  • the methods for gap fill deposition and film densification can be applied to the fabrication of semiconductor devices (e.g., transistors, capacitors, and the like), memory devices (e.g., NAND, DRAM, and the like), display devices (e.g., LCD, LED, and the like), solar and photovoltaic devices, as well as other electronic and microelectronic devices.
  • a gate all around (GAA) transistor can be fabricated with the methods described and discussed herein.
  • FIG. 1 is a flow chart of a method 100 for processing a substrate having features during the fabrication of a microelectronic device, according to one or more embodiments described and discussed herein.
  • the method 100 includes gap fill deposition and film densification processes.
  • the method 100 can include operations 110 - 140 as follows: forming or depositing an oxide layer containing silicon oxide over features on the substrate ( 110 ); exposing the oxide layer to a first plasma treatment to produce a treated oxide layer ( 120 ); exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer ( 130 ); and optionally forming or depositing a fill layer on or over the densified oxide layer ( 140 ).
  • an oxide layer is deposited, produced, or otherwise formed on and over the features on the substrate.
  • the features can be or include multiple or a plurality of fins, columns, film stacks, layers, films, or other structures disposed on the substrate.
  • the features can be or include a plurality of fins.
  • each fin contains a film stack.
  • the film stack can include alternating pairs of layers disposed on one another.
  • each of the pairs of layers contains silicon-germanium layers and silicon layers.
  • Each of the silicon-germanium layers and silicon layers can independently be deposited or formed by an epitaxial growth process or an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • the features can be or include a plurality of silicon-germanium/silicon (SiGe/Si) fin structures or a plurality of germanium/silicon (Ge/Si) fin structures.
  • each of the SiGe layers, the Si layers, or the Ge layers has a thickness of about 5 nm, about 8 nm, or about 10 nm to about 12 nm, about 15 nm, about 20 nm, about 25 nm, or about 30 nm.
  • the oxide layer formed on and over the features contains silicon oxide.
  • the oxide layer is formed by a multiple step process which includes depositing a flowable film onto and over the features so to fill the gaps or spaces between the features.
  • the flowable film enabled void and seam free gap-fill.
  • the flowable film contains one or more polysilazanes.
  • the flowable film or polysilazane is cured to produce a solidified film containing silicon, nitrogen, and hydrogen.
  • the curing of the flowable film or polysilazane can be performed by exposure to one or more types of radiation, such as ultraviolet light, infrared light, visible light, microwave energy, plasma, thermal energy (e.g., heat), or any combination thereof.
  • the flowable film or polysilazane is cured with ultraviolet light to produce a solidified film.
  • the Si—Si bonds, the Si—N bonds, and the Si—H bonds are broken to incorporate oxygen into the material while producing Si—O bonds during the curing process.
  • the flowable film is densified as being oxidized and less flowable and is converted to the solidified film containing silicon oxide.
  • the solidified film is an intermediate film that contains silicon oxide and contaminants, non-oxidized silicon, and/or partially oxidized silicon.
  • the solidified film can be converted or otherwise transformed to the oxide layer containing silicon oxide during an oxidation process and/or an annealing process.
  • the oxidation process includes exposing the solidified film to steam and/or one or more other oxidizing agents during an anneal process to produce the oxide layer containing silicon oxide.
  • the anneal process can include heating and/or maintaining the substrate at a temperature of less than 600° C., such as about 200° C., about 250° C., about 300° C., or about 350° C.
  • oxidizing agent can be or include water, steam, oxygen (O 2 ), ozone, hydrogen peroxide, nitrous oxide, or any combination thereof.
  • the oxide layer containing silicon oxide is denser than the solidified film, but by performing the densification processes described and discussed herein, the oxide layer can be further densified to a desired density.
  • the oxide layer containing silicon oxide has a porosity of less value compared to the porosity of the solidified film from which the oxide layer is prepared from.
  • the oxide layer can have an initial wet etch rate (WER) of greater than 3 ⁇ /min, greater than 3.5 ⁇ /min, or greater than 4 ⁇ /min to about 4.5 ⁇ /min, about 5 ⁇ /min, about 6 ⁇ /min, about 8 ⁇ /min, about 10 ⁇ /min, or greater. If normalized, the oxide layer has an initial wet etch rate ratio (WERR) is 1. Once the oxide layer is converted to the densified oxide layer, the WER and WERR values are reduced so that the densified oxide layer has lower WER and WERR values than the oxide layer from which the densified oxide layer was generated from. The WER values were calculated or otherwise determined during etch processes which include exposing the oxide layer to 1:100 HF:water (volumetric) at about 25° C. for about 2 hours.
  • WERR initial wet etch rate ratio
  • the oxide layer can have a thickness of about 20 nm, about 35 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 500 nm, about 600 nm, about 800 nm, or 1,000 nm.
  • the oxide layer can have a thickness of about 20 nm to about 1,000 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 600 nm, about 50 nm to about 500 nm, about 50 nm to about 400 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 80 nm to about 1,000 nm, about 80 nm to about 800 nm, about 80 nm to about 600 nm, about 80 nm to about 500 nm, about 80 nm to about 400 nm, about 80 nm to about 300 nm, about 80 nm to about 200 nm, about 80 nm to about 100 nm, about 100 nm to about 1,000 nm, about 100 nm to about 800 nm, about 100 nm to about 600 nm, about 100 nm
  • the oxide layer is exposed to a first plasma during a first plasma treatment to produce a treated oxide layer.
  • the first plasma treatment includes generating the first plasma by a first RF source and exposing the oxide layer to the first plasma to produce the treated oxide layer.
  • a direct current (DC) bias can be used to direct the first and/or accelerating ions of the first plasma to the oxide layer.
  • the DC bias can be generated from one or more electrodes below the substrate, such as within or part of the substrate support.
  • the first plasma is an inductively coupled plasma (ICP).
  • the first plasma is ignited or otherwise formed from a process gas containing argon, helium, neon, xenon, nitrogen (N 2 ), hydrogen (H 2 ), oxygen (O 2 ), ozone, or any combination thereof.
  • the first plasma process can be conducted in a plasma chamber or system, such as the Varian VIISTA® PLADTM plasma system, commercially available from Applied Materials, Inc.
  • the first RF source can have a power of about 0.1 kW, about 0.5 kW, about 0.8 kW, or about 1 kW to about 1.2 kW, about 1.5 kW, about 1.8 kW, about 2 kW, about 2.2 kW, about 2.5 kW, about 2.8 kW, or about 3 kW to generate the first plasma during the first plasma treatment.
  • the first RF source can have a power of about 3 kW or less than 3 kW.
  • the first RF source can have a power of about 0.1 kW to about 3 kW, about 0.1 kW to about 2.5 kW, about 0.1 kW to about 2 kW, about 0.1 kW to about 1.5 kW, about 0.1 kW to about 1 kW, about 0.1 kW to about 0.5 kW, about 1 kW to about 3 kW, about 1 kW to about 2.5 kW, about 1 kW to about 2 kW, about 1 kW to about 1.5 kW, about 1 kW to about 1 kW, about 1 kW to about 0.5 kW, about 1.5 kW to about 3 kW, about 1.5 kW to about 2.5 kW, about 1.5 kW to about 2 kW, or about 1.5 kW to about 1.8 kW during the first plasma treatment.
  • the DC bias can have a voltage of about 0.1 kV, about 0.5 kV, about 0.8 kV, about 1 kV, about 1.5 kV, or about 2 kV to about 2.5 kV, about 3 kV, about 3.5 kV, about 4 kV, about 5 kV, about 6 kV, about 7 kV, about 8 kV, about 9 kV, or about 10 kV during the first plasma treatment.
  • the DC bias can have a voltage of about 0.1 kV to about 10 kV, about 0.1 kV to about 8 kV, about 0.1 kV to about 7 kV, about 0.1 kV to about 6 kV, about 0.1 kV to about 5 kV, about 0.1 kV to about 4 kV, about 0.1 kV to about 2 kV, about 0.1 kV to about 1 kV, about 0.1 kV to about 0.5 kV, about 1 kV to about 10 kV, about 1 kV to about 8 kV, about 1 kV to about 7 kV, about 1 kV to about 6 kV, about 1 kV to about 5 kV, about 1 kV to about 4 kV, about 3 kV to about 10 kV, about 3 kV to about 8 kV, about 3 kV to about 7 kV, about 3 kV to about 6 kV, or about 3 kV to
  • the oxide layer is exposed to the first plasma at a dosage value of about 1 ⁇ 10 14 ion/cm 2 , about 5 ⁇ 10 14 ion/cm 2 , about 1 ⁇ 10 15 ion/cm 2 , or about 4 ⁇ 10 15 ion/cm 2 to about 1 ⁇ 10 16 ion/cm 2 , about 5 ⁇ 10 16 ion/cm 2 , about 1 ⁇ 10 17 ion/cm 2 , about 4 ⁇ 10 17 ion/cm 2 , about 8 ⁇ 10 17 ion/cm 2 , or about 1 ⁇ 10 18 ion/cm 2 during the first plasma treatment.
  • the oxide layer is exposed to the first plasma at a dosage value of about 1 ⁇ 10 14 ion/cm 2 to about 1 ⁇ 10 18 ion/cm 2 , about 1 ⁇ 10 14 ion/cm 2 to about 5 ⁇ 10 17 ion/cm 2 , about 1 ⁇ 10 14 ion/cm 2 to about 1 ⁇ 10 17 ion/cm 2 , about 1 ⁇ 10 14 ion/cm 2 to about 5 ⁇ 10 16 ion/cm 2 , about 1 ⁇ 10 14 ion/cm 2 to about 1 ⁇ 10 16 ion/cm 2 , about 1 ⁇ 10 14 ion/cm 2 to about 1 ⁇ 10 15 ion/cm 2 , about 1 ⁇ 10 15 ion/cm 2 to about 1 ⁇ 10 18 ion/cm 2 , about 1 ⁇ 10 15 ion/cm 2 to about 5 ⁇ 10 17 ion/cm 2 , about 1 ⁇ 10 15 ion/cm 2 to about 1 ⁇ 10 17 ion/c
  • the substrate containing the oxide layer is heated or maintained at a first temperature during the first plasma treatment process.
  • the first temperature is typically maintained at less than 600° C. so the features (e.g., fins) are not damaged during the first plasma treatment.
  • the first temperature can be about 150° C., about 200° C., about 250° C., about 300° C., or about 350° C. to about 400° C., about 450° C., about 475° C., about 480° C., about 490° C., about 500° C., about 520° C., about 550° C., about 580° C., or about 590° C.
  • the first temperature can be about 150° C. to less than 600° C., about 200° C.
  • the treated oxide layer is exposed to a second plasma during a second plasma treatment to produce a densified oxide layer.
  • the densified oxide layer has a porosity of less value compared to the porosity of the treated oxide layer from which the densified oxide layer is prepared from.
  • the second plasma is ignited, generated, or otherwise produced by at least two, three, or more plasma sources (e.g., a top RF source and a side RF source) during the second plasma treatment.
  • the second plasma is directed to the treated oxide layer without a bias to produce the densified oxide layer.
  • the top RF source is positioned or otherwise located above the substrate and the side RF source is positioned or otherwise located adjacent or besides the substrate.
  • the second plasma is an ICP.
  • the second plasma can also be a high-density plasma (HDP).
  • the second plasma is ignited or otherwise formed from a process gas containing hydrogen (H 2 ), oxygen (O 2 ), ozone, nitrogen (N 2 ), argon, helium, neon, xenon, or any combination thereof.
  • the second plasma process can be conducted in a plasma chamber or system, such as the CENTURA ULTIMA® HDP-CVD plasma chamber or system, and/or the PRODUCER® PECVD chamber or system, commercially available from Applied Materials, Inc.
  • Each of the top RF source and the side RF source can independently have a power of about 0.5 kW, about 0.8 kW, about 1 kW, about 1.5 kW, about 2 kW, about 2.5 kW, about 3 kW, about 3.5 kW, about 4 kW, about 4.5 kW or about 5 kW to about 5.5 kW, about 6 kW, about 6.5 kW, about 7 kW, about 7.5 kW, about 8 kW, about 8.5 kW, about 8.8 kW, about 9 kW, about 10 kW, or greater to generate the second plasma during the second plasma treatment.
  • each of the top RF source and the side RF source can independently have a power of about 5 kW or greater than 5 kW.
  • each of the top RF source and the side RF source can independently have a power of about 0.5 kW to about 9 kW, about 1 kW to about 9 kW, about 1 kW to about 8.5 kW, about 1 kW to about 8 kW, about 1 kW to about 7.5 kW, about 1 kW to about 7 kW, about 1 kW to about 6.5 kW, about 1 kW to about 6 kW, about 1 kW to about 5 kW, about 1 kW to about 4 kW, about 1 kW to about 3 kW, about 3 kW to about 9 kW, about 3 kW to about 8.5 kW, about 3 kW to about 8 kW, about 3 kW to about 7.5 kW, about 3 kW to about 7 kW, about 3 kW to about 6.5 kW, about 3 kW to about 6 kW, about 3 kW to about 5 kW, about 5 kW to about 9 8.5 kW, about 3 kW to about 7 kW, about 3 kW to about 6.5 kW, about 3 kW
  • the substrate containing the treated oxide layer is heated or maintained at a second temperature during the second plasma treatment process.
  • the second temperature is typically maintained at less than 600° C. so the features (e.g., fins) are not damaged during the second plasma treatment.
  • the second temperature can be about 150° C., about 200° C., about 250° C., about 300° C., or about 350° C. to about 400° C., about 450° C., about 475° C., about 480° C., about 490° C., about 500° C., about 520° C., about 550° C., about 580° C., or about 590° C.
  • the second temperature can be about 150° C. to less than 600° C., about 200° C.
  • the densified oxide layer has a WER (e.g., the final WER) which is less than the WER of the oxide layer (e.g., the initial WER) from which the densified oxide layer was generated from due to the exposures to the first and second plasma treatments.
  • the WERR of the densified oxide layer is less than 1.
  • the final WER of the densified oxide layer is less than 2 ⁇ /min, such as about 1.8 ⁇ /min, as about 1.6 ⁇ /min, about 1.5 ⁇ /min, about 1.4 ⁇ /min, about 1.2 ⁇ /min, about 1 ⁇ /min, about 0.8 ⁇ /min, about 0.5 ⁇ /min, about 0.3 ⁇ /min, about 0.2 ⁇ /min, about 0.1 ⁇ /min, or less.
  • the final WER of the densified oxide layer is less than one-half of the initial WER of the oxide layer.
  • the final WER of the densified oxide layer can be about 0.45, about 0.4, about 0.35, about 0.32, about 0.3, about 0.28, about 0.25, about 0.22, about 0.2, about 0.18, about 0.15, about 0.12, about 0.1, or less than the initial WER of the oxide layer.
  • These ratios are also considered the final WERR of the densified oxide layer.
  • the oxide layer has the initial WERR and the densified oxide layer has a final WERR of less than one-half of the initial WERR.
  • the initial WERR of the oxide layer is 1 and the final WERR of the densified oxide layer is less than 0.5, such as about 0.05, about 0.08, about 0.1, about 0.12, about 0.15, or about 0.18 to about 0.2, about 0.22, about 0.25, about 0.28, about 0.3, about 0.32, about 0.35, about 0.38, about 0.4, about 0.42, about 0.45, about 0.46, about 0.48, or about 0.49.
  • the final WERR of the densified oxide layer is about 0.05 to about 0.48, about 0.1 to about 0.48, about 0.2 to about 0.48, about 0.25 to about 0.48, about 0.3 to about 0.48, about 0.33 to about 0.48, about 0.35 to about 0.48, about 0.38 to about 0.48, about 0.4 to about 0.48, about 0.05 to about 0.4, about 0.1 to about 0.4, about 0.2 to about 0.4, about 0.25 to about 0.4, about 0.25 to about 0.45, about 0.3 to about 0.4, about 0.33 to about 0.4, about 0.35 to about 0.4, about 0.38 to about 0.4, about 0.05 to about 0.35, about 0.1 to about 0.35, about 0.2 to about 0.35, about 0.25 to about 0.35, about 0.3 to about 0.35, about 0.32 to about 0.38, about 0.32 to about 0.35, about 0.35 to about 0.38.
  • the densified oxide layer can have a thickness of about 20 nm, about 35 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 500 nm, about 600 nm, about 800 nm, or 1,000 nm.
  • the densified oxide layer can have a thickness of about 20 nm to about 1,000 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 600 nm, about 50 nm to about 500 nm, about 50 nm to about 400 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 80 nm to about 1,000 nm, about 80 nm to about 800 nm, about 80 nm to about 600 nm, about 80 nm to about 500 nm, about 80 nm to about 400 nm, about 80 nm to about 300 nm, about 80 nm to about 200 nm, about 80 nm to about 100 nm, about 100 nm to about 1,000 nm, about 100 nm to about 800 nm, about 100 nm to about 600 nm, about 80
  • one or more bulk or fill layers can optionally be deposited, produced, or otherwise formed over the densified oxide layer.
  • the bulk or fill layer can be or contain one or more materials, such as silicon, silicon oxide, silicon nitride, silicon oxynitride, dopants thereof, or any combination thereof. Other materials can also be deposited for the bulk or fill layer.
  • the bulk or fill layer can be deposited by one or more deposition process including chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), atomic layer deposition (ALD), plasma-enhanced ALD (PE-ALD), physical vapor deposition (PVD), sputtering, epitaxy, spin-on deposition, or any combination thereof.
  • the bulk or fill layer contains silicon oxide and is deposited by a thermal CVD process.
  • the bulk or fill layer can have a thickness of about 5 nm, about 10 nm, about 20 nm, about 35 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 600 nm, or greater.
  • the bulk or fill layer can have a thickness of about 5 nm to about 600 nm, about 10 nm to about 500 nm, about 50 nm to about 500 nm, about 100 nm to about 400 nm.
  • FIGS. 2 A- 2 B depict cross-sectional views of a microelectronic device 200 which can be fabricated or otherwise prepared by the process 100 , according to one or more embodiments described and discussed herein.
  • the microelectronic device 200 can be or include one or more transistors, such as a GAA transistor.
  • FIG. 2 A depicts the microelectronic device 200 containing a plurality of features 202 separated by spacings 204 disposed on a substrate 210 .
  • the features 202 can include a portion of the substrate 210 , as shown, or alternative, be positioned or otherwise disposed on the substrate 210 (not shown).
  • the features 202 can be or include multiple or a plurality of fins, columns, film stacks, layers, films, or other structures disposed on the substrate 210 and/or including a portion of the substrate 210 .
  • each of the features 202 can be or include a fin containing a film stack 220 .
  • the microelectronic device 200 also contains a densified oxide layer 250 disposed one and over the features 202 and a fill layer 260 disposed on and over the densified oxide layer 250 .
  • the densified oxide layer 250 can be deposited, produced, or otherwise formed by methods described and discussed herein, including process 100 .
  • the densified oxide layer 250 contains silicon oxide, such as densified silicon oxide and the fill layer 260 contains silicon oxide, such as a silicon oxide deposited by vapor deposition (e.g., CVD or ALD).
  • FIG. 2 B depicts the feature 202 containing the film stack 220 , as described and discussed in one or more embodiments herein.
  • the film stack 220 can have two, three, four, or more different types of layers or materials.
  • the film stack 220 contains alternating pairs of layers 222 , 224 disposed on one another.
  • each of the pairs of layers 222 , 224 contains silicon-germanium layers and silicon layers.
  • the layers 222 is or contains silicon-germanium layers and the layers 224 is or contains silicon layers.
  • the layers 222 is or contains silicon layers and the layers 224 is or contains silicon-germanium layers.
  • the film stack 220 also includes a first capping layer 230 layer disposed on the film stack 220 and a second capping layer 240 disposed on the first capping layer 230 .
  • the first capping layer 230 contains silicon oxide and the second capping layer 240 contains silicon nitride.
  • the feature 202 includes the film stack 220 containing a SiGe/Si fin structure, each SiGe layer, each Si layer, and/or each Ge layer is formed by epitaxial growth and has a thickness of about 5 nm to about 30 nm.
  • the first capping layer 230 contains or is a silicon oxide layer deposited by CVD or ALD and has a thickness of about 2 nm to about 10 nm.
  • the second capping layer 240 contains or is silicon nitride layer deposited by CVD or ALD and has a thickness of about 10 nm to about 50 nm.
  • the densified oxide layer 250 contains silicon oxide deposited by flowable CVD processes described and discussed herein, densified by the densification processes (e.g., the first and second plasma treatments) described and discussed herein, and has a thickness of about 50 nm to about 500 nm.
  • the fill layer 260 contains silicon oxide deposited by CVD and has a thickness of about 5 nm to about 600 nm.
  • Embodiments of the present disclosure further relate to any one or more of the following paragraphs 1-21:
  • compositions, an element, or a group of elements are preceded with the transitional phrase “comprising”, it is understood that the same composition or group of elements with transitional phrases “consisting essentially of”, “consisting of”, “selected from the group of consisting of”, or “is” preceding the recitation of the composition, element, or elements and vice versa, are contemplated.
  • the term “about” refers to a +/ ⁇ 10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.

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Abstract

Embodiments of the present disclosure generally relate to methods for gap fill deposition and film densification on microelectronic devices. The method includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer. The second plasma treatment includes generating a second plasma by top and side RF sources and directing the second plasma to the treated oxide layer without a bias. The densified oxide layer has a final WER of less than one-half of the initial WER.

Description

BACKGROUND Field
Embodiments of the present disclosure generally relate to fabrication of microelectronic devices, and more specifically, relate to gap fill deposition and film densification during the fabrication of microelectronic devices.
Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produce devices with feature sizes of 10 nm and sub-10 nm, and new equipment is being developed and implemented to make devices with even smaller geometries. The decreasing feature sizes result in structural features on the device having decreased spatial dimensions. The widths of gaps and trenches on the device narrow to a point where the aspect ratio of gap depth to its width becomes high enough to make it challenging to fill the gap with dielectric material. The depositing dielectric material is prone to clog at the top before the gap completely fills, producing a void or seam in the middle of the gap.
Over the years, many techniques have been developed to avoid having dielectric material clog the top of a gap, or to “heal” the void or seam that has been formed. One approach has been to start with highly flowable precursor materials that may be applied in a liquid phase to a spinning substrate surface (e.g., SOG deposition techniques). These flowable precursors can flow into and fill very small substrate gaps without forming voids or weak seams. However, once these highly flowable materials are deposited, they have to be hardened into a solid dielectric material.
In many instances, the hardening includes a heat treatment to remove components from the deposited material to leave behind a solid dielectric material, such as silicon oxide. Some of these components were necessary to make the initially deposited film flowable. Departing components increase the density of the hardened dielectric material. The hardening dielectric material tends to shrink in volume, which can leave cracks and spaces at the interlace of the dielectric material and the surrounding substrate.
Spin-on dielectrics (SOD) have also been used to flow into features on a patterned substrate. Oxygen from the environment displaces other atoms to produce a silicon oxide layer. High temperature exposure to oxygen environments can ruin underlying layers for some circuit architectures. This consideration results in the need to stay within a “thermal budget” during a manufacturing process flow. Thermal budget considerations have largely limited SOD to process flows incorporating an underlying silicon nitride layer which can protect underlying features from oxidation (e.g., DRAM applications). Alternative methods have been developed which deposit silicon-nitrogen layers by radical-component chemical vapor deposition (CVD). Radical-component CVD can produce a silicon-nitrogen layer by exciting and combining one precursor with an unexcited silicon-containing precursor in the plasma-free substrate processing region.
One example of a microelectronic device which uses a dielectric layer and has gained a lot of interest to fabricate is the gate all around (GAA) transistor. The desired properties of the GAA transistors include improved direct current (DC) performance and short channel controllability over previous transistors. However, if heated for too long and/or at too great of a temperature, the Si/SiGe layers within the GAA transistor are susceptible to oxidation and film damage, as well as dopant diffusion, and intermixing of neighboring layers (e.g., between Si-layers and SiGe-layers). Such undesired results lead to at least shallow trench isolation (STI) field loss at downstream integration, if not complete device failure.
Therefore, there is a need for a method to perform gap fill deposition and film densification during the fabrication of microelectronic devices, such as GAA transistors.
SUMMARY
Embodiments of the present disclosure generally relate to methods for processing substrates during the fabrication of microelectronic devices, where the methods include gap fill deposition and film densification. A gate all around (GAA) transistor is one exemplary type of microelectronic device which can be fabricated with the methods described and discussed herein.
In one or more embodiments, a method for processing a substrate is provided and includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer while maintaining the substrate at a first temperature of less than 600° C. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer while maintaining the substrate at a second temperature of less than 600° C. The second plasma treatment includes generating a second plasma by a top RF source and a side RF source and directing the second plasma to the treated oxide layer without a bias. The densified oxide layer has a final WER of less than one-half of the initial WER.
In other embodiments, a method for processing a substrate is provided and includes forming an oxide layer containing silicon oxide and having an initial WER over features disposed on the substrate. In one or more examples, the oxide layer is formed by depositing a flowable film containing one or more polysilazanes on the features, curing the polysilazane to produce a solidified film containing silicon, nitrogen, and hydrogen, and converting the solidified film to the oxide layer containing silicon oxide during an oxidation process. The method also includes exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method further includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, where the densified oxide layer has a final WER of less than one-half of the initial WER. The second plasma treatment includes generating a second plasma by a top RF source and a side RF source and directing the second plasma to the treated oxide layer without a bias.
In some embodiments, a method for processing a substrate is provided and includes forming an oxide layer containing silicon oxide and having an initial WER over a plurality of fins disposed on the substrate. Each of the fins contains a film stack having alternating pairs of layers, where each of the pairs of layers contains a silicon-germanium layer and a silicon layer disposed on one another. The method also includes exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method further includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, where the densified oxide layer has a final WER of less than one-half of the initial WER. The second plasma treatment includes generating a second plasma by a top RF source and a side RF source and directing the second plasma to the treated oxide layer without a bias.
BRIEF DESCRIPTION OF THE DRAWINGS
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and the disclosure may admit to other equally effective embodiments.
FIG. 1 is a flow chart of an exemplary method for processing a substrate which includes gap fill deposition and film densification during the fabrication of a microelectronic device, according to one or more embodiments described and discussed herein.
FIGS. 2A-2B depict cross-sectional views of an exemplary microelectronic device prepared by the method illustrated in the flow chart of FIG. 1 , according to one or more embodiments described and discussed herein.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the Figures. It is contemplated that elements and features of one or more embodiments may be beneficially incorporated in other embodiments.
DETAILED DESCRIPTION
Embodiments of the present disclosure generally relate to methods for processing substrates during the fabrication of microelectronic devices, where the methods include gap fill deposition and film densification. The methods for gap fill deposition and film densification can be applied to the fabrication of semiconductor devices (e.g., transistors, capacitors, and the like), memory devices (e.g., NAND, DRAM, and the like), display devices (e.g., LCD, LED, and the like), solar and photovoltaic devices, as well as other electronic and microelectronic devices. In one or more examples, a gate all around (GAA) transistor can be fabricated with the methods described and discussed herein.
FIG. 1 is a flow chart of a method 100 for processing a substrate having features during the fabrication of a microelectronic device, according to one or more embodiments described and discussed herein. The method 100 includes gap fill deposition and film densification processes. The method 100 can include operations 110-140 as follows: forming or depositing an oxide layer containing silicon oxide over features on the substrate (110); exposing the oxide layer to a first plasma treatment to produce a treated oxide layer (120); exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer (130); and optionally forming or depositing a fill layer on or over the densified oxide layer (140).
At operation 110 of the method 100, an oxide layer is deposited, produced, or otherwise formed on and over the features on the substrate. The features can be or include multiple or a plurality of fins, columns, film stacks, layers, films, or other structures disposed on the substrate. For example, the features can be or include a plurality of fins. In one or more examples, each fin contains a film stack. The film stack can include alternating pairs of layers disposed on one another. In one or more examples, each of the pairs of layers contains silicon-germanium layers and silicon layers. Each of the silicon-germanium layers and silicon layers can independently be deposited or formed by an epitaxial growth process or an atomic layer deposition (ALD) process.
In one or more embodiments, the features can be or include a plurality of silicon-germanium/silicon (SiGe/Si) fin structures or a plurality of germanium/silicon (Ge/Si) fin structures. In some examples, each of the SiGe layers, the Si layers, or the Ge layers has a thickness of about 5 nm, about 8 nm, or about 10 nm to about 12 nm, about 15 nm, about 20 nm, about 25 nm, or about 30 nm.
The oxide layer formed on and over the features contains silicon oxide. In one or more embodiments, the oxide layer is formed by a multiple step process which includes depositing a flowable film onto and over the features so to fill the gaps or spaces between the features. The flowable film enabled void and seam free gap-fill. In some examples, the flowable film contains one or more polysilazanes. The flowable film or polysilazane is cured to produce a solidified film containing silicon, nitrogen, and hydrogen. The curing of the flowable film or polysilazane can be performed by exposure to one or more types of radiation, such as ultraviolet light, infrared light, visible light, microwave energy, plasma, thermal energy (e.g., heat), or any combination thereof. In one or more examples, the flowable film or polysilazane is cured with ultraviolet light to produce a solidified film. In embodiments where the flowable film contains one or more polysilazanes, the Si—Si bonds, the Si—N bonds, and the Si—H bonds are broken to incorporate oxygen into the material while producing Si—O bonds during the curing process. The flowable film is densified as being oxidized and less flowable and is converted to the solidified film containing silicon oxide.
The solidified film is an intermediate film that contains silicon oxide and contaminants, non-oxidized silicon, and/or partially oxidized silicon. The solidified film can be converted or otherwise transformed to the oxide layer containing silicon oxide during an oxidation process and/or an annealing process. In one or more examples, the oxidation process includes exposing the solidified film to steam and/or one or more other oxidizing agents during an anneal process to produce the oxide layer containing silicon oxide. The anneal process can include heating and/or maintaining the substrate at a temperature of less than 600° C., such as about 200° C., about 250° C., about 300° C., or about 350° C. to about 400° C., about 450° C., about 480° C., about 500° C., about 520° C., about 550° C., about 580° C., or about 590° C. while exposing the solidified film on the substrate to one or more oxidizing agents to form the oxide layer containing silicon oxide. Exemplary oxidizing agent can be or include water, steam, oxygen (O2), ozone, hydrogen peroxide, nitrous oxide, or any combination thereof.
The oxide layer containing silicon oxide is denser than the solidified film, but by performing the densification processes described and discussed herein, the oxide layer can be further densified to a desired density. The oxide layer containing silicon oxide has a porosity of less value compared to the porosity of the solidified film from which the oxide layer is prepared from.
The oxide layer can have an initial wet etch rate (WER) of greater than 3 Å/min, greater than 3.5 Å/min, or greater than 4 Å/min to about 4.5 Å/min, about 5 Å/min, about 6 Å/min, about 8 Å/min, about 10 Å/min, or greater. If normalized, the oxide layer has an initial wet etch rate ratio (WERR) is 1. Once the oxide layer is converted to the densified oxide layer, the WER and WERR values are reduced so that the densified oxide layer has lower WER and WERR values than the oxide layer from which the densified oxide layer was generated from. The WER values were calculated or otherwise determined during etch processes which include exposing the oxide layer to 1:100 HF:water (volumetric) at about 25° C. for about 2 hours.
The oxide layer can have a thickness of about 20 nm, about 35 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 500 nm, about 600 nm, about 800 nm, or 1,000 nm. For example, the oxide layer can have a thickness of about 20 nm to about 1,000 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 600 nm, about 50 nm to about 500 nm, about 50 nm to about 400 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 80 nm to about 1,000 nm, about 80 nm to about 800 nm, about 80 nm to about 600 nm, about 80 nm to about 500 nm, about 80 nm to about 400 nm, about 80 nm to about 300 nm, about 80 nm to about 200 nm, about 80 nm to about 100 nm, about 100 nm to about 1,000 nm, about 100 nm to about 800 nm, about 100 nm to about 600 nm, about 100 nm to about 500 nm, about 100 nm to about 400 nm, about 100 nm to about 300 nm, about 100 nm to about 250 nm, or about 100 nm to about 200 nm.
At operation 120 of the method 100, the oxide layer is exposed to a first plasma during a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating the first plasma by a first RF source and exposing the oxide layer to the first plasma to produce the treated oxide layer. A direct current (DC) bias can be used to direct the first and/or accelerating ions of the first plasma to the oxide layer. The DC bias can be generated from one or more electrodes below the substrate, such as within or part of the substrate support. In one or more examples, the first plasma is an inductively coupled plasma (ICP). The first plasma is ignited or otherwise formed from a process gas containing argon, helium, neon, xenon, nitrogen (N2), hydrogen (H2), oxygen (O2), ozone, or any combination thereof. The first plasma process can be conducted in a plasma chamber or system, such as the Varian VIISTA® PLAD™ plasma system, commercially available from Applied Materials, Inc.
The first RF source can have a power of about 0.1 kW, about 0.5 kW, about 0.8 kW, or about 1 kW to about 1.2 kW, about 1.5 kW, about 1.8 kW, about 2 kW, about 2.2 kW, about 2.5 kW, about 2.8 kW, or about 3 kW to generate the first plasma during the first plasma treatment. In some examples, the first RF source can have a power of about 3 kW or less than 3 kW. For example, the first RF source can have a power of about 0.1 kW to about 3 kW, about 0.1 kW to about 2.5 kW, about 0.1 kW to about 2 kW, about 0.1 kW to about 1.5 kW, about 0.1 kW to about 1 kW, about 0.1 kW to about 0.5 kW, about 1 kW to about 3 kW, about 1 kW to about 2.5 kW, about 1 kW to about 2 kW, about 1 kW to about 1.5 kW, about 1 kW to about 1 kW, about 1 kW to about 0.5 kW, about 1.5 kW to about 3 kW, about 1.5 kW to about 2.5 kW, about 1.5 kW to about 2 kW, or about 1.5 kW to about 1.8 kW during the first plasma treatment.
The DC bias can have a voltage of about 0.1 kV, about 0.5 kV, about 0.8 kV, about 1 kV, about 1.5 kV, or about 2 kV to about 2.5 kV, about 3 kV, about 3.5 kV, about 4 kV, about 5 kV, about 6 kV, about 7 kV, about 8 kV, about 9 kV, or about 10 kV during the first plasma treatment. For example, the DC bias can have a voltage of about 0.1 kV to about 10 kV, about 0.1 kV to about 8 kV, about 0.1 kV to about 7 kV, about 0.1 kV to about 6 kV, about 0.1 kV to about 5 kV, about 0.1 kV to about 4 kV, about 0.1 kV to about 2 kV, about 0.1 kV to about 1 kV, about 0.1 kV to about 0.5 kV, about 1 kV to about 10 kV, about 1 kV to about 8 kV, about 1 kV to about 7 kV, about 1 kV to about 6 kV, about 1 kV to about 5 kV, about 1 kV to about 4 kV, about 3 kV to about 10 kV, about 3 kV to about 8 kV, about 3 kV to about 7 kV, about 3 kV to about 6 kV, or about 3 kV to about 5 kV during the first plasma treatment.
The oxide layer is exposed to the first plasma at a dosage value of about 1×1014 ion/cm2, about 5×1014 ion/cm2, about 1×1015 ion/cm2, or about 4×1015 ion/cm2 to about 1×1016 ion/cm2, about 5×1016 ion/cm2, about 1×1017 ion/cm2, about 4×1017 ion/cm2, about 8×1017 ion/cm2, or about 1×1018 ion/cm2 during the first plasma treatment. For example, the oxide layer is exposed to the first plasma at a dosage value of about 1×1014 ion/cm2 to about 1×1018 ion/cm2, about 1×1014 ion/cm2 to about 5×1017 ion/cm2, about 1×1014 ion/cm2 to about 1×1017 ion/cm2, about 1×1014 ion/cm2 to about 5×1016 ion/cm2, about 1×1014 ion/cm2 to about 1×1016 ion/cm2, about 1×1014 ion/cm2 to about 1×1015 ion/cm2, about 1×1015 ion/cm2 to about 1×1018 ion/cm2, about 1×1015 ion/cm2 to about 5×1017 ion/cm2, about 1×1015 ion/cm2 to about 1×1017 ion/cm2, about 1×1015 ion/cm2 to about 5×1016 ion/cm2, or about 1×1015 ion/cm2 to about 1×1016 ion/cm2 during the first plasma treatment.
The substrate containing the oxide layer is heated or maintained at a first temperature during the first plasma treatment process. The first temperature is typically maintained at less than 600° C. so the features (e.g., fins) are not damaged during the first plasma treatment. The first temperature can be about 150° C., about 200° C., about 250° C., about 300° C., or about 350° C. to about 400° C., about 450° C., about 475° C., about 480° C., about 490° C., about 500° C., about 520° C., about 550° C., about 580° C., or about 590° C. For example, the first temperature can be about 150° C. to less than 600° C., about 200° C. to less than 600° C., about 250° C. to less than 600° C., about 300° C. to less than 600° C., about 350° C. to less than 600° C., about 400° C. to less than 600° C., about 450° C. to less than 600° C., about 500° C. to less than 600° C., about 550° C. to less than 600° C., about 300° C. to about 590° C., about 300° C. to about 575° C., about 300° C. to about 550° C., about 300° C. to about 525° C., about 300° C. to about 500° C., about 300° C. to about 450° C., about 250° C. to about 550° C., about 300° C. to about 550° C., about 350° C. to about 550° C., about 400° C. to about 550° C., about 450° C. to about 550° C., about 500° C. to about 550° C., about 250° C. to about 500° C., about 300° C. to about 500° C., about 350° C. to about 500° C., about 400° C. to about 500° C., about 450° C. to about 500° C., or about 475° C. to about 500° C.
At operation 130 of the method 100, the treated oxide layer is exposed to a second plasma during a second plasma treatment to produce a densified oxide layer. The densified oxide layer has a porosity of less value compared to the porosity of the treated oxide layer from which the densified oxide layer is prepared from. The second plasma is ignited, generated, or otherwise produced by at least two, three, or more plasma sources (e.g., a top RF source and a side RF source) during the second plasma treatment. The second plasma is directed to the treated oxide layer without a bias to produce the densified oxide layer. In one or more examples, the top RF source is positioned or otherwise located above the substrate and the side RF source is positioned or otherwise located adjacent or besides the substrate. In one or more examples, the second plasma is an ICP. The second plasma can also be a high-density plasma (HDP). The second plasma is ignited or otherwise formed from a process gas containing hydrogen (H2), oxygen (O2), ozone, nitrogen (N2), argon, helium, neon, xenon, or any combination thereof. The second plasma process can be conducted in a plasma chamber or system, such as the CENTURA ULTIMA® HDP-CVD plasma chamber or system, and/or the PRODUCER® PECVD chamber or system, commercially available from Applied Materials, Inc.
Each of the top RF source and the side RF source can independently have a power of about 0.5 kW, about 0.8 kW, about 1 kW, about 1.5 kW, about 2 kW, about 2.5 kW, about 3 kW, about 3.5 kW, about 4 kW, about 4.5 kW or about 5 kW to about 5.5 kW, about 6 kW, about 6.5 kW, about 7 kW, about 7.5 kW, about 8 kW, about 8.5 kW, about 8.8 kW, about 9 kW, about 10 kW, or greater to generate the second plasma during the second plasma treatment. In some examples, each of the top RF source and the side RF source can independently have a power of about 5 kW or greater than 5 kW. For example, each of the top RF source and the side RF source can independently have a power of about 0.5 kW to about 9 kW, about 1 kW to about 9 kW, about 1 kW to about 8.5 kW, about 1 kW to about 8 kW, about 1 kW to about 7.5 kW, about 1 kW to about 7 kW, about 1 kW to about 6.5 kW, about 1 kW to about 6 kW, about 1 kW to about 5 kW, about 1 kW to about 4 kW, about 1 kW to about 3 kW, about 3 kW to about 9 kW, about 3 kW to about 8.5 kW, about 3 kW to about 8 kW, about 3 kW to about 7.5 kW, about 3 kW to about 7 kW, about 3 kW to about 6.5 kW, about 3 kW to about 6 kW, about 3 kW to about 5 kW, about 5 kW to about 9 kW, about 5 kW to about 8.5 kW, about 5 kW to about 8 kW, about 5 kW to about 7.5 kW, about 5 kW to about 7 kW, about 5 kW to about 6.5 kW, or about 5 kW to about 6 kW during the second plasma treatment.
The substrate containing the treated oxide layer is heated or maintained at a second temperature during the second plasma treatment process. The second temperature is typically maintained at less than 600° C. so the features (e.g., fins) are not damaged during the second plasma treatment. The second temperature can be about 150° C., about 200° C., about 250° C., about 300° C., or about 350° C. to about 400° C., about 450° C., about 475° C., about 480° C., about 490° C., about 500° C., about 520° C., about 550° C., about 580° C., or about 590° C. For example, the second temperature can be about 150° C. to less than 600° C., about 200° C. to less than 600° C., about 250° C. to less than 600° C., about 300° C. to less than 600° C., about 350° C. to less than 600° C., about 400° C. to less than 600° C., about 450° C. to less than 600° C., about 500° C. to less than 600° C., about 550° C. to less than 600° C., about 300° C. to about 590° C., about 300° C. to about 575° C., about 300° C. to about 550° C., about 300° C. to about 525° C., about 300° C. to about 500° C., about 300° C. to about 450° C., about 250° C. to about 550° C., about 300° C. to about 550° C., about 350° C. to about 550° C., about 400° C. to about 550° C., about 450° C. to about 550° C., about 500° C. to about 550° C., about 250° C. to about 500° C., about 300° C. to about 500° C., about 350° C. to about 500° C., about 400° C. to about 500° C., about 450° C. to about 500° C., or about 475° C. to about 500° C.
The densified oxide layer has a WER (e.g., the final WER) which is less than the WER of the oxide layer (e.g., the initial WER) from which the densified oxide layer was generated from due to the exposures to the first and second plasma treatments. Similarly, by normalizing the wet etch rate ratio (e.g., the initial WERR) of the oxide layer to 1, then the WERR of the densified oxide layer (e.g., the final WERR) is less than 1.
In one or more embodiments, the final WER of the densified oxide layer is less than 2 Å/min, such as about 1.8 Å/min, as about 1.6 Å/min, about 1.5 Å/min, about 1.4 Å/min, about 1.2 Å/min, about 1 Å/min, about 0.8 Å/min, about 0.5 Å/min, about 0.3 Å/min, about 0.2 Å/min, about 0.1 Å/min, or less.
The final WER of the densified oxide layer is less than one-half of the initial WER of the oxide layer. In some examples, the final WER of the densified oxide layer can be about 0.45, about 0.4, about 0.35, about 0.32, about 0.3, about 0.28, about 0.25, about 0.22, about 0.2, about 0.18, about 0.15, about 0.12, about 0.1, or less than the initial WER of the oxide layer. These ratios are also considered the final WERR of the densified oxide layer. For example, the oxide layer has the initial WERR and the densified oxide layer has a final WERR of less than one-half of the initial WERR. The initial WERR of the oxide layer is 1 and the final WERR of the densified oxide layer is less than 0.5, such as about 0.05, about 0.08, about 0.1, about 0.12, about 0.15, or about 0.18 to about 0.2, about 0.22, about 0.25, about 0.28, about 0.3, about 0.32, about 0.35, about 0.38, about 0.4, about 0.42, about 0.45, about 0.46, about 0.48, or about 0.49. In one or more examples, the final WERR of the densified oxide layer is about 0.05 to about 0.48, about 0.1 to about 0.48, about 0.2 to about 0.48, about 0.25 to about 0.48, about 0.3 to about 0.48, about 0.33 to about 0.48, about 0.35 to about 0.48, about 0.38 to about 0.48, about 0.4 to about 0.48, about 0.05 to about 0.4, about 0.1 to about 0.4, about 0.2 to about 0.4, about 0.25 to about 0.4, about 0.25 to about 0.45, about 0.3 to about 0.4, about 0.33 to about 0.4, about 0.35 to about 0.4, about 0.38 to about 0.4, about 0.05 to about 0.35, about 0.1 to about 0.35, about 0.2 to about 0.35, about 0.25 to about 0.35, about 0.3 to about 0.35, about 0.33 to about 0.35, about 0.32 to about 0.38, about 0.32 to about 0.35, about 0.35 to about 0.38.
The densified oxide layer can have a thickness of about 20 nm, about 35 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 500 nm, about 600 nm, about 800 nm, or 1,000 nm. For example, the densified oxide layer can have a thickness of about 20 nm to about 1,000 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 600 nm, about 50 nm to about 500 nm, about 50 nm to about 400 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 80 nm to about 1,000 nm, about 80 nm to about 800 nm, about 80 nm to about 600 nm, about 80 nm to about 500 nm, about 80 nm to about 400 nm, about 80 nm to about 300 nm, about 80 nm to about 200 nm, about 80 nm to about 100 nm, about 100 nm to about 1,000 nm, about 100 nm to about 800 nm, about 100 nm to about 600 nm, about 100 nm to about 500 nm, about 100 nm to about 400 nm, about 100 nm to about 300 nm, about 100 nm to about 250 nm, or about 100 nm to about 200 nm.
At operation 140 of the method 100, one or more bulk or fill layers can optionally be deposited, produced, or otherwise formed over the densified oxide layer. The bulk or fill layer can be or contain one or more materials, such as silicon, silicon oxide, silicon nitride, silicon oxynitride, dopants thereof, or any combination thereof. Other materials can also be deposited for the bulk or fill layer. The bulk or fill layer can be deposited by one or more deposition process including chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), atomic layer deposition (ALD), plasma-enhanced ALD (PE-ALD), physical vapor deposition (PVD), sputtering, epitaxy, spin-on deposition, or any combination thereof. In one or more examples, the bulk or fill layer contains silicon oxide and is deposited by a thermal CVD process.
The bulk or fill layer can have a thickness of about 5 nm, about 10 nm, about 20 nm, about 35 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 600 nm, or greater. For example, the bulk or fill layer can have a thickness of about 5 nm to about 600 nm, about 10 nm to about 500 nm, about 50 nm to about 500 nm, about 100 nm to about 400 nm.
FIGS. 2A-2B depict cross-sectional views of a microelectronic device 200 which can be fabricated or otherwise prepared by the process 100, according to one or more embodiments described and discussed herein. The microelectronic device 200 can be or include one or more transistors, such as a GAA transistor.
FIG. 2A depicts the microelectronic device 200 containing a plurality of features 202 separated by spacings 204 disposed on a substrate 210. The features 202 can include a portion of the substrate 210, as shown, or alternative, be positioned or otherwise disposed on the substrate 210 (not shown). The features 202 can be or include multiple or a plurality of fins, columns, film stacks, layers, films, or other structures disposed on the substrate 210 and/or including a portion of the substrate 210. In one or more examples, each of the features 202 can be or include a fin containing a film stack 220.
The microelectronic device 200 also contains a densified oxide layer 250 disposed one and over the features 202 and a fill layer 260 disposed on and over the densified oxide layer 250. The densified oxide layer 250 can be deposited, produced, or otherwise formed by methods described and discussed herein, including process 100. In one or more examples, the densified oxide layer 250 contains silicon oxide, such as densified silicon oxide and the fill layer 260 contains silicon oxide, such as a silicon oxide deposited by vapor deposition (e.g., CVD or ALD).
FIG. 2B depicts the feature 202 containing the film stack 220, as described and discussed in one or more embodiments herein. The film stack 220 can have two, three, four, or more different types of layers or materials. As depicted in FIG. 2B, the film stack 220 contains alternating pairs of layers 222, 224 disposed on one another. In one or more examples, each of the pairs of layers 222, 224 contains silicon-germanium layers and silicon layers. In some examples, the layers 222 is or contains silicon-germanium layers and the layers 224 is or contains silicon layers. In other examples, the layers 222 is or contains silicon layers and the layers 224 is or contains silicon-germanium layers.
The film stack 220 also includes a first capping layer 230 layer disposed on the film stack 220 and a second capping layer 240 disposed on the first capping layer 230. In one or more examples, the first capping layer 230 contains silicon oxide and the second capping layer 240 contains silicon nitride.
In one or more examples, the feature 202 includes the film stack 220 containing a SiGe/Si fin structure, each SiGe layer, each Si layer, and/or each Ge layer is formed by epitaxial growth and has a thickness of about 5 nm to about 30 nm. The first capping layer 230 contains or is a silicon oxide layer deposited by CVD or ALD and has a thickness of about 2 nm to about 10 nm. The second capping layer 240 contains or is silicon nitride layer deposited by CVD or ALD and has a thickness of about 10 nm to about 50 nm. The densified oxide layer 250 contains silicon oxide deposited by flowable CVD processes described and discussed herein, densified by the densification processes (e.g., the first and second plasma treatments) described and discussed herein, and has a thickness of about 50 nm to about 500 nm. The fill layer 260 contains silicon oxide deposited by CVD and has a thickness of about 5 nm to about 600 nm.
Embodiments of the present disclosure further relate to any one or more of the following paragraphs 1-21:
    • 1. A method for processing a substrate, comprising: forming an oxide layer comprising silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate; exposing the oxide layer to a first plasma treatment to produce a treated oxide layer while maintaining the substrate at a first temperature of less than 600° C., wherein the first plasma treatment comprises: generating a first plasma by a first RF source; and directing the first plasma to the oxide layer by a DC bias; and then exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer while maintaining the substrate at a second temperature of less than 600° C., wherein the densified oxide layer has a final WER of less than one-half of the initial WER, and wherein the second plasma treatment comprises: generating a second plasma by a top RF source and a side RF source; and directing the second plasma to the treated oxide layer without a bias.
    • 2. A method for processing a substrate, comprising: forming an oxide layer comprising silicon oxide and having a WER over features disposed on the substrate, wherein forming the oxide layer comprises; depositing a flowable film comprising a polysilazane on the features; curing the polysilazane to produce a solidified film comprising silicon, nitrogen, and hydrogen; and converting the solidified film to the oxide layer comprising silicon oxide during an oxidation process; exposing the oxide layer to a first plasma treatment to produce a treated oxide layer, wherein the first plasma treatment comprises: generating a first plasma by a first RF source; and directing the first plasma to the oxide layer by a DC bias; and then exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, wherein the densified oxide layer has a final WER of less than one-half of the initial WER, and wherein the second plasma treatment comprises: generating a second plasma by a top RF source and a side RF source; and directing the second plasma to the treated oxide layer without a bias.
    • 3. A method for processing a substrate, comprising: forming an oxide layer comprising silicon oxide and having a WER over a plurality of fins disposed on the substrate, wherein each of the fins comprises a film stack containing alternating pairs of layers, wherein each of the pairs of layers contains a silicon-germanium layer and a silicon layer disposed on one another; exposing the oxide layer to a first plasma treatment to produce a treated oxide layer, wherein the first plasma treatment comprises: generating a first plasma by a first RF source; and directing the first plasma to the oxide layer by a DC bias; and then exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, wherein the densified oxide layer has a final WER of less than one-half of the initial WER, and wherein the second plasma treatment comprises: generating a second plasma by a top RF source and a side RF source; and directing the second plasma to the treated oxide layer without a bias.
    • 4. The method according to any one of paragraphs 1-3, wherein the initial WER is greater than 4 Å/min and the final WER is less than 2 Å/min.
    • 5. The method according to any one of paragraphs 1-4, wherein the oxide layer comprising silicon oxide has an initial wet etch rate ratio (WERR) and the densified oxide layer has a final WERR of less than one-half of the initial WERR.
    • 6. The method according to paragraph 5, wherein the initial wet etch rate ratio (WERR) is 1 and the final WERR is about 0.2 to about 0.48.
    • 7. The method according to any one of paragraphs 1-6, wherein the first RF source has a power of about 0.1 kW to about 3 kW when generating the first plasma during the first plasma treatment.
    • 8. The method according to any one of paragraphs 1-7, wherein the DC bias has a voltage of about 0.1 kV to about 10 kV during the first plasma treatment.
    • 9. The method according to any one of paragraphs 1-8, wherein the oxide layer is exposed to the first plasma at a dosage value of about 1×1014 ion/cm2 to about 1×1018 ion/cm2 during the first plasma treatment.
    • 10. The method according to any one of paragraphs 1-9, wherein each of the top RF source and the side RF source independently has a power of about 1 kW to about 9 kW when generating the second plasma during the second plasma treatment.
    • 11. The method according to any one of paragraphs 1-10, wherein each of the first temperature and the second temperature is independently about 300° C. to about 575° C.
    • 12. The method according to any one of paragraphs 1-11, wherein the densified oxide layer has a porosity of less value compared to the porosity of the treated oxide layer from which the densified oxide layer is prepared from.
    • 13. The method according to any one of paragraphs 1-12, wherein forming the oxide layer further comprises: depositing a flowable film comprising a polysilazane on the features; curing the polysilazane to produce a solidified film comprising silicon, nitrogen, and hydrogen; and converting the solidified film to the oxide layer comprising silicon oxide during an oxidation process.
    • 14. The method according to paragraph 13, wherein the oxidation process comprises exposing the solidified film to steam during an anneal process.
    • 15. The method according to paragraph 14, wherein the substrate is maintained at a temperature of less than 600° C. during the anneal process.
    • 16. The method according to paragraph 13, wherein the polysilazane is cured with ultraviolet light to produce the solidified film.
    • 17. The method according to any one of paragraphs 1-16, further comprising depositing a fill layer over the densified oxide layer.
    • 18. The method according to paragraph 17, wherein the fill layer comprises silicon oxide and is deposited by chemical vapor deposition.
    • 19. The method according to any one of paragraphs 1-18, wherein the features disposed on the substrate are a plurality of fins.
    • 20. The method according to paragraph 19, wherein each of the fins comprises a film stack containing alternating pairs of layers,
    • 21. The method according to paragraph 20, wherein each of the pairs of layers contains a silicon-germanium layer and a silicon layer disposed on one another.
While the foregoing is directed to embodiments of the disclosure, other and further embodiments may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. All documents described herein are incorporated by reference herein, including any priority documents and/or testing procedures to the extent they are not inconsistent with this text. As is apparent from the foregoing general description and the specific embodiments, while forms of the present disclosure have been illustrated and described, various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, it is not intended that the present disclosure be limited thereby. Likewise, the term “comprising” is considered synonymous with the term “including” for purposes of United States law. Likewise, whenever a composition, an element, or a group of elements is preceded with the transitional phrase “comprising”, it is understood that the same composition or group of elements with transitional phrases “consisting essentially of”, “consisting of”, “selected from the group of consisting of”, or “is” preceding the recitation of the composition, element, or elements and vice versa, are contemplated. As used herein, the term “about” refers to a +/−10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.
Certain embodiments and features have been described using a set of numerical upper limits and a set of numerical lower limits. It should be appreciated that ranges including the combination of any two values, e.g., the combination of any lower value with any upper value, the combination of any two lower values, and/or the combination of any two upper values are contemplated unless otherwise indicated. Certain lower limits, upper limits and ranges appear in one or more claims below.

Claims (20)

What is claimed is:
1. A method for processing a substrate, comprising:
forming an oxide layer comprising silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, wherein the initial WER is determined with an etchant having a concentration;
exposing the oxide layer to a first plasma treatment to produce a treated oxide layer while maintaining the substrate at a first temperature of less than 600° C., wherein the first plasma treatment comprises:
generating a first plasma by a first RF source; and
directing the first plasma to the oxide layer by a DC bias; and then
exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer while maintaining the substrate at a second temperature of less than 600° C., wherein the densified oxide layer has a final WER of less than one-half of the initial WER, wherein the final WER is determined with the etchant having the concentration, wherein the oxide layer comprising silicon oxide has a normalized wet etch rate ratio (WERR) of 1 and the densified oxide layer has a final WERR of about 0.1 to about 0.48, and wherein the second plasma treatment comprises:
generating a second plasma by a top RF source and a side RF source; and
directing the second plasma to the treated oxide layer without a bias.
2. The method of claim 1, wherein the initial WER is greater than 4 Å/min and the final WER is less than 2 Å/min.
3. The method of claim 2, wherein the initial WER is about 5 Å/min to about 10 Å/min.
4. The method of claim 1, wherein the final WERR is about 0.1 to about 0.35.
5. The method of claim 1, wherein the first RF source has a power of about 0.1 kW to about 3 kW when generating the first plasma during the first plasma treatment.
6. The method of claim 1, wherein the DC bias has a voltage of about 0.1 kV to about 10 kV during the first plasma treatment.
7. The method of claim 1, wherein the oxide layer is exposed to the first plasma at a dosage value of about 1×1014 ion/cm2 to about 1×1018 ion/cm2 during the first plasma treatment.
8. The method of claim 1, wherein each of the top RF source and the side RF source independently has a power of about 1 kW to about 9 kW when generating the second plasma during the second plasma treatment.
9. The method of claim 1, wherein each of the first temperature and the second temperature is independently about 300° C. to about 575° C.
10. The method of claim 1, wherein the densified oxide layer has a porosity of less value compared to the porosity of the treated oxide layer from which the densified oxide layer is prepared from.
11. The method of claim 1, wherein forming the oxide layer further comprises:
depositing a flowable film comprising a polysilazane on the features;
curing the polysilazane to produce a solidified film comprising silicon, nitrogen, and hydrogen; and
converting the solidified film to the oxide layer comprising silicon oxide during an oxidation process.
12. The method of claim 11, wherein the oxidation process comprises exposing the solidified film to steam during an anneal process.
13. The method of claim 12, wherein the substrate is maintained at a temperature of less than 600° C. during the anneal process.
14. The method of claim 11, wherein the polysilazane is cured with ultraviolet light to produce the solidified film.
15. The method of claim 1, further comprising depositing a fill layer over the densified oxide layer.
16. The method of claim 15, wherein the fill layer comprises silicon oxide and is deposited by chemical vapor deposition.
17. The method of claim 1, wherein the features disposed on the substrate are a plurality of fins.
18. The method of claim 17, wherein each of the fins comprises a film stack containing alternating pairs of layers, wherein each of the pairs of layers contains a silicon-germanium layer and a silicon layer disposed on one another.
19. A method for processing a substrate, comprising:
forming an oxide layer comprising silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, wherein the initial WER is determined with an etchant having a concentration, and wherein forming the oxide layer comprises;
depositing a flowable film comprising a polysilazane on the features;
curing the polysilazane to produce a solidified film comprising silicon, nitrogen, and hydrogen; and
converting the solidified film to the oxide layer comprising silicon oxide during an oxidation process;
exposing the oxide layer to a first plasma treatment to produce a treated oxide layer, wherein the first plasma treatment comprises:
generating a first plasma by a first RF source; and
directing the first plasma to the oxide layer by a DC bias; and then
exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, wherein the densified oxide layer has a final WER of less than one-half of the initial WER, wherein the final WER is determined with the etchant having the concentration, and wherein the oxide layer comprising silicon oxide has a normalized wet etch rate ratio (WERR) of 1 and the densified oxide layer has a final WERR of about 0.1 to about 0.4, and wherein the second plasma treatment comprises:
generating a second plasma by a top RF source and a side RF source; and
directing the second plasma to the treated oxide layer without a bias.
20. A method for processing a substrate, comprising:
forming an oxide layer comprising silicon oxide and having an initial wet etch rate (WER) over a plurality of fins disposed on the substrate, wherein the initial WER is determined with an etchant having a concentration, and wherein each of the fins comprises a film stack containing alternating pairs of layers, wherein each of the pairs of layers contains a silicon-germanium layer and a silicon layer disposed on one another;
exposing the oxide layer to a first plasma treatment to produce a treated oxide layer, wherein the first plasma treatment comprises:
generating a first plasma by a first RF source; and
directing the first plasma to the oxide layer by a DC bias; and then
exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer, wherein the initial WER is greater than 4 Å/min, wherein the densified oxide layer has a final WER of less than 2 Å/min, wherein the final WER is determined with the etchant having the concentration, and wherein the second plasma treatment comprises:
generating a second plasma by a top RF source and a side RF source; and
directing the second plasma to the treated oxide layer without a bias, and
wherein the oxide layer comprising silicon oxide has a normalized wet etch rate ratio (WERR) of 1 and the densified oxide layer has a final WERR of about 0.1 to about 0.48.
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Citations (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270267A (en) * 1989-05-31 1993-12-14 Mitel Corporation Curing and passivation of spin on glasses by a plasma process wherein an external polarization field is applied to the substrate
US6214749B1 (en) * 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices
US6221782B1 (en) * 1994-12-15 2001-04-24 Applied Materials, Inc. Adjusting DC bias voltage in plasma chamber
US20040018319A1 (en) 2001-09-14 2004-01-29 Carlo Waldfried Ultraviolet curing processes for advanced low-k materials
US20060003596A1 (en) * 2004-07-01 2006-01-05 Micron Technology, Inc. Low temperature process for polysilazane oxidation/densification
US7148155B1 (en) 2004-10-26 2006-12-12 Novellus Systems, Inc. Sequential deposition/anneal film densification method
US20070111543A1 (en) 2005-11-15 2007-05-17 Applied Materials, Inc. Methods for improving low k FSG film gap-fill characteristics
US20070298585A1 (en) 2006-06-22 2007-12-27 Applied Materials, Inc. Dielectric deposition and etch back processes for bottom up gapfill
US20080115726A1 (en) 2004-08-27 2008-05-22 Applied Materials, Inc. gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials
US20080128870A1 (en) 2004-01-26 2008-06-05 Katz Zachary B Semiconductor Constructions
US20100330814A1 (en) 2009-06-29 2010-12-30 Applied Materials, Inc. Methods of forming oxide layers on substrates
US7935643B2 (en) 2009-08-06 2011-05-03 Applied Materials, Inc. Stress management for tensile films
US20120003840A1 (en) 2010-01-07 2012-01-05 Applied Materials Inc. In-situ ozone cure for radical-component cvd
US8101531B1 (en) 2010-09-23 2012-01-24 Novellus Systems, Inc. Plasma-activated deposition of conformal films
US20120068242A1 (en) 2010-09-16 2012-03-22 Seung-Mok Shin Semiconductor devices and methods of fabricating the same
US20120077349A1 (en) 2010-09-23 2012-03-29 Ming Li Plasma-activated deposition of conformal films
US20120112188A1 (en) 2010-11-08 2012-05-10 Showa Denko K.K. Semiconductor light-emitting device, manufacturing method thereof, and lamp
US20120135212A1 (en) 2010-11-26 2012-05-31 Hon Hai Precision Industry Co., Ltd. Coated article and method for making same
US20120149213A1 (en) 2010-12-09 2012-06-14 Lakshminarayana Nittala Bottom up fill in high aspect ratio trenches
US20120266819A1 (en) 2011-04-25 2012-10-25 Applied Materials, Inc. Semiconductor substrate processing system
US20120269989A1 (en) 2011-04-20 2012-10-25 Applied Materials, Inc. Low temperature silicon oxide conversion
US20120276407A1 (en) 2011-04-27 2012-11-01 Hon Hai Precision Industry Co., Ltd. Process for surface treating iron-based alloy and article
US8318584B2 (en) 2010-07-30 2012-11-27 Applied Materials, Inc. Oxide-rich liner layer for flowable CVD gapfill
US8329587B2 (en) 2009-10-05 2012-12-11 Applied Materials, Inc. Post-planarization densification
US20130029096A1 (en) 2011-07-29 2013-01-31 Hon Hai Precision Industry Co., Ltd. Coated article and method for making same
US20130049064A1 (en) 2010-04-30 2013-02-28 Canon Anelva Corporation Epitaxial film forming method, vacuum processing apparatus, semiconductor light emitting element manufacturing method, semiconductor light emitting element, and illuminating device
US20130217240A1 (en) 2011-09-09 2013-08-22 Applied Materials, Inc. Flowable silicon-carbon-nitrogen layers for semiconductor processing
US20130217241A1 (en) 2011-09-09 2013-08-22 Applied Materials, Inc. Treatments for decreasing etch rates after flowable deposition of silicon-carbon-and-nitrogen-containing layers
US20130230387A1 (en) * 2012-03-05 2013-09-05 Maricela Carlota Silva Propeller blade seal positioning gauge
US20130230987A1 (en) 2012-03-05 2013-09-05 Nerissa Draeger Flowable oxide film with tunable wet etch rate
US20130288485A1 (en) 2012-04-30 2013-10-31 Applied Materials, Inc. Densification for flowable films
US8575819B1 (en) 2011-07-18 2013-11-05 Integrated Device Technology, Inc. Microelectromechanical resonators with passive frequency tuning using built-in piezoelectric-based varactors
US20140011013A1 (en) 2010-12-20 2014-01-09 The Regents Of The University Of California Superhydrophobic and superoleophobic nanosurfaces
US20140017904A1 (en) 2004-03-25 2014-01-16 Novellus Systems, Inc. Flowable film dielectric gap fill process
US20140030830A1 (en) 2012-07-30 2014-01-30 Electronics And Telecommunications Research Institute Method of fabricating organic light emitting device
US20140134812A1 (en) 2012-11-13 2014-05-15 Dong-chan Kim Method of fabricating semiconductor device
US20140302690A1 (en) 2013-04-04 2014-10-09 Applied Materials, Inc. Chemical linkers to impart improved mechanical strength to flowable films
US20140329027A1 (en) 2013-05-02 2014-11-06 Applied Materials, Inc. Low temperature flowable curing for stress accommodation
US20150179501A1 (en) 2013-12-24 2015-06-25 Ritesh Jhaveri Techniques for trench isolation using flowable dielectric materials
US20150348773A1 (en) 2012-07-02 2015-12-03 Applied Materials, Inc. Aluminum-nitride buffer and active layers by physical vapor deposition
US20160020092A1 (en) 2010-09-23 2016-01-21 Lam Research Corporation Methods for depositing silicon oxide
US20160126089A1 (en) 2014-10-29 2016-05-05 Applied Materials, Inc. Flowable film curing penetration depth improvement and stress tuning
US20160194758A1 (en) 2015-01-07 2016-07-07 Applied Materials, Inc. Advanced process flow for high quality fcvd films
US20160240681A1 (en) * 2014-06-27 2016-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked Gate-All-Around FinFET and Method Forming the Same
US20160244879A1 (en) 2015-02-23 2016-08-25 Applied Materials, Inc. Cyclic sequential processes for forming high quality thin films
US9431268B2 (en) * 2015-01-05 2016-08-30 Lam Research Corporation Isotropic atomic layer etch for silicon and germanium oxides
US9552978B1 (en) * 2016-03-02 2017-01-24 United Microelectronics Corp. Method of decreasing fin bending
US20170194430A1 (en) 2016-01-05 2017-07-06 Applied Materials, Inc. Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications
US20170323785A1 (en) 2016-05-06 2017-11-09 Lam Research Corporation Method to deposit conformal and low wet etch rate encapsulation layer using pecvd
US9847222B2 (en) * 2013-10-25 2017-12-19 Lam Research Corporation Treatment for flowable dielectric deposition on substrate surfaces
US9875888B2 (en) * 2014-10-03 2018-01-23 Applied Materials, Inc. High temperature silicon oxide atomic layer deposition technology
US9941445B2 (en) 2014-06-04 2018-04-10 Université D'aix-Marseille Method for randomly texturing a semiconductor substrate
US10096466B2 (en) * 2015-03-17 2018-10-09 Applied Materials, Inc. Pulsed plasma for film deposition
US20180330980A1 (en) 2017-05-13 2018-11-15 Applied Materials, Inc. Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions
US20200251328A1 (en) * 2019-02-01 2020-08-06 Asm Ip Holding B.V. Method of topology-selective film formation of silicon oxide
US20200312652A1 (en) * 2019-04-01 2020-10-01 Asm Ip Holding B.V. Method for manufacturing a semiconductor device

Patent Citations (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270267A (en) * 1989-05-31 1993-12-14 Mitel Corporation Curing and passivation of spin on glasses by a plasma process wherein an external polarization field is applied to the substrate
US6214749B1 (en) * 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices
US6221782B1 (en) * 1994-12-15 2001-04-24 Applied Materials, Inc. Adjusting DC bias voltage in plasma chamber
US20040018319A1 (en) 2001-09-14 2004-01-29 Carlo Waldfried Ultraviolet curing processes for advanced low-k materials
US6756085B2 (en) 2001-09-14 2004-06-29 Axcelis Technologies, Inc. Ultraviolet curing processes for advanced low-k materials
US20080128870A1 (en) 2004-01-26 2008-06-05 Katz Zachary B Semiconductor Constructions
US20140017904A1 (en) 2004-03-25 2014-01-16 Novellus Systems, Inc. Flowable film dielectric gap fill process
US20060003596A1 (en) * 2004-07-01 2006-01-05 Micron Technology, Inc. Low temperature process for polysilazane oxidation/densification
US20080115726A1 (en) 2004-08-27 2008-05-22 Applied Materials, Inc. gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials
US7148155B1 (en) 2004-10-26 2006-12-12 Novellus Systems, Inc. Sequential deposition/anneal film densification method
US20070111543A1 (en) 2005-11-15 2007-05-17 Applied Materials, Inc. Methods for improving low k FSG film gap-fill characteristics
US20070298585A1 (en) 2006-06-22 2007-12-27 Applied Materials, Inc. Dielectric deposition and etch back processes for bottom up gapfill
US20100330814A1 (en) 2009-06-29 2010-12-30 Applied Materials, Inc. Methods of forming oxide layers on substrates
US7935643B2 (en) 2009-08-06 2011-05-03 Applied Materials, Inc. Stress management for tensile films
US8329587B2 (en) 2009-10-05 2012-12-11 Applied Materials, Inc. Post-planarization densification
US20120003840A1 (en) 2010-01-07 2012-01-05 Applied Materials Inc. In-situ ozone cure for radical-component cvd
US8304351B2 (en) 2010-01-07 2012-11-06 Applied Materials, Inc. In-situ ozone cure for radical-component CVD
US20130049064A1 (en) 2010-04-30 2013-02-28 Canon Anelva Corporation Epitaxial film forming method, vacuum processing apparatus, semiconductor light emitting element manufacturing method, semiconductor light emitting element, and illuminating device
US8318584B2 (en) 2010-07-30 2012-11-27 Applied Materials, Inc. Oxide-rich liner layer for flowable CVD gapfill
US20120068242A1 (en) 2010-09-16 2012-03-22 Seung-Mok Shin Semiconductor devices and methods of fabricating the same
US8101531B1 (en) 2010-09-23 2012-01-24 Novellus Systems, Inc. Plasma-activated deposition of conformal films
US20160020092A1 (en) 2010-09-23 2016-01-21 Lam Research Corporation Methods for depositing silicon oxide
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
US20120077349A1 (en) 2010-09-23 2012-03-29 Ming Li Plasma-activated deposition of conformal films
US8524612B2 (en) 2010-09-23 2013-09-03 Novellus Systems, Inc. Plasma-activated deposition of conformal films
US20130319329A1 (en) 2010-09-23 2013-12-05 Novellus Systems, Inc. Plasma-activated deposition of conformal films
US20120112188A1 (en) 2010-11-08 2012-05-10 Showa Denko K.K. Semiconductor light-emitting device, manufacturing method thereof, and lamp
US20120135212A1 (en) 2010-11-26 2012-05-31 Hon Hai Precision Industry Co., Ltd. Coated article and method for making same
US20120149213A1 (en) 2010-12-09 2012-06-14 Lakshminarayana Nittala Bottom up fill in high aspect ratio trenches
US20140011013A1 (en) 2010-12-20 2014-01-09 The Regents Of The University Of California Superhydrophobic and superoleophobic nanosurfaces
US20120269989A1 (en) 2011-04-20 2012-10-25 Applied Materials, Inc. Low temperature silicon oxide conversion
US8445078B2 (en) 2011-04-20 2013-05-21 Applied Materials, Inc. Low temperature silicon oxide conversion
US20120266819A1 (en) 2011-04-25 2012-10-25 Applied Materials, Inc. Semiconductor substrate processing system
US20120276407A1 (en) 2011-04-27 2012-11-01 Hon Hai Precision Industry Co., Ltd. Process for surface treating iron-based alloy and article
US8575819B1 (en) 2011-07-18 2013-11-05 Integrated Device Technology, Inc. Microelectromechanical resonators with passive frequency tuning using built-in piezoelectric-based varactors
US20130029096A1 (en) 2011-07-29 2013-01-31 Hon Hai Precision Industry Co., Ltd. Coated article and method for making same
US20130217240A1 (en) 2011-09-09 2013-08-22 Applied Materials, Inc. Flowable silicon-carbon-nitrogen layers for semiconductor processing
US20130217241A1 (en) 2011-09-09 2013-08-22 Applied Materials, Inc. Treatments for decreasing etch rates after flowable deposition of silicon-carbon-and-nitrogen-containing layers
US20150044882A1 (en) 2012-03-05 2015-02-12 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
US20130230987A1 (en) 2012-03-05 2013-09-05 Nerissa Draeger Flowable oxide film with tunable wet etch rate
US8846536B2 (en) 2012-03-05 2014-09-30 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
US20130230387A1 (en) * 2012-03-05 2013-09-05 Maricela Carlota Silva Propeller blade seal positioning gauge
US9299559B2 (en) 2012-03-05 2016-03-29 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
US20130288485A1 (en) 2012-04-30 2013-10-31 Applied Materials, Inc. Densification for flowable films
US20150348773A1 (en) 2012-07-02 2015-12-03 Applied Materials, Inc. Aluminum-nitride buffer and active layers by physical vapor deposition
US10109481B2 (en) 2012-07-02 2018-10-23 Applied Materials, Inc. Aluminum-nitride buffer and active layers by physical vapor deposition
US20140030830A1 (en) 2012-07-30 2014-01-30 Electronics And Telecommunications Research Institute Method of fabricating organic light emitting device
US20140134812A1 (en) 2012-11-13 2014-05-15 Dong-chan Kim Method of fabricating semiconductor device
US20140302690A1 (en) 2013-04-04 2014-10-09 Applied Materials, Inc. Chemical linkers to impart improved mechanical strength to flowable films
US20140329027A1 (en) 2013-05-02 2014-11-06 Applied Materials, Inc. Low temperature flowable curing for stress accommodation
US9847222B2 (en) * 2013-10-25 2017-12-19 Lam Research Corporation Treatment for flowable dielectric deposition on substrate surfaces
US20150179501A1 (en) 2013-12-24 2015-06-25 Ritesh Jhaveri Techniques for trench isolation using flowable dielectric materials
US9941445B2 (en) 2014-06-04 2018-04-10 Université D'aix-Marseille Method for randomly texturing a semiconductor substrate
US20160240681A1 (en) * 2014-06-27 2016-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked Gate-All-Around FinFET and Method Forming the Same
US9875888B2 (en) * 2014-10-03 2018-01-23 Applied Materials, Inc. High temperature silicon oxide atomic layer deposition technology
US20160126089A1 (en) 2014-10-29 2016-05-05 Applied Materials, Inc. Flowable film curing penetration depth improvement and stress tuning
US9570287B2 (en) 2014-10-29 2017-02-14 Applied Materials, Inc. Flowable film curing penetration depth improvement and stress tuning
US9431268B2 (en) * 2015-01-05 2016-08-30 Lam Research Corporation Isotropic atomic layer etch for silicon and germanium oxides
US20160194758A1 (en) 2015-01-07 2016-07-07 Applied Materials, Inc. Advanced process flow for high quality fcvd films
US20160244879A1 (en) 2015-02-23 2016-08-25 Applied Materials, Inc. Cyclic sequential processes for forming high quality thin films
US10041167B2 (en) 2015-02-23 2018-08-07 Applied Materials, Inc. Cyclic sequential processes for forming high quality thin films
US10096466B2 (en) * 2015-03-17 2018-10-09 Applied Materials, Inc. Pulsed plasma for film deposition
US20170194430A1 (en) 2016-01-05 2017-07-06 Applied Materials, Inc. Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications
US9552978B1 (en) * 2016-03-02 2017-01-24 United Microelectronics Corp. Method of decreasing fin bending
US20190157078A1 (en) 2016-05-06 2019-05-23 Lam Research Corporation Methods of encapsulation
US20170323785A1 (en) 2016-05-06 2017-11-09 Lam Research Corporation Method to deposit conformal and low wet etch rate encapsulation layer using pecvd
US10157736B2 (en) 2016-05-06 2018-12-18 Lam Research Corporation Methods of encapsulation
US20170323803A1 (en) 2016-05-06 2017-11-09 Lam Research Corporation Methods of encapsulation
US10566186B2 (en) 2016-05-06 2020-02-18 Lam Research Corporation Methods of encapsulation
US20200152452A1 (en) 2016-05-06 2020-05-14 Lam Research Corporation Methods of encapsulation
US10763107B2 (en) 2016-05-06 2020-09-01 Lam Research Corporation Methods of encapsulation
US20180330980A1 (en) 2017-05-13 2018-11-15 Applied Materials, Inc. Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions
US10707116B2 (en) 2017-05-13 2020-07-07 Applied Materials, Inc. Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions
US20200286773A1 (en) 2017-05-13 2020-09-10 Applied Materials, Inc. Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions
US11152248B2 (en) 2017-05-13 2021-10-19 Applied Materials, Inc. Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions
US20200251328A1 (en) * 2019-02-01 2020-08-06 Asm Ip Holding B.V. Method of topology-selective film formation of silicon oxide
US20200312652A1 (en) * 2019-04-01 2020-10-01 Asm Ip Holding B.V. Method for manufacturing a semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
International Search Report and Written Opinion dated Nov. 7, 2022 for Application No. PCT/US2022/036882.
Provine et al., "Correlation of film density and wet etch rate in hydrofluoric acid of plasma enhancedatomic layer deposited silicon nitride" AIP Advances 6, 065012 (2016), 9 pages.
Reinhardt, Handbook of Cleaning for Semiconductor Manufacturing (Wiley 2011) pp. 95-110 (Year: 2011). *

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