US12062661B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US12062661B2
US12062661B2 US17/831,861 US202217831861A US12062661B2 US 12062661 B2 US12062661 B2 US 12062661B2 US 202217831861 A US202217831861 A US 202217831861A US 12062661 B2 US12062661 B2 US 12062661B2
Authority
US
United States
Prior art keywords
pattern
patterns
channel patterns
active
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/831,861
Other versions
US20220302115A1 (en
Inventor
Jongho Park
Jaeyeol Song
Wandon Kim
Byounghoon Lee
Musarrat Hasan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to US17/831,861 priority Critical patent/US12062661B2/en
Publication of US20220302115A1 publication Critical patent/US20220302115A1/en
Application granted granted Critical
Publication of US12062661B2 publication Critical patent/US12062661B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H01L27/0922—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H01L21/823807—
    • H01L21/823814—
    • H01L21/823821—
    • H01L21/823842—
    • H01L21/823857—
    • H01L21/823871—
    • H01L27/0924—
    • H01L29/0653—
    • H01L29/0673—
    • H01L29/0847—
    • H01L29/1054—
    • H01L29/161—
    • H01L29/41791—
    • H01L29/42392—
    • H01L29/4908—
    • H01L29/4966—
    • H01L29/516—
    • H01L29/517—
    • H01L29/66545—
    • H01L29/7848—
    • H01L29/78696—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/701—IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/689—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs

Definitions

  • Embodiments of the inventive concepts relate to a semiconductor device and, more particularly, to a semiconductor device including a field effect transistor and a method for manufacturing the same.
  • Semiconductor devices may include integrated circuits including metal-oxide-semiconductor field effect transistors (MOSFETs). As sizes and design rules of semiconductor devices have been reduced, MOSFETs have been scaled down. Operating characteristics of semiconductor devices may be deteriorated by reduction in size of MOSFETs. Accordingly, various methods for forming semiconductor devices which have excellent performance while overcoming limitations by the high integration have been studied.
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • Embodiments of the inventive concepts may provide a semiconductor device with improved electrical characteristics.
  • a semiconductor device may include a substrate including a first active region and a second active region, a first active pattern and a second active pattern on the first and second active regions, respectively, a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns, which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns, which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively.
  • Each of the first and second gate electrodes may include a first metal pattern adjacent to a corresponding one of the first and second channel patterns.
  • the first and second channel patterns may include silicon-germanium (SiGe).
  • a concentration of germanium (Ge) of the second channel pattern may be higher than a concentration of germanium (Ge) of the first channel pattern, and a thickness of the first metal pattern of the second gate electrode may be greater than a thickness of the first metal pattern of the first gate electrode.
  • a semiconductor device may include a substrate including a first active region and a second active region, a first active pattern and a second active pattern on the first and second active regions, respectively, a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns, which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns, which are provided in an upper portion of the second active pattern, first and second gate electrodes intersecting the first and second channel patterns, respectively, a first gate dielectric pattern between the first gate electrode and the first channel pattern, and a second gate dielectric pattern between the second gate electrode and the second channel pattern.
  • a concentration of germanium (Ge) of the first channel pattern may be different from a concentration of germanium (Ge) of the second channel pattern
  • the first gate dielectric pattern may include lanthanum (La) or aluminum (Al).
  • a semiconductor device may include a substrate including a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction, a first active pattern and a second active pattern on the PMOSFET region and the NMOSFET region, respectively, the first and second active patterns extending in a second direction intersecting the first direction, the first active pattern having an upper portion including a semiconductor pattern, a device isolation layer on the substrate that extends over a sidewall of a lower portion of each of the first and second active patterns, the first and second active patterns having upper portions protruding upward from a top surface of the device isolation layer, a pair of first source/drain patterns in the upper portion of the first active pattern, a pair of second source/drain patterns in the upper portion of the second active pattern, a gate electrode intersecting the first and second active patterns and extending in the first direction, a gate dielectric pattern between the gate electrode and the first and second active patterns, active contacts electrically connected to the first and second source/drain patterns, and interconnection
  • the semiconductor pattern of the first active pattern may include silicon-germanium (SiGe).
  • the semiconductor pattern of the first active pattern may further include nitrogen (N) as an impurity.
  • a concentration of germanium (Ge) in the semiconductor pattern may increase from a top surface of the semiconductor pattern toward a bottom surface of the semiconductor pattern.
  • a concentration of nitrogen (N) in the semiconductor pattern may decrease from the top surface of the semiconductor pattern toward the bottom surface of the semiconductor pattern.
  • FIG. 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.
  • FIGS. 2 A, 2 B, 2 C and 2 D are cross-sectional views taken along lines A-A′, B-B′, C-C′ and D-D′ of FIG. 1 , respectively.
  • FIG. 3 is an enlarged cross-sectional view of a first active region of FIG. 2 A .
  • FIGS. 4 , 6 , 8 , 10 , 12 , 14 and 16 are plan views illustrating a method for manufacturing a semiconductor device according to some embodiments of the inventive concepts.
  • FIGS. 5 A, 7 A, 9 A, 11 A, 13 A, 15 A and 17 A are cross-sectional views taken along lines A-A′ of FIGS. 4 , 6 , 8 , 10 , 12 , 14 and 16 , respectively.
  • FIGS. 5 B, 7 B, 9 B, 11 B, 13 B, 15 B and 17 B are cross-sectional views taken along lines B-B′ of FIGS. 4 , 6 , 8 , 10 , 12 , 14 and 16 , respectively.
  • FIGS. 15 C and 17 C are cross-sectional views taken along lines C-C′ of FIGS. 14 and 16 , respectively.
  • FIGS. 15 D and 17 D are cross-sectional views taken along lines D-D′ of FIGS. 14 and 16 , respectively.
  • FIGS. 18 and 19 are cross-sectional views taken along the line A-A′ of FIG. 1 to illustrate semiconductor devices according to some embodiments of the inventive concepts.
  • FIGS. 20 A, 20 B and 20 C are cross-sectional views taken along the lines A-A′, C-C′ and D-D′ of FIG. 1 , respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts.
  • FIG. 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.
  • FIGS. 2 A, 2 B, 2 C and 2 D are cross-sectional views taken along lines A-A′, B-B′, C-C′ and D-D′ of FIG. 1 , respectively.
  • FIG. 3 is an enlarged cross-sectional view of a first active region of FIG. 2 A .
  • a substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided.
  • the substrate 100 may be a semiconductor substrate including silicon, germanium, or silicon-germanium or may be a compound semiconductor substrate. In some embodiments, the substrate 100 may be a silicon substrate.
  • the PMOSFET region PR and the NMOSFET region NR may be included in a logic cell region on which logic transistors constituting a logic circuit of a semiconductor device are disposed.
  • the logic transistors constituting the logic circuit may be disposed on the logic cell region of the substrate 100 .
  • Some of the logic transistors may be disposed on the PMOSFET region PR and/or the NMOSFET region NR.
  • the PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR 2 formed in an upper portion of the substrate 100 .
  • the second trench TR 2 may be disposed between the PMOSFET region PR and the NMOSFET region NR.
  • the PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D 1 with the second trench TR 2 interposed therebetween.
  • Each of the PMOSFET region PR and the NMOSFET region NR may extend in a second direction D 2 intersecting the first direction D 1 .
  • the first direction D 1 may be perpendicular to the second direction D 2 .
  • the PMOSFET region PR may include a first active region PR 1 , a second active region PR 2 , and a third active region PR 3 .
  • the first to third active regions PR 1 , PR 2 and PR 3 may be spaced apart from each other in the second direction D 2 .
  • An absolute value of a threshold voltage of a PMOS transistor on the first active region PR 1 may be higher than an absolute value of a threshold voltage of a PMOS transistor on the second active region PR 2 .
  • the absolute value of the threshold voltage of the PMOS transistor on the second active region PR 2 may be higher than an absolute value of a threshold voltage of a PMOS transistor on the third active region PR 3 .
  • First active patterns AP 1 may be provided on the PMOSFET region PR, and second active patterns AP 2 may be provided on the NMOSFET region NR.
  • the first and second active patterns AP 1 and AP 2 may extend in the second direction D 2 .
  • the first and second active patterns AP 1 and AP 2 may be portions of the substrate 100 , which vertically protrude.
  • First trenches TR 1 may be defined between the first active patterns AP 1 adjacent to each other and between the second active patterns AP 2 adjacent to each other.
  • the first trench TR 1 may be shallower than the second trench TR 2 .
  • a device isolation layer ST may fill the first and second trenches TR 1 and TR 2 .
  • the device isolation layer ST may include a silicon oxide layer.
  • Upper portions of the first and second active patterns AP 1 and AP 2 may vertically protrude from the device isolation layer ST (see FIG. 2 C ).
  • Each of the upper portions of the first and second active patterns AP 1 and AP 2 may have a fin shape.
  • the device isolation layer ST may not cover or extend over the upper portions of the first and second active patterns AP 1 and AP 2 .
  • the device isolation layer ST may cover, overlap, or extend over sidewalls of lower portions of the first and second active patterns AP 1 and AP 2 .
  • An upper portion of the first active pattern AP 1 of the first active region PR 1 may include a first semiconductor pattern SP 1 .
  • An upper portion of the first active pattern AP 1 of the second active region PR 2 may include a second semiconductor pattern SP 2 .
  • An upper portion of the first active pattern AP 1 of the third active region PR 3 may include a third semiconductor pattern SP 3 .
  • Each of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may include silicon-germanium (SiGe).
  • Each of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may be used as a first channel pattern CH 1 to be described later.
  • the PMOS transistors according to some embodiments of the inventive concepts may have channels formed of silicon-germanium (SiGe).
  • the first semiconductor pattern SP 1 will be mainly described in detail with reference to FIG. 3 .
  • the first semiconductor pattern SP 1 may further include nitrogen (N) as impurities. Nitrogen (N) may be diffused into the first semiconductor pattern SP 1 in a process of forming the first semiconductor pattern SP 1 .
  • a concentration of nitrogen (N) may gradually decrease from a top surface SP 1 t of the first semiconductor pattern SP 1 to a bottom surface SP 1 b of the first semiconductor pattern SP 1 .
  • a concentration of nitrogen (N) at the top surface SP 1 t of the first semiconductor pattern SP 1 may range from 6 atomic percent (at %) to 8 at %, and a concentration of nitrogen (N) at the bottom surface SP 1 b of the first semiconductor pattern SP 1 may be 1 at %.
  • the concentration of nitrogen (N) may decrease from 7 at % to 1 at % as a distance from the top surface SP 1 t toward the bottom surface SP 1 b increases.
  • a concentration of germanium (Ge) in the first semiconductor pattern SP 1 may gradually increase from the top surface SP 1 t of the first semiconductor pattern SP 1 to the bottom surface SP 1 b of the first semiconductor pattern SP 1 .
  • a concentration of germanium (Ge) at the top surface SP 1 t of the first semiconductor pattern SP 1 may range from 5 at % to 15 at %, and a concentration of germanium (Ge) at the bottom surface SP 1 b of the first semiconductor pattern SP 1 may be about 30 at %.
  • the concentration of germanium (Ge) may increase from 10 at % to 30 at % as a distance from the top surface SP 1 t toward the bottom surface SP 1 b increases.
  • concentrations of nitrogen (N) of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may be different from each other.
  • the concentration of nitrogen (N) may be a concentration measured at the top surface (e.g., SP 1 t of FIG. 3 ) of each of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 .
  • a concentration of nitrogen (N) in the second semiconductor pattern SP 2 may gradually decrease from its top surface to its bottom surface.
  • the concentration of nitrogen (N) at the top surface of the second semiconductor pattern SP 2 may range from 3 at % to 6 at %, and a concentration of nitrogen (N) at the bottom surface of the second semiconductor pattern SP 2 may be 1 at %.
  • a concentration of nitrogen (N) in the third semiconductor pattern SP 3 may gradually decrease from its top surface to its bottom surface.
  • the concentration of nitrogen (N) at the top surface of the third semiconductor pattern SP 3 may range from 0 at % to 4 at %.
  • the third semiconductor pattern SP 3 may not include nitrogen (N).
  • Concentrations of germanium (Ge) of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may be different from each other.
  • the concentration of germanium (Ge) may be a concentration measured at the top surface (e.g., SP 1 t of FIG. 3 ) of each of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 .
  • the concentration of germanium (Ge) of the first semiconductor pattern SP 1 may be lower than the concentration of germanium (Ge) of the second semiconductor pattern SP 2 .
  • the concentration of germanium (Ge) of the second semiconductor pattern SP 2 may be lower than the concentration of germanium (Ge) of the third semiconductor pattern SP 3 .
  • the concentration of germanium (Ge) of the first semiconductor pattern SP 1 may range from 5 at % to 15 at %.
  • the concentration of germanium (Ge) of the second semiconductor pattern SP 2 may range from 10 at % to 20 at %.
  • the concentration of germanium (Ge) of the third semiconductor pattern SP 3 may range from 20 at % to 30 at %.
  • the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may be provided in the upper portion of the first active pattern AP 1 .
  • the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may not be provided in an upper portion of the second active pattern AP 2 .
  • the upper portion of the second active pattern AP 2 may include silicon (Si).
  • First source/drain patterns SD 1 may be provided in the upper portion of the first active pattern AP 1 .
  • the first source/drain patterns SD 1 may be dopant regions having a first conductivity type (e.g., a P-type).
  • a first channel pattern CH 1 may be disposed between a pair of the first source/drain patterns SD 1 .
  • the bottom surface of each of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may be lower than a bottom surface of each of the first source/drain patterns SD 1 .
  • the first source/drain patterns SD 1 may be merged together.
  • Second source/drain patterns SD 2 may be provided in the upper portions of the second active patterns AP 2 .
  • the second source/drain patterns SD 2 may be dopant regions having a second conductivity type (e.g., an N-type).
  • a second channel pattern CH 2 may be disposed between a pair of the second source/drain patterns SD 2 .
  • the second source/drain patterns SD 2 may be merged together.
  • the first and second source/drain patterns SD 1 and SD 2 may include epitaxial patterns formed by a selective epitaxial growth (SEG) process.
  • a top surface of each of the first and second source/drain patterns SD 1 and SD 2 may be disposed at substantially the same level as a top surface of each of the first and second channel patterns CH 1 and CH 2 .
  • the first source/drain patterns SD 1 may include a semiconductor element (e.g., SiGe) of which a lattice constant is greater than that of a semiconductor element of the substrate 100 .
  • the first source/drain patterns SD 1 may provide compressive stress to the first channel patterns CH 1 .
  • the second source/drain patterns SD 2 may include the same semiconductor element (e.g., silicon) as the substrate 100 .
  • Gate electrodes GE may extend in the first direction D 1 to intersect the first and second active patterns AP 1 and AP 2 .
  • the gate electrodes GE may be spaced apart from each other in the second direction D 2 .
  • the gate electrodes GE may vertically overlap with the first and second channel patterns CH 1 and CH 2 in the third direction D 3 .
  • the gate electrode GE may be provided on a first top surface TS 1 of the first channel pattern CH 1 and at least one first sidewall SW 1 of the first channel pattern CH 1 .
  • the gate electrode GE may be provided on a second top surface TS 2 of the second channel pattern CH 2 and at least one second sidewall SW 2 of the second channel pattern CH 2 .
  • the transistors according to some embodiments may be three-dimensional (3D) field effect transistors (e.g., FinFETs) in which the gate electrode GE three-dimensionally surrounds channels CH 1 and CH 2 .
  • a pair of gate spacers GS may be disposed on both sidewalls of each of the gate electrodes GE, respectively.
  • the gate spacers GS may extend along the gate electrodes GE in the first direction D 1 .
  • Top surfaces of the gate spacers GS may be higher than top surfaces of the gate electrodes GE.
  • the top surfaces of the gate spacers GS may be coplanar with a top surface of a first interlayer insulating layer 110 to be described later.
  • the gate spacers GS may include at least one of SiCN, SiCON, or SiN.
  • each of the gate spacers GS may have a multi-layered structure formed of at least two of SiCN, SiCON, or SiN.
  • a gate capping pattern GP may be provided on each of the gate electrodes GE.
  • the gate capping pattern GP may extend along the gate electrode GE in the first direction D 1 .
  • the gate capping patterns GP may include a material having an etch selectivity with respect to first and second interlayer insulating layers 110 and 120 to be described later.
  • the gate capping patterns GP may include at least one of SiON, SiCN, SiCON, or SiN.
  • a gate dielectric pattern GI may be disposed between the gate electrode GE and the first active pattern AP 1 and between the gate electrode GE and the second active pattern AP 2 .
  • the gate dielectric pattern GI may extend along a bottom surface of the gate electrode GE thereon.
  • the gate dielectric pattern GI may cover the top surface and both sidewalls of the first channel pattern CH 1 .
  • the gate dielectric pattern GI may cover the top surface and both sidewalls of the second channel pattern CH 2 .
  • the gate dielectric pattern GI may cover a top surface of the device isolation layer ST under the gate electrode GE (see FIG. 2 C ).
  • the gate dielectric pattern GI may include a high-k dielectric material of which a dielectric constant is higher than that of silicon oxide.
  • the high-k dielectric material may include at least one of hafnium oxide, hafnium-silicon oxide, hafnium-zirconium oxide, hafnium-tantalum oxide, lanthanum oxide, zirconium oxide, zirconium-silicon oxide, tantalum oxide, titanium oxide, barium-strontium-titanium oxide, barium-titanium oxide, strontium-titanium oxide, lithium oxide, aluminum oxide, lead-scandium-tantalum oxide, or lead-zinc niobate.
  • the gate dielectric pattern GI may include a ferroelectric material.
  • the gate dielectric pattern GI including the ferroelectric material may function as a negative capacitor. Negative capacitance occurs when a change in charge causes the net voltage across a material to change in the opposite direction. In other words, a decrease in voltage leads to an increase in charge.
  • a negative capacitance effect by a phase change from an initial polarity state to another state may be generated by movement of dipoles in the ferroelectric material.
  • a total capacitance of the transistor including the ferroelectric material in the embodiments may be increased, and thus a sub-threshold swing characteristic of the transistor may be improved and an operating voltage of the transistor may be reduced.
  • the ferroelectric material of the gate dielectric pattern GI may include hafnium oxide doped with (or containing) at least one of zirconium (Zr), silicon (Si), aluminum (Al), or lanthanum (La). Since hafnium oxide is doped with at least one of zirconium (Zr), silicon (Si), aluminum (Al), or lanthanum (La) at a predetermined ratio, at least a portion of the ferroelectric material may have an orthorhombic crystal structure. When at least a portion of the ferroelectric material has the orthorhombic crystal structure, the negative capacitance effect may be generated.
  • a volume ratio of a portion having the orthorhombic crystal structure in the ferroelectric material may range from 10% to 50%.
  • the ferroelectric material includes zirconium-doped hafnium oxide (ZrHfO)
  • ZrHfO zirconium-doped hafnium oxide
  • a ratio of Zr atoms to a sum of Zr atoms and Hf atoms (Zr/(Hf+Zr)) may range from 45 at % to 55 at %.
  • the ferroelectric material includes silicon-doped hafnium oxide (SiHfO)
  • Si/(Hf+Si) silicon-doped hafnium oxide
  • the ferroelectric material includes aluminum-doped hafnium oxide (AlHfO)
  • AlHfO aluminum-doped hafnium oxide
  • a ratio of Al atoms to a sum of Al atoms and Hf atoms may range from 5 at % to 10 at %.
  • the ferroelectric material includes lanthanum-doped hafnium oxide (LaHfO)
  • La/(Hf+La) may range from 5 at % to 10 at %.
  • Each of the gate electrodes GE may include a first metal pattern WF 1 , a second metal pattern WF 2 , and an electrode pattern EL.
  • the first metal pattern WF 1 may be provided on the gate dielectric pattern GI.
  • the gate dielectric pattern GI may be disposed between the first metal pattern WF 1 and the first channel pattern CH 1 .
  • the gate dielectric pattern GI and the first metal pattern WF 1 may be chamfered (i.e., cut away at a right-angled edge or corner to make a symmetrical sloping edge), and thus upper portions thereof may be lower than the topmost surface GEt of the gate electrode GE.
  • the first metal pattern WF 1 may have a recessed top surface RSt, and the recessed top surface RSt may be lower than the topmost surface GEt of the gate electrode GE.
  • the first metal pattern WF 1 may include a metal nitride having a relatively high work function.
  • the work function is the minimum amount of energy required to make the free electrons escape from the metal surface. If a material has a high work function, then a high amount of energy may be needed to make electrons escape from the metal surface.
  • the first metal pattern WF 1 may include a P-type work function metal.
  • the first metal pattern WF 1 may include titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium-silicon nitride (TiSiN), titanium-aluminum nitride (TiAlN), tungsten carbonitride (WCN), and/or molybdenum nitride (MoN).
  • TiN titanium nitride
  • TaN tantalum nitride
  • TiON titanium oxynitride
  • TiSiN titanium-silicon nitride
  • TiAlN titanium-aluminum nitride
  • WCN tungsten carbonitride
  • MoN molybdenum nitride
  • the second metal pattern WF 2 may be provided on the first metal pattern WF 1 .
  • the second metal pattern WF 2 may cover or extend over the recessed top surface RSt of the first metal pattern WF 1 .
  • the second metal pattern WF 2 may include a metal carbide having a relatively low work function. In other words, the second metal pattern WF 2 may include an N-type work function metal.
  • the second metal pattern WF 2 may include a metal carbide doped with (or containing) silicon and/or aluminum.
  • the second metal pattern WF 2 may include aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), and/or silicon-doped tantalum carbide (TaSiC).
  • the second metal pattern WF 2 may include titanium carbide doped with aluminum and silicon (TiAlSiC), or tantalum carbide doped with aluminum and silicon (TaAlSiC).
  • the second metal pattern WF 2 may include aluminum-doped titanium (TiAl).
  • the work function of the second metal pattern WF 2 may be adjusted by adjusting a doping concentration of silicon or aluminum corresponding to a dopant.
  • a concentration of the dopant (e.g., silicon or aluminum) in the second metal pattern WF 2 may range from 0.1 at % to 25 at %.
  • the electrode pattern EL may be provided on the second metal pattern WF 2 .
  • a resistance of the electrode pattern EL may be lower than respective resistances of the first and second metal patterns WF 1 and WF 2 .
  • the electrode pattern EL may include a low-resistance metal including at least one of aluminum (Al), tungsten (W), titanium (Ti), or tantalum (Ta).
  • the first and second metal patterns WF 1 and WF 2 may be adjacent to the first channel pattern CH 1 .
  • the first and second metal patterns WF 1 and WF 2 may function as a work function metal for adjusting the threshold voltage of the PMOS transistor.
  • a desired threshold voltage may be obtained by adjusting a thickness and/or a composition of each of the first and second metal patterns WF 1 and WF 2 .
  • a thickness of the first metal pattern WF 1 on the second active region PR 2 may be greater than a thickness of the first metal pattern WF 1 on the first active region PR 1 .
  • a thickness of the first metal pattern WF 1 on the third active region PR 3 may be greater than the thickness of the first metal pattern WF 1 on the second active region PR 2 .
  • the thickness of the first metal pattern WF 1 may be a width, in the second direction D 2 , of an upper portion of the first metal pattern WF 1 adjacent to the gate spacer GS.
  • the thicknesses of the first metal patterns WF 1 may sequentially increase from the first active region PR 1 to the third active region PR 3 .
  • effective work functions (eWF) of the gate electrodes GE may sequentially increase from the first active region PR 1 to the third active region PR 3 .
  • the absolute values of the threshold voltages of the PMOS transistors may sequentially decrease from the first active region PR 1 to the third active region PR 3 .
  • the effective work functions of the gate electrodes GE may also be adjusted by the concentrations of germanium (Ge) of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 .
  • the effective work function of the gate electrode GE may increase as the concentration of germanium (Ge) of the semiconductor pattern SP 1 , SP 2 or SP 3 increases. Since the concentrations of germanium (Ge) of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 increase in the order listed, the effective work functions of the gate electrodes GE may sequentially increase from the first active region PR 1 to the third active region PR 3 .
  • the absolute values of the threshold voltages of the PMOS transistors may sequentially decrease from the first active region PR 1 to the third active region PR 3 .
  • the concentration of germanium (Ge) of the third semiconductor pattern SP 3 of the third active region PR 3 may be greater than the concentration of germanium (Ge) of the first semiconductor pattern SP 1 of the first active region PR 1 .
  • the thickness of the first metal pattern WF 1 on the third active region PR 3 may be greater than the thickness of the first metal pattern WF 1 on the first active region PR 1 .
  • the effective work function of the gate electrode GE on the third active region PR 3 may be relatively increased by interaction of the thickness of the first metal pattern WF 1 on the third active region PR 3 and the concentration of germanium (Ge) of the third semiconductor pattern SP 3 .
  • the effective work function of the gate electrode GE on the first active region PR 1 may be relatively decreased by interaction of the thickness of the first metal pattern WF 1 on the first active region PR 1 and the concentration of germanium (Ge) of the first semiconductor pattern SP 1 .
  • the absolute value of the threshold voltage of the PMOS transistor on the third active region PR 3 may be much lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR 1 .
  • a first interlayer insulating layer 110 may be provided on the substrate 100 .
  • the first interlayer insulating layer 110 may cover or extend over the gate spacers GS and the first and second source/drain patterns SD 1 and SD 2 .
  • a top surface of the first interlayer insulating layer 110 may be substantially coplanar with top surfaces of the gate capping patterns GP and top surfaces of the gate spacers GS.
  • a second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 and the gate capping patterns GP.
  • each of the first and second interlayer insulating layers 110 and 120 may include a silicon oxide layer.
  • Active contacts AC may penetrate the second and first interlayer insulating layers 120 and 110 so as to be electrically connected to the first and second source/drain patterns SD 1 and SD 2 .
  • Each of the active contacts AC may be provided between a pair of the gate electrodes GE.
  • the active contact AC may be a self-aligned contact.
  • the active contact AC may be formed to be self-aligned using the gate capping pattern GP and the gate spacer GS.
  • the active contact AC may cover, overlap, or extend over at least a portion of a sidewall of the gate spacer GS. Even though not shown in the drawings, the active contact AC may cover or extend over a portion of the top surface of the gate capping pattern GP.
  • Silicide patterns SC may be disposed between the active contact AC and the first source/drain pattern SD 1 and between the active contact AC and the second source/drain pattern SD 2 , respectively.
  • the active contact AC may be electrically connected to the source/drain pattern SD 1 or SD 2 through the silicide pattern SC.
  • the silicide pattern SC may include a metal silicide and may include at least one of, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or a cobalt silicide.
  • the active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM.
  • the conductive pattern FM may include at least one metal of aluminum, copper, tungsten, molybdenum, or cobalt.
  • the barrier pattern BM may cover a bottom surface and sidewalls of the conductive pattern FM.
  • the barrier pattern BM may include a metal layer/a metal nitride layer.
  • the metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum.
  • the metal nitride layer may include at least one of a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, or a platinum nitride (PtN) layer.
  • TiN titanium nitride
  • TaN tantalum nitride
  • WN tungsten nitride
  • NiN nickel nitride
  • CoN cobalt nitride
  • PtN platinum nitride
  • a third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120 .
  • a first metal layer may be provided in the third interlayer insulating layer 130 .
  • the first metal layer may include first interconnection lines M 1 , first vias V 1 , and second vias V 2 .
  • the first and second vias V 1 and V 2 may be provided under the first interconnection lines M 1 .
  • the first interconnection lines M 1 may extend in the second direction D 2 in parallel to each other.
  • the first interconnection lines M 1 may be arranged in the first direction D 1 .
  • the first via V 1 may be disposed between the active contact AC and a corresponding one of the first interconnection lines M 1 to electrically connect the active contact AC to the corresponding one of the first interconnection lines M 1 .
  • the second via V 2 may be disposed between the gate electrode GE and a corresponding one of the first interconnection lines M 1 to electrically connect the gate electrode GE to the corresponding one of the first interconnection lines M 1 .
  • first interconnection line M 1 and the first or second via V 1 or V 2 disposed thereunder may be connected to each other to constitute a single unitary conductive structure.
  • first interconnection line M 1 and the first or second via V 1 or V 2 may be formed together.
  • the first interconnection line M 1 and the first or second via V 1 or V 2 may be formed as the single unitary conductive structure by using a dual damascene process.
  • stacked metal layers may be additionally disposed on the third interlayer insulating layer 130 .
  • FIGS. 4 , 6 , 8 , 10 , 12 , 14 and 16 are plan views illustrating a method for manufacturing a semiconductor device according to some embodiments of the inventive concepts.
  • FIGS. 5 A, 7 A, 9 A, 11 A, 13 A, 15 A and 17 A are cross-sectional views taken along lines A-A′ of FIGS. 4 , 6 , 8 , 10 , 12 , 14 and 16 , respectively.
  • FIGS. 5 B, 7 B, 9 B, 11 B, 13 B, 15 B and 17 B are cross-sectional views taken along lines B-B′ of FIGS. 4 , 6 , 8 , 10 , 12 , 14 and 16 , respectively.
  • FIGS. 15 C and 17 C are cross-sectional views taken along lines C-C′ of FIGS. 14 and 16 , respectively.
  • FIGS. 15 D and 17 D are cross-sectional views taken along lines D-D′ of FIGS. 14 and 16 , respectively.
  • a substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided.
  • a semiconductor layer SL may be formed on the PMOSFET region PR of the substrate 100 .
  • the formation of the semiconductor layer SL may include forming a trench on the PMOSFET region PR of the substrate 100 , and performing a selective epitaxial growth (SEG) process on the PMOSFET region PR to form the semiconductor layer SL filling the trench.
  • SEG selective epitaxial growth
  • the semiconductor layer SL may include silicon-germanium (SiGe).
  • a concentration of germanium (Ge) of the semiconductor layer SL may range from 20 at % to 30 at %.
  • a first mask layer ML 1 may be formed on the NMOSFET region NR and a third active region PR 3 of the PMOSFET region PR.
  • the first mask layer ML 1 may expose first and second active regions PR 1 and PR 2 of the PMOSFET region PR.
  • a first plasma treatment PA 1 may be performed on the first and second active regions PR 1 and PR 2 exposed by the first mask layer ML 1 .
  • the first plasma treatment PA 1 may include an annealing process using hydrogen plasma.
  • the hydrogen plasma may be provided onto the semiconductor layer SL on the first and second active regions PR 1 and PR 2 , i.e., onto the exposed semiconductor layer SL.
  • a natural oxide layer e.g., a germanium oxide (GeO) layer
  • germanium (Ge) of an exposed surface of the semiconductor layer SL may be selectively removed during the first plasma treatment PM.
  • a silicon-rich layer may be formed on the exposed surface of the semiconductor layer SL by the removal of germanium (Ge) of the exposed surface of the semiconductor layer SL.
  • a concentration of germanium (Ge) of the semiconductor layer SL on the first and second active regions PR 1 and PR 2 may be reduced as compared with the concentration of germanium (Ge) of the semiconductor layer SL on the third active region PR 3 .
  • the concentration of germanium (Ge) of the exposed surface of the semiconductor layer SL may be reduced by about 5 at % during the first plasma treatment PM.
  • Germanium (Ge) in the exposed semiconductor layer SL may have a concentration gradient by the first plasma treatment PA 1 (see FIG. 3 ).
  • Nitrogen (N) may be diffused into the exposed semiconductor layer SL in the first plasma treatment PA 1 .
  • Nitrogen (N) may be generated from a coating material inside an apparatus for performing the first plasma treatment PM. Since nitrogen (N) is diffused into the exposed semiconductor layer SL, nitrogen (N) in the exposed semiconductor layer SL may have a concentration gradient (see FIG. 3 ).
  • the first mask layer ML 1 may be removed.
  • a second mask layer ML 2 may be formed on the NMOSFET region NR and the second and third active regions PR 2 and PR 3 of the PMOSFET region PR.
  • the second mask layer ML 2 may expose the first active region PR 1 of the PMOSFET region PR.
  • a second plasma treatment PA 2 may be performed on the first active region PR 1 exposed by the second mask layer ML 2 .
  • the second plasma treatment PA 2 may include an annealing process using hydrogen plasma.
  • the second plasma treatment PA 2 may be substantially the same as the first plasma treatment PA 1 described above.
  • a concentration of germanium (Ge) of the semiconductor layer SL on the first active region PR 1 may be reduced as compared with the concentration of germanium (Ge) of the semiconductor layer SL on the second active region PR 2 .
  • the concentration of germanium (Ge) of the exposed surface of the semiconductor layer SL may be reduced by about 5 at % during the second plasma treatment PA 2 .
  • the semiconductor layer SL of the first active region PR 1 on which the first and second plasma treatments PA 1 and PA 2 are performed, may have the lowest germanium concentration.
  • the semiconductor layer SL of the third active region PR 3 on which the first and second plasma treatments PA 1 and PA 2 are not performed, may have the highest germanium concentration.
  • the second mask layer ML 2 may be removed.
  • the substrate 100 may be patterned to form first and second active patterns AP 1 and AP 2 .
  • the first active patterns AP 1 may be formed on the PMOSFET region PR, and the second active patterns AP 2 may be formed on the NMOSFET region NR.
  • First trenches TR 1 may be formed between the first active patterns AP 1 and between the second active patterns AP 2 .
  • the formation of the first active patterns AP 1 may include patterning the semiconductor layer SL to form first to third semiconductor patterns SP 1 , SP 2 and SP 3 on the first to third active regions PR 1 , PR 2 and PR 3 , respectively.
  • an upper portion of the first active pattern AP 1 of the first active region PR 1 may include the first semiconductor pattern SP 1 .
  • An upper portion of the first active pattern AP 1 of the second active region PR 2 may include the second semiconductor pattern SP 2 .
  • An upper portion of the first active pattern AP 1 of the third active region PR 3 may include the third semiconductor pattern SP 3 .
  • the substrate 100 may be patterned to form a second trench TR 2 between the PMOSFET region PR and the NMOSFET region NR.
  • the second trench TR 2 may be deeper than the first trench TR 1 .
  • a device isolation layer ST may be formed on the substrate 100 to fill the first and second trenches TR 1 and TR 2 .
  • the device isolation layer ST may include an insulating material such as a silicon oxide layer.
  • the device isolation layer ST may be recessed until upper portions of the first and second active patterns AP 1 and AP 2 are exposed. Thus, the upper portions of the first and second active patterns AP 1 and AP 2 may vertically protrude from the device isolation layer ST.
  • the first to third semiconductor patterns SP 1 , SP 2 and SP 3 of the first active pattern AP 1 may vertically protrude from the device isolation layer ST.
  • sacrificial patterns PP may be formed to intersect the first and second active patterns AP 1 and AP 2 .
  • the sacrificial patterns PP may have line shapes or bar shapes, which extend in the first direction D 1 .
  • the formation of the sacrificial patterns PP may include forming a sacrificial layer on an entire top surface of the substrate 100 , forming hard mask patterns MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask patterns MA as etch masks.
  • the sacrificial layer may include poly-silicon.
  • a pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns PP, respectively.
  • the formation of the gate spacers GS may include conformally forming a gate spacer layer on an entire top surface of the substrate 100 and anisotropically etching the gate spacer layer.
  • the gate spacer layer may include at least one of SiCN, SiCON, or SiN.
  • the gate spacer layer may be formed of a multi-layer including at least two of SiCN, SiCON, or SiN.
  • first source/drain patterns SD 1 may be formed in an upper portion of the first active pattern AP 1 .
  • a pair of the first source/drain patterns SD 1 may be formed at both sides of each of the sacrificial patterns PP.
  • the upper portion of the first active pattern AP 1 may be etched using the hard mask patterns MA and the gate spacers GS as etch masks to form first recess regions.
  • the device isolation layer ST between the first active patterns AP 1 may be recessed while the upper portions of the first active patterns AP 1 are etched.
  • the first source/drain patterns SD 1 may be formed by performing a selective epitaxial growth (SEG) process using inner surfaces of the first recess regions of the first active patterns AP 1 as a seed layer. Since the first source/drain patterns SD 1 are formed, a first channel pattern CH 1 may be defined between the pair of first source/drain patterns SD 1 .
  • the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.
  • the first source/drain patterns SD 1 may include a semiconductor element (e.g., SiGe) of which a lattice constant is greater than that of a semiconductor element of the substrate 100 .
  • each of the first source/drain patterns SD 1 may be formed of a plurality of stacked semiconductor layers.
  • dopants may be injected in-situ into the first source/drain patterns SD 1 during the SEG process for forming the first source/drain patterns SD 1 .
  • the dopants may be injected or implanted into the first source/drain patterns SD 1 after the SEG process for forming the first source/drain patterns SD 1 .
  • the first source/drain patterns SD 1 may be doped with the dopants to have a first conductivity type (e.g., a P-type).
  • Second source/drain patterns SD 2 may be formed in an upper portion of the second active pattern AP 2 .
  • a pair of the second source/drain patterns SD 2 may be formed at both sides of each of the sacrificial patterns PP.
  • the upper portion of the second active pattern AP 2 may be etched using the hard mask patterns MA and the gate spacers GS as etch masks to form second recess regions.
  • the second source/drain patterns SD 2 may be formed by performing a SEG process using inner surfaces of the second recess regions of the second active pattern AP 2 as a seed layer. Since the second source/drain patterns SD 2 are formed, a second channel pattern CH 2 may be defined between the pair of second source/drain patterns SD 2 .
  • the second source/drain patterns SD 2 may include the same semiconductor element (e.g., silicon) as the substrate 100 .
  • the second source/drain patterns SD 2 may be doped with dopants to have a second conductivity type (e.g., an N-type).
  • the first source/drain patterns SD 1 and the second source/drain patterns SD 2 may be sequentially formed by different processes from each other. In other words, the first source/drain patterns SD 1 may not be formed simultaneously with the second source/drain patterns SD 2 .
  • a first interlayer insulating layer 110 may be formed to cover, overlap, or extend over the first and second source/drain patterns SD 1 and SD 2 , the hard mask patterns MA, and the gate spacers GS.
  • the first interlayer insulating layer 110 may include a silicon oxide layer.
  • the first interlayer insulating layer 110 may be planarized until top surfaces of the sacrificial patterns PP are exposed.
  • the planarization process of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the hard mask patterns MA may be completely removed during the planarization process.
  • a top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surfaces of the sacrificial patterns PP and top surfaces of the gate spacers GS.
  • the sacrificial patterns PP may be replaced with gate electrodes GE, respectively.
  • the exposed sacrificial patterns PP may be selectively removed.
  • Empty spaces may be formed by the removal of the sacrificial patterns PP.
  • a gate dielectric pattern GI, a gate electrode GE and a gate capping pattern GP may be formed in each of the empty spaces.
  • the gate electrode GE may include a first metal pattern WF 1 , a second metal pattern WF 2 , and an electrode pattern EL.
  • the first metal pattern WF 1 on the second active region PR 2 may be formed to be thicker than the first metal pattern WF 1 on the first active region PR 1 .
  • the first metal pattern WF 1 on the third active region PR 3 may be formed to be thicker than the first metal pattern WF 1 on the second active region PR 2 .
  • a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 .
  • the second interlayer insulating layer 120 may include a silicon oxide layer.
  • Active contacts AC may be formed in the second and first interlayer insulating layers 120 and 110 .
  • the active contacts AC may penetrate the second and first interlayer insulating layers 120 and 110 so as to be electrically connected to the first and second source/drain patterns SD 1 and SD 2 .
  • a third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120 .
  • a first metal layer may be formed in the third interlayer insulating layer 130 .
  • the first metal layer may include first interconnection lines M 1 , first vias V 1 , and second vias V 2 .
  • FIGS. 18 and 19 are cross-sectional views taken along the line A-A′ of FIG. 1 to illustrate semiconductor devices according to some embodiments of the inventive concepts.
  • the descriptions to the same technical features as in the embodiments of FIGS. 1 and 2 A to 2 D will be omitted for the purpose of ease and convenience in explanation.
  • differences between the present embodiments and the embodiments of FIGS. 1 and 2 A to 2 D will be mainly described hereinafter.
  • first to third gate dielectric patterns GI 1 , GI 2 and GI 3 may be provided on the first to third active regions PR 1 , PR 2 and PR 3 , respectively.
  • the first gate dielectric pattern GI 1 may be disposed between the gate electrode GE and the first semiconductor pattern SP 1 .
  • the second gate dielectric pattern GI 2 may be disposed between the gate electrode GE and the second semiconductor pattern SP 2 .
  • the third gate dielectric pattern GI 3 may be disposed between the gate electrode GE and the third semiconductor pattern SP 3 . Thicknesses of first metal patterns WF 1 on the first to third active regions PR 1 , PR 2 and PR 3 may be equal to each other.
  • the first gate dielectric pattern GI 1 may include a first dipole.
  • the first dipole may include lanthanum (La).
  • the first gate dielectric pattern GI 1 may include hafnium oxide containing lanthanum (La).
  • the hafnium oxide containing lanthanum (La) in the first gate dielectric pattern GI 1 may reduce an effective work function of the gate electrode GE.
  • the formation of the first gate dielectric pattern GI 1 may include forming a first dipole layer including lanthanum oxide on the first gate dielectric pattern GI 1 , and performing an annealing process on the first dipole layer to diffuse lanthanum into the first gate dielectric pattern GI 1 .
  • a first dipole-interface may be formed in the first gate dielectric pattern GI 1 .
  • the third gate dielectric pattern GI 3 may include a second dipole.
  • the second dipole may include aluminum (Al).
  • the third gate dielectric pattern GI 3 may include hafnium oxide containing aluminum (Al).
  • the hafnium oxide containing aluminum (Al) in the third gate dielectric pattern GI 3 may increase an effective work function of the gate electrode GE.
  • the formation of the third gate dielectric pattern GI 3 may include forming a second dipole layer including aluminum oxide on the third gate dielectric pattern GI 3 , and performing an annealing process on the second dipole layer to diffuse aluminum into the third gate dielectric pattern GI 3 .
  • a second dipole-interface may be formed in the third gate dielectric pattern GI 3 .
  • the second gate dielectric pattern GI 2 may not include a dipole. In other words, the second gate dielectric pattern GI 2 may include hafnium oxide.
  • the second gate dielectric pattern GI 2 may be substantially the same as the gate dielectric pattern GI described above with reference to FIGS. 1 and 2 A to 2 D .
  • the effective work function of the gate electrode GE on the third active region PR 3 may be relatively increased by interaction of the third gate dielectric pattern GI 3 on the third active region PR 3 and the concentration of germanium (Ge) of the third semiconductor pattern SP 3 .
  • the effective work function of the gate electrode GE on the first active region PR 1 may be relatively decreased by interaction of the first gate dielectric pattern GI 1 on the first active region PR 1 and the concentration of germanium (Ge) of the first semiconductor pattern SP 1 .
  • the absolute value of the threshold voltage of the PMOS transistor on the third active region PR 3 may be much lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR 1 .
  • thicknesses of first metal patterns WF 1 on the first to third active regions PR 1 , PR 2 and PR 3 may be equal to each other. However, materials of the first metal patterns WF 1 on the first to third active regions PR 1 , PR 2 and PR 3 may be different from each other.
  • the first metal pattern WF 1 on the first active region PR 1 may include a first work function metal W 1 .
  • the first work function metal W 1 may be a metal having a relatively low work function.
  • the first work function metal W 1 may include titanium-aluminum nitride (TiAlN), titanium-silicon nitride (TiSiN), and/or tantalum nitride (TaN).
  • the first metal pattern WF 1 on the second active region PR 2 may include a second work function metal W 2 .
  • the second work function metal W 2 may include titanium nitride (TiN).
  • the first metal pattern WF 1 on the third active region PR 3 may include a third work function metal W 3 .
  • the third work function metal W 3 may be a metal having a relatively high work function.
  • the third work function metal W 3 may include titanium oxynitride (TiON), tungsten carbonitride (WCN), or molybdenum nitride (MoN).
  • the effective work function of the gate electrode GE on the third active region PR 3 may be relatively increased by interaction of the third work function metal W 3 on the third active region PR 3 and the concentration of germanium (Ge) of the third semiconductor pattern SP 3 .
  • the effective work function of the gate electrode GE on the first active region PR 1 may be relatively decreased by interaction of the first work function metal W 1 on the first active region PR 1 and the concentration of germanium (Ge) of the first semiconductor pattern SP 1 .
  • the absolute value of the threshold voltage of the PMOS transistor on the third active region PR 3 may be much lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR 1 .
  • FIGS. 20 A, 20 B and 20 C are cross-sectional views taken along the lines A-A′, C-C′ and D-D′ of FIG. 1 , respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts.
  • the descriptions to the same technical features as in the embodiments of FIGS. 1 , 2 A to 2 D and 18 will be omitted for the purpose of ease and convenience in explanation.
  • differences between the present embodiment and the embodiments of FIGS. 1 , 2 A to 2 D and 18 will be mainly described hereinafter.
  • a substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided.
  • a device isolation layer ST may be provided on the substrate 100 .
  • the device isolation layer ST may define a first active pattern AP 1 and a second active pattern AP 2 on the substrate 100 .
  • the first active pattern AP 1 and the second active pattern AP 2 may be defined on the PMOSFET region PR and the NMOSFET region NR, respectively.
  • An upper portion of the first active pattern AP 1 may include first to third semiconductor patterns SP 1 , SP 2 and SP 3 .
  • the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may be provided on first to third active regions PR 1 , PR 2 and PR 3 of the PMOSFET region PR, respectively.
  • Each of the first to third semiconductor patterns SP 1 , SP 2 and SP 3 may include first channel patterns CH 1 which are vertically stacked.
  • the stacked first channel patterns CH 1 may be spaced apart from each other in a third direction D 3 .
  • the stacked first channel patterns CH 1 may vertically overlap with each other.
  • the second active pattern AP 2 may include second channel patterns CH 2 which are vertically stacked.
  • the stacked second channel patterns CH 2 may be spaced apart from each other in the third direction D 3 .
  • the stacked second channel patterns CH 2 may vertically overlap with each other.
  • the first and second channel patterns CH 1 and CH 2 may include at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).
  • the first active pattern AP 1 may further include first source/drain patterns SD 1 .
  • the stacked first channel patterns CH 1 may be disposed between a pair of the first source/drain patterns SD 1 adjacent to each other.
  • the stacked first channel patterns CH 1 may connect the pair of first source/drain patterns SD 1 adjacent to each other.
  • the second active pattern AP 2 may further include second source/drain patterns SD 2 .
  • the stacked second channel patterns CH 2 may be disposed between a pair of the second source/drain patterns SD 2 adjacent to each other.
  • the stacked second channel patterns CH 2 may connect the pair of second source/drain patterns SD 2 adjacent to each other.
  • Gate electrodes GE may extend in the first direction D 1 to intersect the first and second channel patterns CH 1 and CH 2 .
  • the gate electrodes GE may vertically overlap with the first and second channel patterns CH 1 and CH 2 .
  • a pair of gate spacers GS may be disposed on both sidewalls of each of the gate electrodes GE, respectively.
  • a gate capping pattern GP may be provided on each of the gate electrodes GE.
  • the gate electrode GE may surround each of the first and second channel patterns CH 1 and CH 2 (see FIG. 20 B ) in the first direction D 1 and/or the third direction D 3 .
  • the gate electrode GE may be provided on a first top surface TS 1 , at least one first sidewall SW 1 and a first bottom surface BS 1 of the first channel pattern CH 1 .
  • the gate electrode GE may be provided on a second top surface TS 2 , at least one second sidewall SW 2 and a second bottom surface BS 2 of the second channel pattern CH 2 .
  • the gate electrode GE may surround the top surface, the bottom surface and both sidewalls of each of the first and second channel patterns CH 1 and CH 2 .
  • Transistors may be 3D field effect transistors (e.g., MBCFETs) in which the gate electrode GE three-dimensionally surrounds the channel patterns CH 1 and CH 2 .
  • a first gate dielectric pattern GI 1 may be provided between the gate electrode GE and the first channel pattern CH 1 on the first active region PR 1 .
  • a second gate dielectric pattern GI 2 may be provided between the gate electrode GE and the first channel pattern CH 1 on the second active region PR 2 .
  • a third gate dielectric pattern GI 3 may be provided between the gate electrode GE and the first channel pattern CH 1 on the third active region PR 3 .
  • the first to third gate dielectric patterns GI 1 , GI 2 and GI 3 may be substantially the same as described above with reference to FIG. 18 .
  • a first interlayer insulating layer 110 and a second interlayer insulating layer 120 may be provided on an entire top surface of the substrate 100 . Active contacts AC may penetrate the second and first interlayer insulating layers 120 and 110 so as to be connected to the first and second source/drain patterns SD 1 and SD 2 .
  • a third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120 .
  • a first metal layer may be provided in the third interlayer insulating layer 130 .
  • the first metal layer may include first interconnection lines M 1 , first vias V 1 , and second vias V 2 .
  • the threshold voltage of the transistor may be adjusted using the interaction of the thickness of the first metal pattern including the P-type work function metal and the concentration of germanium (Ge) of the channel. According to some embodiments of the inventive concepts, a sufficient difference value between the threshold voltages of the transistors may be obtained. According to some embodiments of the inventive concepts, the threshold voltage of the transistor may be adjusted by controlling the impurity of the gate dielectric pattern and/or a kind of the metal of the first metal pattern.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This U.S. non-provisional patent application is a continuation of U.S. patent application Ser. No. 16/840,880, filed Apr. 6, 2020, which itself claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0114081, filed on Sep. 17, 2019, in the Korean Intellectual Property Office, the disclosures of both of which are hereby incorporated by reference in its entirety.
BACKGROUND
Embodiments of the inventive concepts relate to a semiconductor device and, more particularly, to a semiconductor device including a field effect transistor and a method for manufacturing the same.
Semiconductor devices may include integrated circuits including metal-oxide-semiconductor field effect transistors (MOSFETs). As sizes and design rules of semiconductor devices have been reduced, MOSFETs have been scaled down. Operating characteristics of semiconductor devices may be deteriorated by reduction in size of MOSFETs. Accordingly, various methods for forming semiconductor devices which have excellent performance while overcoming limitations by the high integration have been studied.
SUMMARY
Embodiments of the inventive concepts may provide a semiconductor device with improved electrical characteristics.
In some embodiments, a semiconductor device may include a substrate including a first active region and a second active region, a first active pattern and a second active pattern on the first and second active regions, respectively, a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns, which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns, which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes may include a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns may include silicon-germanium (SiGe). A concentration of germanium (Ge) of the second channel pattern may be higher than a concentration of germanium (Ge) of the first channel pattern, and a thickness of the first metal pattern of the second gate electrode may be greater than a thickness of the first metal pattern of the first gate electrode.
In some embodiments, a semiconductor device may include a substrate including a first active region and a second active region, a first active pattern and a second active pattern on the first and second active regions, respectively, a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns, which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns, which are provided in an upper portion of the second active pattern, first and second gate electrodes intersecting the first and second channel patterns, respectively, a first gate dielectric pattern between the first gate electrode and the first channel pattern, and a second gate dielectric pattern between the second gate electrode and the second channel pattern. A concentration of germanium (Ge) of the first channel pattern may be different from a concentration of germanium (Ge) of the second channel pattern, and the first gate dielectric pattern may include lanthanum (La) or aluminum (Al).
In some embodiments, a semiconductor device may include a substrate including a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction, a first active pattern and a second active pattern on the PMOSFET region and the NMOSFET region, respectively, the first and second active patterns extending in a second direction intersecting the first direction, the first active pattern having an upper portion including a semiconductor pattern, a device isolation layer on the substrate that extends over a sidewall of a lower portion of each of the first and second active patterns, the first and second active patterns having upper portions protruding upward from a top surface of the device isolation layer, a pair of first source/drain patterns in the upper portion of the first active pattern, a pair of second source/drain patterns in the upper portion of the second active pattern, a gate electrode intersecting the first and second active patterns and extending in the first direction, a gate dielectric pattern between the gate electrode and the first and second active patterns, active contacts electrically connected to the first and second source/drain patterns, and interconnection lines on the active contacts and electrically connected to the active contacts and the gate electrode. The semiconductor pattern of the first active pattern may include silicon-germanium (SiGe). The semiconductor pattern of the first active pattern may further include nitrogen (N) as an impurity. A concentration of germanium (Ge) in the semiconductor pattern may increase from a top surface of the semiconductor pattern toward a bottom surface of the semiconductor pattern. A concentration of nitrogen (N) in the semiconductor pattern may decrease from the top surface of the semiconductor pattern toward the bottom surface of the semiconductor pattern.
BRIEF DESCRIPTION OF THE DRAWINGS
The inventive concepts will become more apparent in view of the attached drawings and accompanying detailed description.
FIG. 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.
FIGS. 2A, 2B, 2C and 2D are cross-sectional views taken along lines A-A′, B-B′, C-C′ and D-D′ of FIG. 1 , respectively.
FIG. 3 is an enlarged cross-sectional view of a first active region of FIG. 2A.
FIGS. 4, 6, 8, 10, 12, 14 and 16 are plan views illustrating a method for manufacturing a semiconductor device according to some embodiments of the inventive concepts.
FIGS. 5A, 7A, 9A, 11A, 13A, 15A and 17A are cross-sectional views taken along lines A-A′ of FIGS. 4, 6, 8, 10, 12, 14 and 16 , respectively.
FIGS. 5B, 7B, 9B, 11B, 13B, 15B and 17B are cross-sectional views taken along lines B-B′ of FIGS. 4, 6, 8, 10, 12, 14 and 16 , respectively.
FIGS. 15C and 17C are cross-sectional views taken along lines C-C′ of FIGS. 14 and 16 , respectively.
FIGS. 15D and 17D are cross-sectional views taken along lines D-D′ of FIGS. 14 and 16 , respectively.
FIGS. 18 and 19 are cross-sectional views taken along the line A-A′ of FIG. 1 to illustrate semiconductor devices according to some embodiments of the inventive concepts.
FIGS. 20A, 20B and 20C are cross-sectional views taken along the lines A-A′, C-C′ and D-D′ of FIG. 1 , respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts.
 DETAILED DESCRIPTION OF THE EMBODIMENTS
FIG. 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts. FIGS. 2A, 2B, 2C and 2D are cross-sectional views taken along lines A-A′, B-B′, C-C′ and D-D′ of FIG. 1 , respectively. FIG. 3 is an enlarged cross-sectional view of a first active region of FIG. 2A.
Referring to FIGS. 1 and 2A to 2D, a substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. The substrate 100 may be a semiconductor substrate including silicon, germanium, or silicon-germanium or may be a compound semiconductor substrate. In some embodiments, the substrate 100 may be a silicon substrate.
In some embodiments, the PMOSFET region PR and the NMOSFET region NR may be included in a logic cell region on which logic transistors constituting a logic circuit of a semiconductor device are disposed. For example, the logic transistors constituting the logic circuit may be disposed on the logic cell region of the substrate 100. Some of the logic transistors may be disposed on the PMOSFET region PR and/or the NMOSFET region NR.
The PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR2 formed in an upper portion of the substrate 100. The second trench TR2 may be disposed between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1 with the second trench TR2 interposed therebetween. Each of the PMOSFET region PR and the NMOSFET region NR may extend in a second direction D2 intersecting the first direction D1. The first direction D1 may be perpendicular to the second direction D2.
The PMOSFET region PR may include a first active region PR1, a second active region PR2, and a third active region PR3. The first to third active regions PR1, PR2 and PR3 may be spaced apart from each other in the second direction D2. An absolute value of a threshold voltage of a PMOS transistor on the first active region PR1 may be higher than an absolute value of a threshold voltage of a PMOS transistor on the second active region PR2. The absolute value of the threshold voltage of the PMOS transistor on the second active region PR2 may be higher than an absolute value of a threshold voltage of a PMOS transistor on the third active region PR3.
First active patterns AP1 may be provided on the PMOSFET region PR, and second active patterns AP2 may be provided on the NMOSFET region NR. The first and second active patterns AP1 and AP2 may extend in the second direction D2. The first and second active patterns AP1 and AP2 may be portions of the substrate 100, which vertically protrude. First trenches TR1 may be defined between the first active patterns AP1 adjacent to each other and between the second active patterns AP2 adjacent to each other. The first trench TR1 may be shallower than the second trench TR2.
A device isolation layer ST may fill the first and second trenches TR1 and TR2. For example, the device isolation layer ST may include a silicon oxide layer. Upper portions of the first and second active patterns AP1 and AP2 may vertically protrude from the device isolation layer ST (see FIG. 2C). Each of the upper portions of the first and second active patterns AP1 and AP2 may have a fin shape. The device isolation layer ST may not cover or extend over the upper portions of the first and second active patterns AP1 and AP2. The device isolation layer ST may cover, overlap, or extend over sidewalls of lower portions of the first and second active patterns AP1 and AP2.
An upper portion of the first active pattern AP1 of the first active region PR1 may include a first semiconductor pattern SP1. An upper portion of the first active pattern AP1 of the second active region PR2 may include a second semiconductor pattern SP2. An upper portion of the first active pattern AP1 of the third active region PR3 may include a third semiconductor pattern SP3. Each of the first to third semiconductor patterns SP1, SP2 and SP3 may include silicon-germanium (SiGe). Each of the first to third semiconductor patterns SP1, SP2 and SP3 may be used as a first channel pattern CH1 to be described later. In other words, the PMOS transistors according to some embodiments of the inventive concepts may have channels formed of silicon-germanium (SiGe).
The first semiconductor pattern SP1 will be mainly described in detail with reference to FIG. 3 . The first semiconductor pattern SP1 may further include nitrogen (N) as impurities. Nitrogen (N) may be diffused into the first semiconductor pattern SP1 in a process of forming the first semiconductor pattern SP1.
A concentration of nitrogen (N) may gradually decrease from a top surface SP1 t of the first semiconductor pattern SP1 to a bottom surface SP1 b of the first semiconductor pattern SP1. A concentration of nitrogen (N) at the top surface SP1 t of the first semiconductor pattern SP1 may range from 6 atomic percent (at %) to 8 at %, and a concentration of nitrogen (N) at the bottom surface SP1 b of the first semiconductor pattern SP1 may be 1 at %. For example, the concentration of nitrogen (N) may decrease from 7 at % to 1 at % as a distance from the top surface SP1 t toward the bottom surface SP1 b increases.
A concentration of germanium (Ge) in the first semiconductor pattern SP1 may gradually increase from the top surface SP1 t of the first semiconductor pattern SP1 to the bottom surface SP1 b of the first semiconductor pattern SP1. A concentration of germanium (Ge) at the top surface SP1 t of the first semiconductor pattern SP1 may range from 5 at % to 15 at %, and a concentration of germanium (Ge) at the bottom surface SP1 b of the first semiconductor pattern SP1 may be about 30 at %. For example, the concentration of germanium (Ge) may increase from 10 at % to 30 at % as a distance from the top surface SP1 t toward the bottom surface SP1 b increases.
Referring again to FIGS. 1 and 2A to 2D, concentrations of nitrogen (N) of the first to third semiconductor patterns SP1, SP2 and SP3 may be different from each other. Here, the concentration of nitrogen (N) may be a concentration measured at the top surface (e.g., SP1 t of FIG. 3 ) of each of the first to third semiconductor patterns SP1, SP2 and SP3.
Like the first semiconductor pattern SP1, a concentration of nitrogen (N) in the second semiconductor pattern SP2 may gradually decrease from its top surface to its bottom surface. The concentration of nitrogen (N) at the top surface of the second semiconductor pattern SP2 may range from 3 at % to 6 at %, and a concentration of nitrogen (N) at the bottom surface of the second semiconductor pattern SP2 may be 1 at %.
Like the first semiconductor pattern SP1, a concentration of nitrogen (N) in the third semiconductor pattern SP3 may gradually decrease from its top surface to its bottom surface. The concentration of nitrogen (N) at the top surface of the third semiconductor pattern SP3 may range from 0 at % to 4 at %. For an example, the third semiconductor pattern SP3 may not include nitrogen (N).
Concentrations of germanium (Ge) of the first to third semiconductor patterns SP1, SP2 and SP3 may be different from each other. Here, the concentration of germanium (Ge) may be a concentration measured at the top surface (e.g., SP1 t of FIG. 3 ) of each of the first to third semiconductor patterns SP1, SP2 and SP3. The concentration of germanium (Ge) of the first semiconductor pattern SP1 may be lower than the concentration of germanium (Ge) of the second semiconductor pattern SP2. The concentration of germanium (Ge) of the second semiconductor pattern SP2 may be lower than the concentration of germanium (Ge) of the third semiconductor pattern SP3. For example, the concentration of germanium (Ge) of the first semiconductor pattern SP1 may range from 5 at % to 15 at %. The concentration of germanium (Ge) of the second semiconductor pattern SP2 may range from 10 at % to 20 at %. The concentration of germanium (Ge) of the third semiconductor pattern SP3 may range from 20 at % to 30 at %.
The first to third semiconductor patterns SP1, SP2 and SP3 may be provided in the upper portion of the first active pattern AP1. The first to third semiconductor patterns SP1, SP2 and SP3 may not be provided in an upper portion of the second active pattern AP2. Thus, the upper portion of the second active pattern AP2 may include silicon (Si).
First source/drain patterns SD1 may be provided in the upper portion of the first active pattern AP1. The first source/drain patterns SD1 may be dopant regions having a first conductivity type (e.g., a P-type). A first channel pattern CH1 may be disposed between a pair of the first source/drain patterns SD1. The bottom surface of each of the first to third semiconductor patterns SP1, SP2 and SP3 may be lower than a bottom surface of each of the first source/drain patterns SD1. In some embodiments, such as FIG. 2D, the first source/drain patterns SD1 may be merged together.
Second source/drain patterns SD2 may be provided in the upper portions of the second active patterns AP2. The second source/drain patterns SD2 may be dopant regions having a second conductivity type (e.g., an N-type). A second channel pattern CH2 may be disposed between a pair of the second source/drain patterns SD2. In some embodiments, such as FIG. 2D, the second source/drain patterns SD2 may be merged together.
The first and second source/drain patterns SD1 and SD2 may include epitaxial patterns formed by a selective epitaxial growth (SEG) process. In some embodiments, a top surface of each of the first and second source/drain patterns SD1 and SD2 may be disposed at substantially the same level as a top surface of each of the first and second channel patterns CH1 and CH2.
The first source/drain patterns SD1 may include a semiconductor element (e.g., SiGe) of which a lattice constant is greater than that of a semiconductor element of the substrate 100. Thus, the first source/drain patterns SD1 may provide compressive stress to the first channel patterns CH1. The second source/drain patterns SD2 may include the same semiconductor element (e.g., silicon) as the substrate 100.
Gate electrodes GE may extend in the first direction D1 to intersect the first and second active patterns AP1 and AP2. The gate electrodes GE may be spaced apart from each other in the second direction D2. The gate electrodes GE may vertically overlap with the first and second channel patterns CH1 and CH2 in the third direction D3.
Referring again to FIG. 2C, the gate electrode GE may be provided on a first top surface TS1 of the first channel pattern CH1 and at least one first sidewall SW1 of the first channel pattern CH1. The gate electrode GE may be provided on a second top surface TS2 of the second channel pattern CH2 and at least one second sidewall SW2 of the second channel pattern CH2. In other words, the transistors according to some embodiments may be three-dimensional (3D) field effect transistors (e.g., FinFETs) in which the gate electrode GE three-dimensionally surrounds channels CH1 and CH2.
Referring again to FIGS. 1 and 2A to 2D, a pair of gate spacers GS may be disposed on both sidewalls of each of the gate electrodes GE, respectively. The gate spacers GS may extend along the gate electrodes GE in the first direction D1. Top surfaces of the gate spacers GS may be higher than top surfaces of the gate electrodes GE. The top surfaces of the gate spacers GS may be coplanar with a top surface of a first interlayer insulating layer 110 to be described later. The gate spacers GS may include at least one of SiCN, SiCON, or SiN. In certain embodiments, each of the gate spacers GS may have a multi-layered structure formed of at least two of SiCN, SiCON, or SiN.
A gate capping pattern GP may be provided on each of the gate electrodes GE. The gate capping pattern GP may extend along the gate electrode GE in the first direction D1. The gate capping patterns GP may include a material having an etch selectivity with respect to first and second interlayer insulating layers 110 and 120 to be described later. For example, the gate capping patterns GP may include at least one of SiON, SiCN, SiCON, or SiN.
A gate dielectric pattern GI may be disposed between the gate electrode GE and the first active pattern AP1 and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI may extend along a bottom surface of the gate electrode GE thereon. For example, the gate dielectric pattern GI may cover the top surface and both sidewalls of the first channel pattern CH1. The gate dielectric pattern GI may cover the top surface and both sidewalls of the second channel pattern CH2. The gate dielectric pattern GI may cover a top surface of the device isolation layer ST under the gate electrode GE (see FIG. 2C).
In some embodiments, the gate dielectric pattern GI may include a high-k dielectric material of which a dielectric constant is higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium-silicon oxide, hafnium-zirconium oxide, hafnium-tantalum oxide, lanthanum oxide, zirconium oxide, zirconium-silicon oxide, tantalum oxide, titanium oxide, barium-strontium-titanium oxide, barium-titanium oxide, strontium-titanium oxide, lithium oxide, aluminum oxide, lead-scandium-tantalum oxide, or lead-zinc niobate.
In some embodiments, the gate dielectric pattern GI may include a ferroelectric material. The gate dielectric pattern GI including the ferroelectric material may function as a negative capacitor. Negative capacitance occurs when a change in charge causes the net voltage across a material to change in the opposite direction. In other words, a decrease in voltage leads to an increase in charge. For example, when an external voltage is applied to the ferroelectric material, a negative capacitance effect by a phase change from an initial polarity state to another state may be generated by movement of dipoles in the ferroelectric material. In this case, a total capacitance of the transistor including the ferroelectric material in the embodiments may be increased, and thus a sub-threshold swing characteristic of the transistor may be improved and an operating voltage of the transistor may be reduced.
The ferroelectric material of the gate dielectric pattern GI may include hafnium oxide doped with (or containing) at least one of zirconium (Zr), silicon (Si), aluminum (Al), or lanthanum (La). Since hafnium oxide is doped with at least one of zirconium (Zr), silicon (Si), aluminum (Al), or lanthanum (La) at a predetermined ratio, at least a portion of the ferroelectric material may have an orthorhombic crystal structure. When at least a portion of the ferroelectric material has the orthorhombic crystal structure, the negative capacitance effect may be generated. A volume ratio of a portion having the orthorhombic crystal structure in the ferroelectric material may range from 10% to 50%.
When the ferroelectric material includes zirconium-doped hafnium oxide (ZrHfO), a ratio of Zr atoms to a sum of Zr atoms and Hf atoms (Zr/(Hf+Zr)) may range from 45 at % to 55 at %. When the ferroelectric material includes silicon-doped hafnium oxide (SiHfO), a ratio of Si atoms to a sum of Si atoms and Hf atoms (Si/(Hf+Si)) may range from 4 at % to 6 at %. When the ferroelectric material includes aluminum-doped hafnium oxide (AlHfO), a ratio of Al atoms to a sum of Al atoms and Hf atoms (Al/(Hf+Al)) may range from 5 at % to 10 at %. When the ferroelectric material includes lanthanum-doped hafnium oxide (LaHfO), a ratio of La atoms to a sum of La atoms and Hf atoms (La/(Hf+La)) may range from 5 at % to 10 at %.
Each of the gate electrodes GE may include a first metal pattern WF1, a second metal pattern WF2, and an electrode pattern EL. The first metal pattern WF1 may be provided on the gate dielectric pattern GI. For example, the gate dielectric pattern GI may be disposed between the first metal pattern WF1 and the first channel pattern CH1.
The gate dielectric pattern GI and the first metal pattern WF1 may be chamfered (i.e., cut away at a right-angled edge or corner to make a symmetrical sloping edge), and thus upper portions thereof may be lower than the topmost surface GEt of the gate electrode GE. For example, the first metal pattern WF1 may have a recessed top surface RSt, and the recessed top surface RSt may be lower than the topmost surface GEt of the gate electrode GE.
The first metal pattern WF1 may include a metal nitride having a relatively high work function. The work function is the minimum amount of energy required to make the free electrons escape from the metal surface. If a material has a high work function, then a high amount of energy may be needed to make electrons escape from the metal surface. The first metal pattern WF1 may include a P-type work function metal. For example, the first metal pattern WF1 may include titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium-silicon nitride (TiSiN), titanium-aluminum nitride (TiAlN), tungsten carbonitride (WCN), and/or molybdenum nitride (MoN).
The second metal pattern WF2 may be provided on the first metal pattern WF1. The second metal pattern WF2 may cover or extend over the recessed top surface RSt of the first metal pattern WF1. The second metal pattern WF2 may include a metal carbide having a relatively low work function. In other words, the second metal pattern WF2 may include an N-type work function metal. The second metal pattern WF2 may include a metal carbide doped with (or containing) silicon and/or aluminum. For example, the second metal pattern WF2 may include aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), and/or silicon-doped tantalum carbide (TaSiC). For other examples, the second metal pattern WF2 may include titanium carbide doped with aluminum and silicon (TiAlSiC), or tantalum carbide doped with aluminum and silicon (TaAlSiC). For still another example, the second metal pattern WF2 may include aluminum-doped titanium (TiAl).
In the second metal pattern WF2, the work function of the second metal pattern WF2 may be adjusted by adjusting a doping concentration of silicon or aluminum corresponding to a dopant. For example, a concentration of the dopant (e.g., silicon or aluminum) in the second metal pattern WF2 may range from 0.1 at % to 25 at %.
The electrode pattern EL may be provided on the second metal pattern WF2. A resistance of the electrode pattern EL may be lower than respective resistances of the first and second metal patterns WF1 and WF2. For example, the electrode pattern EL may include a low-resistance metal including at least one of aluminum (Al), tungsten (W), titanium (Ti), or tantalum (Ta).
According to some embodiments of the inventive concepts, the first and second metal patterns WF1 and WF2 may be adjacent to the first channel pattern CH1. The first and second metal patterns WF1 and WF2 may function as a work function metal for adjusting the threshold voltage of the PMOS transistor. In other words, a desired threshold voltage may be obtained by adjusting a thickness and/or a composition of each of the first and second metal patterns WF1 and WF2.
A thickness of the first metal pattern WF1 on the second active region PR2 may be greater than a thickness of the first metal pattern WF1 on the first active region PR1. A thickness of the first metal pattern WF1 on the third active region PR3 may be greater than the thickness of the first metal pattern WF1 on the second active region PR2. As discussed herein, the thickness of the first metal pattern WF1 may be a width, in the second direction D2, of an upper portion of the first metal pattern WF1 adjacent to the gate spacer GS.
The thicknesses of the first metal patterns WF1 may sequentially increase from the first active region PR1 to the third active region PR3. In other words, effective work functions (eWF) of the gate electrodes GE may sequentially increase from the first active region PR1 to the third active region PR3. Thus, the absolute values of the threshold voltages of the PMOS transistors may sequentially decrease from the first active region PR1 to the third active region PR3.
In addition, the effective work functions of the gate electrodes GE may also be adjusted by the concentrations of germanium (Ge) of the first to third semiconductor patterns SP1, SP2 and SP3. The effective work function of the gate electrode GE may increase as the concentration of germanium (Ge) of the semiconductor pattern SP1, SP2 or SP3 increases. Since the concentrations of germanium (Ge) of the first to third semiconductor patterns SP1, SP2 and SP3 increase in the order listed, the effective work functions of the gate electrodes GE may sequentially increase from the first active region PR1 to the third active region PR3. Thus, the absolute values of the threshold voltages of the PMOS transistors may sequentially decrease from the first active region PR1 to the third active region PR3.
In detail, the concentration of germanium (Ge) of the third semiconductor pattern SP3 of the third active region PR3 may be greater than the concentration of germanium (Ge) of the first semiconductor pattern SP1 of the first active region PR1. In addition, the thickness of the first metal pattern WF1 on the third active region PR3 may be greater than the thickness of the first metal pattern WF1 on the first active region PR1. The effective work function of the gate electrode GE on the third active region PR3 may be relatively increased by interaction of the thickness of the first metal pattern WF1 on the third active region PR3 and the concentration of germanium (Ge) of the third semiconductor pattern SP3. The effective work function of the gate electrode GE on the first active region PR1 may be relatively decreased by interaction of the thickness of the first metal pattern WF1 on the first active region PR1 and the concentration of germanium (Ge) of the first semiconductor pattern SP1. As a result, the absolute value of the threshold voltage of the PMOS transistor on the third active region PR3 may be much lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR1.
A first interlayer insulating layer 110 may be provided on the substrate 100. The first interlayer insulating layer 110 may cover or extend over the gate spacers GS and the first and second source/drain patterns SD1 and SD2. A top surface of the first interlayer insulating layer 110 may be substantially coplanar with top surfaces of the gate capping patterns GP and top surfaces of the gate spacers GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 and the gate capping patterns GP. For example, each of the first and second interlayer insulating layers 110 and 120 may include a silicon oxide layer.
Active contacts AC may penetrate the second and first interlayer insulating layers 120 and 110 so as to be electrically connected to the first and second source/drain patterns SD1 and SD2. Each of the active contacts AC may be provided between a pair of the gate electrodes GE.
The active contact AC may be a self-aligned contact. In other words, the active contact AC may be formed to be self-aligned using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover, overlap, or extend over at least a portion of a sidewall of the gate spacer GS. Even though not shown in the drawings, the active contact AC may cover or extend over a portion of the top surface of the gate capping pattern GP.
Silicide patterns SC may be disposed between the active contact AC and the first source/drain pattern SD1 and between the active contact AC and the second source/drain pattern SD2, respectively. The active contact AC may be electrically connected to the source/drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC may include a metal silicide and may include at least one of, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or a cobalt silicide.
The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal of aluminum, copper, tungsten, molybdenum, or cobalt. The barrier pattern BM may cover a bottom surface and sidewalls of the conductive pattern FM. The barrier pattern BM may include a metal layer/a metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may include at least one of a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, or a platinum nitride (PtN) layer.
A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A first metal layer may be provided in the third interlayer insulating layer 130. The first metal layer may include first interconnection lines M1, first vias V1, and second vias V2. The first and second vias V1 and V2 may be provided under the first interconnection lines M1.
The first interconnection lines M1 may extend in the second direction D2 in parallel to each other. The first interconnection lines M1 may be arranged in the first direction D1. The first via V1 may be disposed between the active contact AC and a corresponding one of the first interconnection lines M1 to electrically connect the active contact AC to the corresponding one of the first interconnection lines M1. The second via V2 may be disposed between the gate electrode GE and a corresponding one of the first interconnection lines M1 to electrically connect the gate electrode GE to the corresponding one of the first interconnection lines M1.
For example, the first interconnection line M1 and the first or second via V1 or V2 disposed thereunder may be connected to each other to constitute a single unitary conductive structure. In other words, the first interconnection line M1 and the first or second via V1 or V2 may be formed together. The first interconnection line M1 and the first or second via V1 or V2 may be formed as the single unitary conductive structure by using a dual damascene process. Even though not shown in the drawings, stacked metal layers may be additionally disposed on the third interlayer insulating layer 130.
FIGS. 4, 6, 8, 10, 12, 14 and 16 are plan views illustrating a method for manufacturing a semiconductor device according to some embodiments of the inventive concepts. FIGS. 5A, 7A, 9A, 11A, 13A, 15A and 17A are cross-sectional views taken along lines A-A′ of FIGS. 4, 6, 8, 10, 12, 14 and 16 , respectively. FIGS. 5B, 7B, 9B, 11B, 13B, 15B and 17B are cross-sectional views taken along lines B-B′ of FIGS. 4, 6, 8, 10, 12, 14 and 16 , respectively. FIGS. 15C and 17C are cross-sectional views taken along lines C-C′ of FIGS. 14 and 16 , respectively. FIGS. 15D and 17D are cross-sectional views taken along lines D-D′ of FIGS. 14 and 16 , respectively.
Referring to FIGS. 4, 5A and 5B, a substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. A semiconductor layer SL may be formed on the PMOSFET region PR of the substrate 100. The formation of the semiconductor layer SL may include forming a trench on the PMOSFET region PR of the substrate 100, and performing a selective epitaxial growth (SEG) process on the PMOSFET region PR to form the semiconductor layer SL filling the trench. The semiconductor layer SL may not be formed on the NMOSFET region NR.
The semiconductor layer SL may include silicon-germanium (SiGe). A concentration of germanium (Ge) of the semiconductor layer SL may range from 20 at % to 30 at %.
Referring to FIGS. 6, 7A and 7B, a first mask layer ML1 may be formed on the NMOSFET region NR and a third active region PR3 of the PMOSFET region PR. The first mask layer ML1 may expose first and second active regions PR1 and PR2 of the PMOSFET region PR.
A first plasma treatment PA1 may be performed on the first and second active regions PR1 and PR2 exposed by the first mask layer ML1. The first plasma treatment PA1 may include an annealing process using hydrogen plasma. The hydrogen plasma may be provided onto the semiconductor layer SL on the first and second active regions PR1 and PR2, i.e., onto the exposed semiconductor layer SL. At this time, a natural oxide layer (e.g., a germanium oxide (GeO) layer) formed on the exposed semiconductor layer SL may be volatilized by the hydrogen plasma treatment and thus may be removed. In other words, germanium (Ge) of an exposed surface of the semiconductor layer SL may be selectively removed during the first plasma treatment PM. Even though not shown in the drawings, a silicon-rich layer may be formed on the exposed surface of the semiconductor layer SL by the removal of germanium (Ge) of the exposed surface of the semiconductor layer SL.
Due to the first plasma treatment PA1, a concentration of germanium (Ge) of the semiconductor layer SL on the first and second active regions PR1 and PR2 may be reduced as compared with the concentration of germanium (Ge) of the semiconductor layer SL on the third active region PR3. For example, the concentration of germanium (Ge) of the exposed surface of the semiconductor layer SL may be reduced by about 5 at % during the first plasma treatment PM. Germanium (Ge) in the exposed semiconductor layer SL may have a concentration gradient by the first plasma treatment PA1 (see FIG. 3 ).
Nitrogen (N) may be diffused into the exposed semiconductor layer SL in the first plasma treatment PA1. Nitrogen (N) may be generated from a coating material inside an apparatus for performing the first plasma treatment PM. Since nitrogen (N) is diffused into the exposed semiconductor layer SL, nitrogen (N) in the exposed semiconductor layer SL may have a concentration gradient (see FIG. 3 ).
Referring to FIGS. 8, 9A and 9B, the first mask layer ML1 may be removed. A second mask layer ML2 may be formed on the NMOSFET region NR and the second and third active regions PR2 and PR3 of the PMOSFET region PR. The second mask layer ML2 may expose the first active region PR1 of the PMOSFET region PR.
A second plasma treatment PA2 may be performed on the first active region PR1 exposed by the second mask layer ML2. The second plasma treatment PA2 may include an annealing process using hydrogen plasma. The second plasma treatment PA2 may be substantially the same as the first plasma treatment PA1 described above.
Due to the second plasma treatment PA2, a concentration of germanium (Ge) of the semiconductor layer SL on the first active region PR1 may be reduced as compared with the concentration of germanium (Ge) of the semiconductor layer SL on the second active region PR2. For example, the concentration of germanium (Ge) of the exposed surface of the semiconductor layer SL may be reduced by about 5 at % during the second plasma treatment PA2.
As a result, the semiconductor layer SL of the first active region PR1, on which the first and second plasma treatments PA1 and PA2 are performed, may have the lowest germanium concentration. The semiconductor layer SL of the third active region PR3, on which the first and second plasma treatments PA1 and PA2 are not performed, may have the highest germanium concentration.
Referring to FIGS. 10, 11A and 11B, the second mask layer ML2 may be removed. The substrate 100 may be patterned to form first and second active patterns AP1 and AP2. The first active patterns AP1 may be formed on the PMOSFET region PR, and the second active patterns AP2 may be formed on the NMOSFET region NR. First trenches TR1 may be formed between the first active patterns AP1 and between the second active patterns AP2.
The formation of the first active patterns AP1 may include patterning the semiconductor layer SL to form first to third semiconductor patterns SP1, SP2 and SP3 on the first to third active regions PR1, PR2 and PR3, respectively. In other words, an upper portion of the first active pattern AP1 of the first active region PR1 may include the first semiconductor pattern SP1. An upper portion of the first active pattern AP1 of the second active region PR2 may include the second semiconductor pattern SP2. An upper portion of the first active pattern AP1 of the third active region PR3 may include the third semiconductor pattern SP3.
The substrate 100 may be patterned to form a second trench TR2 between the PMOSFET region PR and the NMOSFET region NR. The second trench TR2 may be deeper than the first trench TR1.
A device isolation layer ST may be formed on the substrate 100 to fill the first and second trenches TR1 and TR2. The device isolation layer ST may include an insulating material such as a silicon oxide layer. The device isolation layer ST may be recessed until upper portions of the first and second active patterns AP1 and AP2 are exposed. Thus, the upper portions of the first and second active patterns AP1 and AP2 may vertically protrude from the device isolation layer ST. The first to third semiconductor patterns SP1, SP2 and SP3 of the first active pattern AP1 may vertically protrude from the device isolation layer ST.
Referring to FIGS. 12, 13A and 13B, sacrificial patterns PP may be formed to intersect the first and second active patterns AP1 and AP2. The sacrificial patterns PP may have line shapes or bar shapes, which extend in the first direction D1. For example, the formation of the sacrificial patterns PP may include forming a sacrificial layer on an entire top surface of the substrate 100, forming hard mask patterns MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask patterns MA as etch masks. The sacrificial layer may include poly-silicon.
A pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns PP, respectively. The formation of the gate spacers GS may include conformally forming a gate spacer layer on an entire top surface of the substrate 100 and anisotropically etching the gate spacer layer. For example, the gate spacer layer may include at least one of SiCN, SiCON, or SiN. In some embodiments, the gate spacer layer may be formed of a multi-layer including at least two of SiCN, SiCON, or SiN.
Referring to FIGS. 14 and 15A to 15D, first source/drain patterns SD1 may be formed in an upper portion of the first active pattern AP1. A pair of the first source/drain patterns SD1 may be formed at both sides of each of the sacrificial patterns PP.
In detail, the upper portion of the first active pattern AP1 may be etched using the hard mask patterns MA and the gate spacers GS as etch masks to form first recess regions. The device isolation layer ST between the first active patterns AP1 may be recessed while the upper portions of the first active patterns AP1 are etched.
The first source/drain patterns SD1 may be formed by performing a selective epitaxial growth (SEG) process using inner surfaces of the first recess regions of the first active patterns AP1 as a seed layer. Since the first source/drain patterns SD1 are formed, a first channel pattern CH1 may be defined between the pair of first source/drain patterns SD1. For example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source/drain patterns SD1 may include a semiconductor element (e.g., SiGe) of which a lattice constant is greater than that of a semiconductor element of the substrate 100. In some embodiments, each of the first source/drain patterns SD1 may be formed of a plurality of stacked semiconductor layers.
In some embodiments, dopants may be injected in-situ into the first source/drain patterns SD1 during the SEG process for forming the first source/drain patterns SD1. In certain embodiments, the dopants may be injected or implanted into the first source/drain patterns SD1 after the SEG process for forming the first source/drain patterns SD1. The first source/drain patterns SD1 may be doped with the dopants to have a first conductivity type (e.g., a P-type).
Second source/drain patterns SD2 may be formed in an upper portion of the second active pattern AP2. A pair of the second source/drain patterns SD2 may be formed at both sides of each of the sacrificial patterns PP.
In detail, the upper portion of the second active pattern AP2 may be etched using the hard mask patterns MA and the gate spacers GS as etch masks to form second recess regions. The second source/drain patterns SD2 may be formed by performing a SEG process using inner surfaces of the second recess regions of the second active pattern AP2 as a seed layer. Since the second source/drain patterns SD2 are formed, a second channel pattern CH2 may be defined between the pair of second source/drain patterns SD2. For example, the second source/drain patterns SD2 may include the same semiconductor element (e.g., silicon) as the substrate 100. The second source/drain patterns SD2 may be doped with dopants to have a second conductivity type (e.g., an N-type).
The first source/drain patterns SD1 and the second source/drain patterns SD2 may be sequentially formed by different processes from each other. In other words, the first source/drain patterns SD1 may not be formed simultaneously with the second source/drain patterns SD2.
Referring to FIGS. 16 and 17A to 17D, a first interlayer insulating layer 110 may be formed to cover, overlap, or extend over the first and second source/drain patterns SD1 and SD2, the hard mask patterns MA, and the gate spacers GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.
The first interlayer insulating layer 110 may be planarized until top surfaces of the sacrificial patterns PP are exposed. The planarization process of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask patterns MA may be completely removed during the planarization process. As a result, a top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surfaces of the sacrificial patterns PP and top surfaces of the gate spacers GS.
The sacrificial patterns PP may be replaced with gate electrodes GE, respectively. In more detail, the exposed sacrificial patterns PP may be selectively removed. Empty spaces may be formed by the removal of the sacrificial patterns PP. A gate dielectric pattern GI, a gate electrode GE and a gate capping pattern GP may be formed in each of the empty spaces. The gate electrode GE may include a first metal pattern WF1, a second metal pattern WF2, and an electrode pattern EL.
The first metal pattern WF1 on the second active region PR2 may be formed to be thicker than the first metal pattern WF1 on the first active region PR1. The first metal pattern WF1 on the third active region PR3 may be formed to be thicker than the first metal pattern WF1 on the second active region PR2.
Referring again to FIGS. 1 and 2A to 2D, a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. Active contacts AC may be formed in the second and first interlayer insulating layers 120 and 110. The active contacts AC may penetrate the second and first interlayer insulating layers 120 and 110 so as to be electrically connected to the first and second source/drain patterns SD1 and SD2.
A third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. A first metal layer may be formed in the third interlayer insulating layer 130. The first metal layer may include first interconnection lines M1, first vias V1, and second vias V2.
FIGS. 18 and 19 are cross-sectional views taken along the line A-A′ of FIG. 1 to illustrate semiconductor devices according to some embodiments of the inventive concepts. In the present embodiments, the descriptions to the same technical features as in the embodiments of FIGS. 1 and 2A to 2D will be omitted for the purpose of ease and convenience in explanation. In other words, differences between the present embodiments and the embodiments of FIGS. 1 and 2A to 2D will be mainly described hereinafter.
Referring to FIG. 18 , first to third gate dielectric patterns GI1, GI2 and GI3 may be provided on the first to third active regions PR1, PR2 and PR3, respectively. The first gate dielectric pattern GI1 may be disposed between the gate electrode GE and the first semiconductor pattern SP1. The second gate dielectric pattern GI2 may be disposed between the gate electrode GE and the second semiconductor pattern SP2. The third gate dielectric pattern GI3 may be disposed between the gate electrode GE and the third semiconductor pattern SP3. Thicknesses of first metal patterns WF1 on the first to third active regions PR1, PR2 and PR3 may be equal to each other.
The first gate dielectric pattern GI1 may include a first dipole. The first dipole may include lanthanum (La). For example, the first gate dielectric pattern GI1 may include hafnium oxide containing lanthanum (La). The hafnium oxide containing lanthanum (La) in the first gate dielectric pattern GI1 may reduce an effective work function of the gate electrode GE.
The formation of the first gate dielectric pattern GI1 may include forming a first dipole layer including lanthanum oxide on the first gate dielectric pattern GI1, and performing an annealing process on the first dipole layer to diffuse lanthanum into the first gate dielectric pattern GI1. Thus, a first dipole-interface may be formed in the first gate dielectric pattern GI1.
The third gate dielectric pattern GI3 may include a second dipole. The second dipole may include aluminum (Al). For example, the third gate dielectric pattern GI3 may include hafnium oxide containing aluminum (Al). The hafnium oxide containing aluminum (Al) in the third gate dielectric pattern GI3 may increase an effective work function of the gate electrode GE.
The formation of the third gate dielectric pattern GI3 may include forming a second dipole layer including aluminum oxide on the third gate dielectric pattern GI3, and performing an annealing process on the second dipole layer to diffuse aluminum into the third gate dielectric pattern GI3. Thus, a second dipole-interface may be formed in the third gate dielectric pattern GI3.
The second gate dielectric pattern GI2 may not include a dipole. In other words, the second gate dielectric pattern GI2 may include hafnium oxide. The second gate dielectric pattern GI2 may be substantially the same as the gate dielectric pattern GI described above with reference to FIGS. 1 and 2A to 2D.
The effective work function of the gate electrode GE on the third active region PR3 may be relatively increased by interaction of the third gate dielectric pattern GI3 on the third active region PR3 and the concentration of germanium (Ge) of the third semiconductor pattern SP3. The effective work function of the gate electrode GE on the first active region PR1 may be relatively decreased by interaction of the first gate dielectric pattern GI1 on the first active region PR1 and the concentration of germanium (Ge) of the first semiconductor pattern SP1. As a result, without changing the thicknesses of the first metal patterns WF1, the absolute value of the threshold voltage of the PMOS transistor on the third active region PR3 may be much lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR1.
Referring to FIG. 19 , thicknesses of first metal patterns WF1 on the first to third active regions PR1, PR2 and PR3 may be equal to each other. However, materials of the first metal patterns WF1 on the first to third active regions PR1, PR2 and PR3 may be different from each other.
In detail, the first metal pattern WF1 on the first active region PR1 may include a first work function metal W1. The first work function metal W1 may be a metal having a relatively low work function. The first work function metal W1 may include titanium-aluminum nitride (TiAlN), titanium-silicon nitride (TiSiN), and/or tantalum nitride (TaN). The first metal pattern WF1 on the second active region PR2 may include a second work function metal W2. The second work function metal W2 may include titanium nitride (TiN). The first metal pattern WF1 on the third active region PR3 may include a third work function metal W3. The third work function metal W3 may be a metal having a relatively high work function. The third work function metal W3 may include titanium oxynitride (TiON), tungsten carbonitride (WCN), or molybdenum nitride (MoN).
The effective work function of the gate electrode GE on the third active region PR3 may be relatively increased by interaction of the third work function metal W3 on the third active region PR3 and the concentration of germanium (Ge) of the third semiconductor pattern SP3. The effective work function of the gate electrode GE on the first active region PR1 may be relatively decreased by interaction of the first work function metal W1 on the first active region PR1 and the concentration of germanium (Ge) of the first semiconductor pattern SP1. As a result, without changing the thicknesses of the first metal patterns WF1, the absolute value of the threshold voltage of the PMOS transistor on the third active region PR3 may be much lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR1.
FIGS. 20A, 20B and 20C are cross-sectional views taken along the lines A-A′, C-C′ and D-D′ of FIG. 1 , respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts. In the present embodiment, the descriptions to the same technical features as in the embodiments of FIGS. 1, 2A to 2D and 18 will be omitted for the purpose of ease and convenience in explanation. In other words, differences between the present embodiment and the embodiments of FIGS. 1, 2A to 2D and 18 will be mainly described hereinafter.
Referring to FIGS. 1 and 20A to 20C, a substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. A device isolation layer ST may be provided on the substrate 100. The device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 on the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be defined on the PMOSFET region PR and the NMOSFET region NR, respectively.
An upper portion of the first active pattern AP1 may include first to third semiconductor patterns SP1, SP2 and SP3. The first to third semiconductor patterns SP1, SP2 and SP3 may be provided on first to third active regions PR1, PR2 and PR3 of the PMOSFET region PR, respectively.
Each of the first to third semiconductor patterns SP1, SP2 and SP3 may include first channel patterns CH1 which are vertically stacked. The stacked first channel patterns CH1 may be spaced apart from each other in a third direction D3. The stacked first channel patterns CH1 may vertically overlap with each other.
The second active pattern AP2 may include second channel patterns CH2 which are vertically stacked. The stacked second channel patterns CH2 may be spaced apart from each other in the third direction D3. The stacked second channel patterns CH2 may vertically overlap with each other. The first and second channel patterns CH1 and CH2 may include at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).
The first active pattern AP1 may further include first source/drain patterns SD1. The stacked first channel patterns CH1 may be disposed between a pair of the first source/drain patterns SD1 adjacent to each other. The stacked first channel patterns CH1 may connect the pair of first source/drain patterns SD1 adjacent to each other.
The second active pattern AP2 may further include second source/drain patterns SD2. The stacked second channel patterns CH2 may be disposed between a pair of the second source/drain patterns SD2 adjacent to each other. The stacked second channel patterns CH2 may connect the pair of second source/drain patterns SD2 adjacent to each other.
Gate electrodes GE may extend in the first direction D1 to intersect the first and second channel patterns CH1 and CH2. The gate electrodes GE may vertically overlap with the first and second channel patterns CH1 and CH2. A pair of gate spacers GS may be disposed on both sidewalls of each of the gate electrodes GE, respectively. A gate capping pattern GP may be provided on each of the gate electrodes GE.
The gate electrode GE may surround each of the first and second channel patterns CH1 and CH2 (see FIG. 20B) in the first direction D1 and/or the third direction D3. The gate electrode GE may be provided on a first top surface TS1, at least one first sidewall SW1 and a first bottom surface BS1 of the first channel pattern CH1. The gate electrode GE may be provided on a second top surface TS2, at least one second sidewall SW2 and a second bottom surface BS2 of the second channel pattern CH2. In other words, the gate electrode GE may surround the top surface, the bottom surface and both sidewalls of each of the first and second channel patterns CH1 and CH2. Transistors according to some embodiment may be 3D field effect transistors (e.g., MBCFETs) in which the gate electrode GE three-dimensionally surrounds the channel patterns CH1 and CH2.
A first gate dielectric pattern GI1 may be provided between the gate electrode GE and the first channel pattern CH1 on the first active region PR1. A second gate dielectric pattern GI2 may be provided between the gate electrode GE and the first channel pattern CH1 on the second active region PR2. A third gate dielectric pattern GI3 may be provided between the gate electrode GE and the first channel pattern CH1 on the third active region PR3. The first to third gate dielectric patterns GI1, GI2 and GI3 may be substantially the same as described above with reference to FIG. 18 .
A first interlayer insulating layer 110 and a second interlayer insulating layer 120 may be provided on an entire top surface of the substrate 100. Active contacts AC may penetrate the second and first interlayer insulating layers 120 and 110 so as to be connected to the first and second source/drain patterns SD1 and SD2. A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A first metal layer may be provided in the third interlayer insulating layer 130. The first metal layer may include first interconnection lines M1, first vias V1, and second vias V2.
In the semiconductor device according to some embodiments of the inventive concepts, the threshold voltage of the transistor may be adjusted using the interaction of the thickness of the first metal pattern including the P-type work function metal and the concentration of germanium (Ge) of the channel. According to some embodiments of the inventive concepts, a sufficient difference value between the threshold voltages of the transistors may be obtained. According to some embodiments of the inventive concepts, the threshold voltage of the transistor may be adjusted by controlling the impurity of the gate dielectric pattern and/or a kind of the metal of the first metal pattern.
While the inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of the inventive concepts are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.

Claims (10)

What is claimed is:
1. A semiconductor device comprising:
a substrate comprising a PMOSFET region of the substrate;
a first active pattern and a second active pattern on the PMOSFET region;
a plurality of first channel patterns stacked on the first active pattern;
a plurality of second channel patterns stacked on the second active pattern;
a first gate electrode on the plurality of first channel patterns;
a first gate dielectric pattern between the first gate electrode and each of the plurality of first channel patterns;
a second gate electrode on the plurality of second channel patterns; and
a second gate dielectric pattern between the second gate electrode and each of the plurality of second channel patterns,
wherein the plurality of first channel patterns and the plurality of second channel patterns comprise silicon-germanium (SiGe),
wherein a first concentration of germanium (Ge) of the plurality of first channel patterns is different from a second concentration of germanium (Ge) of the plurality of second channel patterns,
wherein the first gate dielectric pattern comprises a first dipole,
wherein the second gate dielectric pattern comprises a second dipole different from the first dipole, and
wherein a concentration of nitrogen (N) in the plurality of first channel patterns decreases from an uppermost one of the plurality of first channel patterns toward a lowermost one of the plurality of first channel patterns.
2. The semiconductor device of claim 1, wherein a threshold voltage of a first transistor on the first active pattern is different from a threshold voltage of a second transistor on the second active pattern.
3. The semiconductor device of claim 1,
wherein the first dipole comprises lanthanum (La), and
wherein the second dipole comprises aluminum (Al).
4. The semiconductor device of claim 1, wherein the first gate electrode is on a top surface, a bottom surface and opposite sidewalls of each of the plurality of first channel patterns.
5. The semiconductor device of claim 4, wherein the second gate electrode is on a top surface, a bottom surface and opposite sidewalls of each of the plurality of second channel patterns.
6. A semiconductor device comprising:
a substrate comprising an active region of the substrate;
an active pattern on the active region;
a plurality of channel patterns stacked on the active pattern; and
a gate electrode on the plurality of channel patterns,
wherein the gate electrode is on a top surface, a bottom surface and opposite sidewalls of each of the plurality of channel patterns,
wherein the plurality of channel patterns comprise silicon-germanium (SiGe),
wherein the plurality of channel patterns further comprise nitrogen (N) as an impurity,
wherein a concentration of germanium (Ge) in the plurality of channel patterns increases from an uppermost one of the plurality of channel patterns toward a lowermost one of the plurality of channel patterns, and
wherein a concentration of nitrogen (N) in the plurality of channel patterns decreases from the uppermost one of the plurality of channel patterns toward the lowermost one of the plurality of channel patterns.
7. The semiconductor device of claim 6, further comprising:
a pair of source/drain patterns on the active pattern,
wherein the plurality of channel patterns are interposed between the pair of source/drain patterns.
8. The semiconductor device of claim 6,
wherein the gate electrode comprises a first metal pattern, a second metal pattern on the first metal pattern, and an electrode pattern on the second metal pattern, and
wherein the first metal pattern is in a space between adjacent ones of the plurality of channel patterns.
9. The semiconductor device of claim 8, wherein the first metal pattern comprises titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium-silicon nitride (TiSiN), titanium-aluminum nitride (TiAIN), tungsten carbonitride (WCN), or molybdenum nitride (MoN).
10. The semiconductor device of claim 6, further comprising:
a gate dielectric pattern between the gate electrode and each of the plurality of channel patterns,
wherein the gate dielectric pattern comprises a dipole selected from lanthanum (La) or aluminum (Al).
US17/831,861 2019-09-17 2022-06-03 Semiconductor device Active US12062661B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/831,861 US12062661B2 (en) 2019-09-17 2022-06-03 Semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2019-0114081 2019-09-17
KR1020190114081A KR102839927B1 (en) 2019-09-17 2019-09-17 Semiconductor device
US16/840,880 US11387236B2 (en) 2019-09-17 2020-04-06 Semiconductor device
US17/831,861 US12062661B2 (en) 2019-09-17 2022-06-03 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US16/840,880 Continuation US11387236B2 (en) 2019-09-17 2020-04-06 Semiconductor device

Publications (2)

Publication Number Publication Date
US20220302115A1 US20220302115A1 (en) 2022-09-22
US12062661B2 true US12062661B2 (en) 2024-08-13

Family

ID=74868642

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/840,880 Active US11387236B2 (en) 2019-09-17 2020-04-06 Semiconductor device
US17/831,861 Active US12062661B2 (en) 2019-09-17 2022-06-03 Semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US16/840,880 Active US11387236B2 (en) 2019-09-17 2020-04-06 Semiconductor device

Country Status (3)

Country Link
US (2) US11387236B2 (en)
KR (1) KR102839927B1 (en)
CN (1) CN112531014A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102437286B1 (en) 2017-11-30 2022-08-30 삼성전자주식회사 Semiconductor device
KR102759937B1 (en) 2019-05-28 2025-02-03 삼성전자주식회사 Semiconductor device and method of fabricating the same
KR20210128534A (en) * 2020-04-16 2021-10-27 삼성전자주식회사 Semiconductor devices
US11791218B2 (en) * 2020-05-20 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dipole patterning for CMOS devices
US12176392B2 (en) 2020-06-25 2024-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with silicide gate fill structure
KR20220151085A (en) * 2021-05-04 2022-11-14 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US20240063064A1 (en) * 2022-08-19 2024-02-22 Applied Materials, Inc. Integrated dipole region for transistor

Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080116487A1 (en) 2006-11-20 2008-05-22 Samsung Electronics Co., Ltd. Methods of fabricating transistors having high carrier mobility and transistors fabricated thereby
US20090050982A1 (en) 2006-05-29 2009-02-26 Interuniversitair Microelektronica Centrum (Imec) Method for Modulating the Effective Work Function
US7514753B2 (en) 2003-12-05 2009-04-07 Kabushiki Kaisha Toshiba Semiconductor device
US8129794B2 (en) 2008-01-25 2012-03-06 Panasonic Corporation Semiconductor device including MISFETs having different threshold voltages
JP4929867B2 (en) 2006-06-19 2012-05-09 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US20120244670A1 (en) * 2011-03-22 2012-09-27 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US8294180B2 (en) 2005-09-28 2012-10-23 Intel Corporation CMOS devices with a single work function gate electrode and method of fabrication
US20120319207A1 (en) 2011-06-17 2012-12-20 Toshiba America Electronic Components, Inc. Semiconductor device with threshold voltage control and method of fabricating the same
US20140299934A1 (en) 2013-04-09 2014-10-09 Samsung Electronics Co., Ltd. Semiconductor Device and Method for Fabricating the Same
US20150187763A1 (en) * 2013-12-27 2015-07-02 Kug-Hwan Kim Semiconductor devices and methods of fabricating semiconductor devices
US20160049400A1 (en) 2014-06-26 2016-02-18 Globalfoundries Inc. Threshold voltage control for mixed-type non-planar semiconductor devices
US20160126343A1 (en) 2014-08-05 2016-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with Source/Drain Cladding
US9362277B2 (en) 2014-02-07 2016-06-07 Globalfounries Inc. FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
US20160218007A1 (en) 2015-01-28 2016-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming semiconductor structure with anti-punch through structure
US20160351569A1 (en) 2015-05-28 2016-12-01 Samsung Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US20160365439A1 (en) 2015-06-15 2016-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical Semiconductor Device Structure and Method of Forming
US20170033106A1 (en) 2015-07-31 2017-02-02 Taiwan Semiconductor Manufacturing Company Ltd. Multi-threshold voltage field effect transistor and manufacturing method thereof
US9728467B2 (en) 2015-09-15 2017-08-08 United Microelectronics Corp. Method for modulating work function of semiconductor device having metal gate structure by gas treatment
US20180308763A1 (en) 2017-04-20 2018-10-25 International Business Machines Corporation Vertical silicon/silicon-germanium transistors with multiple threshold voltages
US10141430B1 (en) 2017-07-27 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures with uniform threshold voltage distribution and method of making the same
US10262905B2 (en) 2013-04-18 2019-04-16 International Business Machines Corporation Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
US20190139828A1 (en) 2017-11-09 2019-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold Voltage Tuning for Fin-Based Integrated Circuit Device
US20200020690A1 (en) * 2018-07-16 2020-01-16 International Business Machines Corporation Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages
US20200044087A1 (en) * 2018-08-06 2020-02-06 Intel Corporation Sub-fin isolation schemes for gate-all-around transistor devices
US20200135913A1 (en) * 2018-10-31 2020-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Finfet device and methods of forming the same
US20200135737A1 (en) 2018-10-30 2020-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
US20200312658A1 (en) 2019-04-01 2020-10-01 Hitachi High-Technologies Corporation Manufacturing method of a semiconductor device and a plasma processing apparatus
US20200373400A1 (en) 2019-05-24 2020-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. Work Function Layers for Transistor Gate Electrodes
US20200411662A1 (en) 2019-06-27 2020-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Fabrication of Field Effect Transistors With Ferroelectric Materials
US20200411691A1 (en) 2017-06-30 2020-12-31 Intel Corporation Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer
US20210028290A1 (en) * 2019-07-26 2021-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Novel Structure for Metal Gate Electrode and Method of Fabrication

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140083736A (en) * 2012-12-26 2014-07-04 에스케이하이닉스 주식회사 Method for forming gate oxide and method for fabricating semiconductor device using the same
KR102312262B1 (en) * 2014-09-02 2021-10-15 삼성전자주식회사 Semiconductor device and method of fabricating the same
KR102395071B1 (en) * 2015-05-14 2022-05-10 삼성전자주식회사 Semiconductor devices including field effect transistors
US20170084454A1 (en) * 2015-09-17 2017-03-23 International Business Machines Corporation Uniform height tall fins with varying silicon germanium concentrations
KR102293127B1 (en) * 2017-06-23 2021-08-26 삼성전자주식회사 Semiconductor device and method for manufacturing the same
KR102465356B1 (en) * 2018-02-09 2022-11-10 삼성전자주식회사 Semiconductor device
KR102452925B1 (en) * 2018-02-23 2022-10-07 삼성전자주식회사 Semiconductor device and method for fabricating the same

Patent Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7514753B2 (en) 2003-12-05 2009-04-07 Kabushiki Kaisha Toshiba Semiconductor device
US8294180B2 (en) 2005-09-28 2012-10-23 Intel Corporation CMOS devices with a single work function gate electrode and method of fabrication
US20090050982A1 (en) 2006-05-29 2009-02-26 Interuniversitair Microelektronica Centrum (Imec) Method for Modulating the Effective Work Function
JP4929867B2 (en) 2006-06-19 2012-05-09 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US20080116487A1 (en) 2006-11-20 2008-05-22 Samsung Electronics Co., Ltd. Methods of fabricating transistors having high carrier mobility and transistors fabricated thereby
US8129794B2 (en) 2008-01-25 2012-03-06 Panasonic Corporation Semiconductor device including MISFETs having different threshold voltages
US20120244670A1 (en) * 2011-03-22 2012-09-27 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
JP2013004968A (en) 2011-06-17 2013-01-07 Toshiba Corp Semiconductor device and manufacturing method of the same
US20120319207A1 (en) 2011-06-17 2012-12-20 Toshiba America Electronic Components, Inc. Semiconductor device with threshold voltage control and method of fabricating the same
US20140299934A1 (en) 2013-04-09 2014-10-09 Samsung Electronics Co., Ltd. Semiconductor Device and Method for Fabricating the Same
US10262905B2 (en) 2013-04-18 2019-04-16 International Business Machines Corporation Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
US20150187763A1 (en) * 2013-12-27 2015-07-02 Kug-Hwan Kim Semiconductor devices and methods of fabricating semiconductor devices
US9362277B2 (en) 2014-02-07 2016-06-07 Globalfounries Inc. FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
US20160049400A1 (en) 2014-06-26 2016-02-18 Globalfoundries Inc. Threshold voltage control for mixed-type non-planar semiconductor devices
US20160126343A1 (en) 2014-08-05 2016-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with Source/Drain Cladding
KR101735204B1 (en) 2015-01-28 2017-05-12 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Barrier layer above anti-punch through (apt) implant region to improve mobility of channel region of fin field effect transistor (finfet) device structure
US20160218007A1 (en) 2015-01-28 2016-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming semiconductor structure with anti-punch through structure
KR20160139814A (en) 2015-05-28 2016-12-07 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US20160351569A1 (en) 2015-05-28 2016-12-01 Samsung Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US20160365439A1 (en) 2015-06-15 2016-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical Semiconductor Device Structure and Method of Forming
US20170033106A1 (en) 2015-07-31 2017-02-02 Taiwan Semiconductor Manufacturing Company Ltd. Multi-threshold voltage field effect transistor and manufacturing method thereof
US9728467B2 (en) 2015-09-15 2017-08-08 United Microelectronics Corp. Method for modulating work function of semiconductor device having metal gate structure by gas treatment
US20180308763A1 (en) 2017-04-20 2018-10-25 International Business Machines Corporation Vertical silicon/silicon-germanium transistors with multiple threshold voltages
US20200411691A1 (en) 2017-06-30 2020-12-31 Intel Corporation Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer
US10141430B1 (en) 2017-07-27 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures with uniform threshold voltage distribution and method of making the same
US20190139828A1 (en) 2017-11-09 2019-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold Voltage Tuning for Fin-Based Integrated Circuit Device
US20200020690A1 (en) * 2018-07-16 2020-01-16 International Business Machines Corporation Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages
US20200044087A1 (en) * 2018-08-06 2020-02-06 Intel Corporation Sub-fin isolation schemes for gate-all-around transistor devices
US20200135737A1 (en) 2018-10-30 2020-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
US20200135913A1 (en) * 2018-10-31 2020-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Finfet device and methods of forming the same
US20200312658A1 (en) 2019-04-01 2020-10-01 Hitachi High-Technologies Corporation Manufacturing method of a semiconductor device and a plasma processing apparatus
US20200373400A1 (en) 2019-05-24 2020-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. Work Function Layers for Transistor Gate Electrodes
US20200411662A1 (en) 2019-06-27 2020-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Fabrication of Field Effect Transistors With Ferroelectric Materials
US20210028290A1 (en) * 2019-07-26 2021-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Novel Structure for Metal Gate Electrode and Method of Fabrication

Also Published As

Publication number Publication date
US11387236B2 (en) 2022-07-12
CN112531014A (en) 2021-03-19
US20220302115A1 (en) 2022-09-22
KR102839927B1 (en) 2025-07-30
KR20210033102A (en) 2021-03-26
US20210082917A1 (en) 2021-03-18

Similar Documents

Publication Publication Date Title
US12062661B2 (en) Semiconductor device
US11610975B2 (en) Semiconductor devices having multiple barrier patterns
US11569350B2 (en) Semiconductor device
US11837645B2 (en) Method of manufacturing a semiconductor device
US10950709B2 (en) Semiconductor device
US11961839B2 (en) Semiconductor device
US11217677B2 (en) Semiconductor device and method of fabricating the same
US11881509B2 (en) Semiconductor device
US12432992B2 (en) Semiconductor device including source/drain patterns
US20210408241A1 (en) Method for manufacturing a semiconductor device
KR102554708B1 (en) Semiconductor device
US20240347597A1 (en) Semiconductor device
US20240105789A1 (en) Semiconductor device including a field effect transistor
US20240274665A1 (en) Semiconductor device and method of fabricating the same
KR102866523B1 (en) Semiconductor device
US20240128321A1 (en) Semiconductor device including blocking layer and source/drain structure
US20230402523A1 (en) Semiconductor device
US20240162322A1 (en) Semiconductor device and method of fabricating the same
US20240021734A1 (en) Semiconductor device and method of fabricating the same

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

ZAAA Notice of allowance and fees due

Free format text: ORIGINAL CODE: NOA

ZAAB Notice of allowance mailed

Free format text: ORIGINAL CODE: MN/=.

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE