US12015053B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US12015053B2
US12015053B2 US17/717,724 US202217717724A US12015053B2 US 12015053 B2 US12015053 B2 US 12015053B2 US 202217717724 A US202217717724 A US 202217717724A US 12015053 B2 US12015053 B2 US 12015053B2
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film
semiconductor substrate
dielectric constant
insulating film
semiconductor device
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Makoto Koshimizu
Yasutaka Nakashiba
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H01L29/0607—
    • H01L29/7823—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H01L29/66681—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

  • the present invention relates to a semiconductor device and, for example, to techniques valid for application to semiconductor device including laterally diffused MOSFET (LDMOSFET: Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor).
  • LDMOSFET Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor
  • LDMOSFET employing a step insulating film can suppress an increase of off-leakage current as compared with LDMOSFET employing an STI structure, by replacing the STI structure with a step insulating film.
  • a semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, and a high dielectric constant film having a higher dielectric constant than silicon and in contact with the step insulating film.
  • the performance of semiconductor device including LDMOSFET can be improved.
  • FIG. 1 is a flowchart for explaining the mechanism of increase of the on-resistance of LDMOSFET when hot carriers are injected into the step insulating film.
  • FIG. 2 is a diagram explaining the basic concept in the present embodiment.
  • FIG. 3 is a diagram schematically showing a state in which electrons flow in LDMOSFET where the potential control film is not existed.
  • FIG. 4 is a diagram schematically showing a state in which electrons flow in LDMOSFET in which the basic concept of providing a potential control film is embodied.
  • FIG. 5 is a cross-sectional view showing the device structure of LDMOSFET in the present embodiment.
  • FIG. 6 A is a figure schematically showing a band structure at the surface of the n-type resurf layer when, for example, a gate dielectric film made of a silicon oxide film is formed on the n-type resurf layer.
  • FIG. 63 is a figure schematically showing a band structure at the surface of the n-type resurf layer when a gate dielectric film made of a silicon oxide film and a high dielectric constant film are formed on the n-type resurf layer.
  • FIGS. 7 A and 7 B are diagrams schematically showing band structures in which the Fermi levels of FIGS. 6 A and 6 B are adjusted to the same energy level.
  • FIG. 8 is a cross-sectional view showing a manufacturing process of semiconductor device in the present embodiment.
  • FIG. 9 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 8 .
  • FIG. 10 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 9 .
  • FIG. 11 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 10 .
  • FIG. 12 is a cross-sectional view showing the device structure of LDMOSFET in the first modified example.
  • FIG. 13 is a cross-sectional view showing the manufacturing process of semiconductor device in the first modified example.
  • FIG. 14 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 13 .
  • FIG. 15 is a cross-sectional view showing the device structure of LDMOSFET in the second modified example.
  • FIG. 16 is a cross-sectional view showing the manufacturing process of semiconductor device in the second modified example.
  • FIG. 17 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 16 .
  • FIG. 18 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 17 .
  • FIG. 19 is a cross-sectional view showing the device structure of LDMOSFET in the third modified example.
  • FIG. 20 is a cross-sectional view showing the manufacturing process of semiconductor device in the third modified example.
  • FIG. 21 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 20 .
  • FIG. 22 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 21 .
  • FIG. 23 is a cross-sectional view showing the device structure of LDMOSFET in the fourth modified example.
  • FIG. 24 cross-sectional view showing the manufacturing process of semiconductor device in the fourth modified example.
  • FIG. 25 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 24 .
  • FIG. 26 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 25 .
  • the present inventors have found a new room for improvement regarding the on-resistance is increased by hot carriers are injected into the step insulating film in LDMOSFET employing the step insulating film. Therefore, the mechanism that the on-resistance of LDMOSFET is increased when hot carriers are injected into the step insulating film, will be described.
  • FIG. 1 is a flowchart for explaining the mechanism of increase of the on-resistance of LDMOSFET when hot carriers are injected into the step insulating film.
  • LDMOSFET turns on by applying a gate voltage above the threshold voltage to the gate electrode in a state that a high voltage applied between the source and drain of LDMOSFET (S 101 ). This causes electrons to flow from the source through the channel to the drain. At this time, hot carriers are generated as a result of electrons accelerated by the high voltage applied between the source and drain (S 102 ). In particular, since the corner portion vicinity of the step insulating film is a high electric field, the hot carriers generated by accelerating with the high electric field overcomes the potential barrier by the step insulating film and the hot carriers are injected into the step insulating film (S 103 ).
  • step insulating film S 104
  • step insulating film is charged negatively (minus)
  • depletion phenomena occurs on the surface of the n-type resurf layer in contact with the step insulating film (S 105 ).
  • this depletion region functions as an insulating region, electrons flowing from the source through the channel to the drain will be bypassed so as to avoid the depletion region formed on the surface of the re-type resurf layer (S 106 ).
  • the on-resistance of LDMOSFET is increased by the “factor 1” of depletion of the n-type resurf layer caused by hot carriers are injected into the step insulating film, and by the “factor 2” that the distance becomes longer because the path through which electrons flow is alternate path (S 107 ).
  • the basic concept of the present embodiment is that a potential control film is provided in LDMOSFET to form a potential barrier for electrons on the surface of the semiconductor substrate located under the step insulating film.
  • This allows the electron-flowing current path to be shifted from “the surface of the semiconductor substrate” to “the inner part of the semiconductor substrate (inside the bulk)” by the potential barrier formed on the surface of the semiconductor substrate located under the step insulating film. That is, because the potential barrier moves electrons away from the surface of the semiconductor substrate, the current path through which the electrons flow shifts from “the surface of the semiconductor substrate” to “the inner part of the semiconductor substrate (inside the bulk)”.
  • FIG. 2 is a diagram for explaining the basic concept in the present embodiment.
  • LDMOSEFT 100 has a semiconductor substrate 1 .
  • a p-type resurf layer 10 and an n-type resurf layer 11 which formed on the p-type resurf layer 10 are formed.
  • the n-type resurf layer 11 is also referred to as an n-type drift layer.
  • a gate dielectric film 12 is formed on the semiconductor substrate 1 , and a potential control film 13 is formed on the gate dielectric film 12 .
  • the potential control film 13 is in contact with the step insulating film 14 , and a field plate portion 15 in contact with the step insulating film 14 and a gate electrode 16 in contact with the potential control film 13 are integrally formed.
  • a drain region 17 formed of an n-type semiconductor region is formed in the n-type resurf layer 11 so as to be aligned with the step insulating film 14 .
  • a p-type body region 18 is formed in the semiconductor substrate 1 , and a source region formed of an n-type semiconductor region and a body contact region 20 formed of a p-type semiconductor region are formed so as to be included in the p-type body region 18 .
  • the basic concept in the present embodiment is to form a potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 by the potential control film 13 provided in LDMOSFET 100 configured as described above. Specifically, as shown in the right part of FIG. 2 , the potential at the surface of the semiconductor substrate 1 is shifted from the solid line A to the broken line B by the presence of the potential control film 13 . In this situation, the potential at the surface of the semiconductor substrate 1 is shifted toward high energy when viewed from the electron. This means that the repulsive force which electrons receive from the potential shifted toward high energy at the surface of the semiconductor substrate 1 is increased.
  • FIG. 3 is a diagram schematically showing a state in which electrons flow in a LDMOSFET where the potential control film 13 is not provided.
  • FIG. 4 is a diagram schematically showing a state in which electrons flow in a LDMOSFET in which the basic concept of providing the potential control film 13 is embodied.
  • the current path through which the electrons flow shifts from “the surface of the semiconductor substrate 1 ” to “the inner part of the semiconductor substrate 1 (inside the bulk).”
  • the current path through which the electrons flow is moved away from the interface between the step insulating film 14 and the semiconductor substrate 1 , so that the hot carriers are suppressed from being injected into the step insulating film 14 . Therefore, in LDMOSFET shown FIG. 4 , it is possible co suppress the increase of the on-resistance caused by the injection of hot carriers into the step insulating film 14 .
  • FIG. 5 is a cross-sectional view showing the schematic device structure of LDMOSFET 100 A.
  • LDMOSFET has, for example, a semiconductor substrate 1 made of silicon.
  • the semiconductor substrate 1 has a p-type resurf layer 10 , and an n-type resurf layer 11 formed on the p-type resurf layer 10 (n-type drift layer).
  • a gate dielectric film 12 formed of, for example, a silicon oxide film is formed on the semiconductor substrate 1 .
  • a gate electrode 16 formed of, for example, an n-type polysilicon film is formed on the gate dielectric film 12 .
  • the gate electrode 16 formed “on” the gate dielectric film 12 is used in a broad intention including not only the configuration of the gate electrode 16 formed directly above the gate dielectric film 12 , but also, for example as shown in FIG. 5 the configuration in which a high dielectric constant film 30 is formed on the gate dielectric film 12 and the gate electrode 16 is formed on the high dielectric constant film 30 .
  • a high dielectric constant film 30 is formed on the gate dielectric film 12 , the gate electrode 16 is formed on the high dielectric constant film 30 .
  • the “high dielectric constant film 30 ” in this specification is defined as a film having a dielectric constant higher than that of silicon.
  • the high dielectric constant film 30 includes a “first portion” sandwiched between the gate dielectric film 12 and the gate electrode 16 , and a “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12 .
  • LDMOSFET 100 A includes a field plate portion 5 which is integrally formed with the gate electrode 16 , and a step insulating 14 in contact with the field plate portion 15 .
  • the step insulating film 14 is formed of, for example, a silicon oxide film.
  • the high dielectric constant film 30 is in contact with the step insulating film 14 .
  • a drain region 17 formed of an n-type semiconductor region aligned with the step insulating film 14 is formed in the n-type resurf layer 11 .
  • the p-type body region 18 formed of a p-type semiconductor region is formed in the semiconductor substrate 1 , and in the p-type body region 18 , the source region 19 which is an n-type semiconductor region and the body contact region 20 which is a p-type semiconductor region, are formed.
  • the source region 19 and the body contact region 20 are electrically connected to each other, and, for example, a ground potential of 0 V is supplied thereto. As a result, the ground potential is also supplied to the p-type body region 18 electrically connected to the body contact region 20 .
  • a positive potential is supplied to the drain region 17 .
  • the high dielectric constant film 30 shown in FIG. 5 is an example of the potential control film 13 shown in FIG. 2 . That is, the high dielectric constant film 30 functions as the potential control film 13 for forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 . More specifically, as will be described later, the high dielectric constant film 30 has a function of forming a potential barrier on the surface by shifting the Fermi level on the surface of the semiconductor substrate 1 located under the step insulating film 14 .
  • the high dielectric constant film 30 having such a function includes, for example, any of HfSiO, HfSiON, HfAlON, Y 2 O 3 or Al 2 O 3 .
  • LDMOSFET 100 A is configured.
  • LDMOSFET 100 A In a state of supplying a positive potential to the drain region 17 while supplying a ground potential to the source region 19 , a gate voltage above the threshold voltage is applied to the gate electrode 16 . Then, the inversion layer (n-type layer) serving as a channel layer is formed on the surface of the p-type body region 18 located under the gate electrode 16 . Thus, electrons flow in the path of the source region 19 , channel layer (inversion layer), n-type resurf layer 11 and drain region 17 in this order. In this way, LDMOSFET 100 A is operated in on state.
  • LDMOSFET 100 A the off-operation of LDMOSFET 100 A will be described.
  • a smaller gate voltage e.g., 0V
  • the inversion layer formed on the surface of the p-type body region 18 disappears.
  • the path of the flow of electrons from the source region 19 to the drain region 17 is blocked. In this way, LDMOSFET 100 A is turned off.
  • the feature point in the present embodiment is that, for example, as shown in FIG. 5 , a high dielectric constant film 30 is employed as a potential control film 13 for forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 .
  • the feature point in the present embodiment is that a potential barrier is formed on the surface of the semiconductor substrate 1 located under the step insulating film 14 by the high dielectric constant film 30 , and that the current path through which electrons flow is shifted from “the surface of the semiconductor substrate” to “the inner part of the semiconductor substrate (inside the bulk)” by this potential barrier.
  • the path through which electrons flow can be moved away from the interface between the step insulating film 14 and the semiconductor substrate 1 , thereby suppressing hot carriers from being injected into the step insulating film 14 .
  • the high dielectric constant film 30 functions as the potential control film 13 .
  • FIG. 6 A is a diagram schematically showing a band structure at the surface of the n-type resurf layer 11 when the gate dielectric film 12 formed of, for example, a silicon oxide film is formed on the n-type resurf layer 11 .
  • the n-type resurf layer 11 is the n-type semiconductor layer, the Fermi level Ef is present in the vicinity of the lower end of conduction band.
  • the gate dielectric film 12 formed of a silicon oxide film but also a high dielectric constant film 30 including, for example, HfSiO, HfSiON, HfAlON, Y2O3, or Al2O3 or the like in the constituent material and having a dielectric constant higher than that of silicon on this gate dielectric film 12 are formed, Fermi level Ef is moved away from the lower end of the conduction band, so-called “Fermi level pinning” phenomena occurs.
  • FIG. 6 B is a diagram schematically showing a band structure on the surface of the n-type resurf layer 11 when the gate dielectric film 12 formed of a silicon oxide film and the high dielectric constant film 30 are formed on the n-type resurf layer 11 .
  • the n-type resurf layer 11 is n-type semiconductor layer
  • this “Fermi-level pinning” is used to form a potential barrier on the surface of the semiconductor substrate 1 located under the step insulating film 14 . This point will be described below.
  • FIG. 7 A is a diagram schematically showing a band structure at the surface of the n-type resurf layer 11 when, for example, a gate dielectric film 12 formed of a silicon oxide film is formed on the n-type resurf layer 11
  • FIG. 75 is a diagram schematically showing a band structure at the surface of the n-type resurf layer 11 when a gate dielectric film 12 formed of a silicon oxide film and high dielectric constant film 30 are formed on the n-type resurf layer 11 .
  • the feature point in the present embodiment is that the potential barrier is formed on the surface of the semiconductor substrate 1 located under the step insulating film 14 by utilizing the phenomena “Fermi level pinning” caused by the high dielectric constant film 30 .
  • the path through which electrons flow can be moved away from the interface between the step insulating film 14 and the semiconductor substrate 1 by the repulsive force caused by the potential barrier. Therefore, according to the present embodiment, it is possible to suppress injection of hot carriers into the step insulating film 14 , and as a result, it is possible to suppress an increase of on-resistance of LDMOSFET caused by injection of hot carriers into the step insulating film 14 .
  • a semiconductor substrate 1 made of silicon is prepared. After a sacrificial silicon oxide film. 35 is formed on the semiconductor substrate 1 , a p-type resurf layer 10 and an n-type resurf layer 11 are formed in the semiconductor substrate 1 by ion implantation. Specifically, the p-type resurf layer 10 is formed by implanting boron as a p-type impurity (acceptor) into the semiconductor substrate 1 . On the other hand, the n-type resurf layer 11 is formed by implanting phosphorus (P), which is an n-type impurity (donor), into the semiconductor substrate 1 .
  • P phosphorus
  • a gate dielectric film 12 formed of a silicon oxide film is formed on the semiconductor substrate 1 by using, for example, a thermal oxidation method.
  • a high dielectric constant film 30 formed by using an ALD (Atomic Layer Deposition) method or a CVD (Chemical Vapor Deposition) method.
  • ALD Atomic Layer Deposition
  • CVD Chemical Vapor Deposition
  • the high dielectric constant film 30 for example, HfSiO film, HfSiON film, HfAlON film, Y 2 O 3 film, and Al 2 O 3 film can be mentioned.
  • a silicon oxide film 14 a is formed on the high dielectric constant film 30 .
  • the silicon oxide film 14 a is patterned by using a photolithography technique and an etching technique to form a step insulating film 14 .
  • a polysilicon film is formed on the high dielectric constant film 30 so as to cover the step insulating film 14 by using, for example, a CVD method.
  • the polysilicon film is patterned by using photolithography and etching techniques.
  • a gate electrode 16 and the field plate portion 15 which are formed of a polysilicon film are integrally formed.
  • boron which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form a p-type body region 18 .
  • phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form a drain region 17 and a source region 19
  • boron which is a p-type impurity
  • a semiconductor device including LDMOSFET 100 A is manufactured.
  • the high dielectric constant film 30 includes a “first portion” sandwiched between the gate dielectric film 12 and the gate electrode 16 , and a “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12 .
  • the “second portion” of the high dielectric constant film 30 is important from the viewpoint of forming the potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 .
  • the “first portion” of the high dielectric constant film 30 configures a stacked film with the gate dielectric film 12 , and this stacked film influences threshold voltage for forming an inversion layer. That is, the “first portion” of the high dielectric constant film 30 is not essential from the viewpoint of forming the potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 . Rather, there is a disadvantage that the threshold voltage for forming the inversion layer is increased the “Fermi level pinning” caused by the “first portion” of the high dielectric constant film 30 .
  • FIG. 12 is a cross-sectional view schematically showing the device structure of LDMOSFET 1003 in the present first modified example.
  • the high dielectric constant film 30 is composed of only the “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12 .
  • the steps shown in FIGS. 8 and 9 are the same as in the above embodiment.
  • the high dielectric constant film 30 exposed from the step insulating film 14 is removed by using an etching technique.
  • the high dielectric constant film 30 composed of only the “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12 can be formed.
  • a polysilicon film is formed on the gate dielectric film 12 so as to cover the step insulating film 14 by using, for example, a CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 which are formed of a polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body regions 18 .
  • phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19
  • boron which is a p-type impurity
  • the interlayer insulating film forming step to form the interlayer insulating films and wiring forming step to form the wirings, it is possible to manufacture semiconductor device including LDMOSFET 100 B.
  • FIG. 15 is a cross-sectional view schematically showing the device structure of LDMOSFET 1000 in the present second modified example.
  • the feature point in the second modified example is that a high dielectric constant film 30 is formed over the exposed gate dielectric film 12 , the gate electrode 16 , the field plate portion 15 , and the exposed step insulating film 14 .
  • the film thickness of the high dielectric constant film 30 in the present second modified example is thicker than the film thickness of the high dielectric constant film 30 in the above embodiment and the first modified example.
  • LDMOSFET 100 C in the present second modified example is configured.
  • the step shown in FIG. 8 is the same as the above embodiment.
  • a silicon oxide film is formed on the semiconductor substrate 1 by using, for example, a CVD method
  • the silicon oxide film is patterned by using a photolithography technique and an etch technique to form a step insulating film 14 .
  • a gate dielectric film 12 is formed on the exposed surface of the semiconductor substrate 1 by using, for example, a thermal oxidization method.
  • a polysilicon film is formed on the gate dielectric film 12 and the step insulating film 14 by using, for example, the CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 formed of the polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body region 18 .
  • phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19
  • boron which is a p-type impurity
  • a high dielectric constant film 30 is formed so as to cover the exposed gate dielectric film 12 , the gate electrode 16 , the field plate portion 15 , and the exposed step insulating film 14 .
  • the interlayer insulating film forming step to form interlayer insulating films and wiring forming step to form wirings, it is possible to manufacture a semiconductor device including LDMOSFET 100 C.
  • the present second modified example since the step of patterning the high dielectric constant film 30 is not necessary as in the above-mentioned first modified example, it is possible to suppress an increase of threshold voltage for forming inversion layer without adding a patterning step while forming potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 .
  • FIG. 19 is a cross-sectional view schematically showing the device structure of LDMOSFET 100 D in the present third modified example.
  • the feature point of the present third modified example is that, as it is premise that the step insulating film 4 has the “contact portion” in contact with the field plate portion 15 and the “non-contact portion” projecting from the field plate portion 15 , the “non-contact portion” is configured of the “thin film portion” in which the concave portion is formed and the “thick film portion” which is thicker than the “thin film portion”, and that the high dielectric constant film 30 is formed over the exposed gate dielectric film 12 , the gate electrode 16 , the field plate portion 15 , and the exposed step insulating film 14 .
  • the film thickness of the “thick film portion” is set to “t1” and the film thickness of the “thin film portion” is set to “t2”, the relationship of t2 ⁇ t1 is established.
  • a concave portion 40 is formed in the step insulating film 14 by using a photolithography technique and an etching technique.
  • a gate dielectric film 12 is formed on the exposed surface of the semiconductor substrate 1 by using, for example, a thermal oxidization method.
  • a polysilicon film is formed on the gate dielectric film and the step insulating film 14 by using, for example, the CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 formed of the polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body regions 18 .
  • phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19
  • boron which is a p type impurity, is implanted into the semiconductor substrate 1 to form the body contact region 20 .
  • a high dielectric constant film 30 is formed so as to cover the exposed gate dielectric film 12 , the gate electrode 16 , the field plate portion 15 , and the exposed step insulating film 14 .
  • the interlayer insulating film forming step to form interlayer insulating films and wiring forming step to form wirings, it is possible to manufacture a semiconductor device including LDMOSFET 100 D.
  • the “thin film portion” in which the concave portion is formed is formed in the step insulating film 14 , and the high dielectric constant film 30 is also formed inside the concave portion of the “thin film portion”.
  • the advantage that can reduce the film thickness of the high dielectric constant film 30 than second modified example is obtained.
  • FIG. 23 is a cross-sectional view schematically showing the device structure of LDMOSFET 100 E in the present fourth modified example.
  • the feature point of the present fourth modified example is that the film thickness “t2” of the “thin film portion” including the concave portion provided in the step insulating film 14 is equal to the film thickness of the gate dielectric film 12 .
  • a concave portion 40 is formed in the step insulating film 14 by using a photolithography technique and an etching technique. At this time, the concave portion 40 is formed such that the bottom of the concave portion 40 reaches the surface of the semiconductor substrate 1 .
  • a gate dielectric film 12 is formed on the exposed surface of the semiconductor substrate 1 by using, for example, a thermal oxidization method.
  • the gate dielectric film 12 is also formed on the surface of the semiconductor substrate 1 exposed at the bottom of the concave portion 40 .
  • the film thickness of the gate dielectric film 12 formed at the bottom of the concave portion 40 is equal to the film thickness of the gate dielectric film 12 formed on the other surface of the semiconductor substrate 1 .
  • a polysilicon film is formed on the gate dielectric film 12 and the step insulating film 14 by using, for example, the CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 formed of the polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body regions 18 .
  • phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19
  • boron which is a p-type impurity
  • a high dielectric constant film 30 is formed so as to cover the exposed gate dielectric film 12 , the gate electrode 16 , the field plate portion 15 , and the exposed step insulating film 14 .
  • the interlayer insulating film forming step to form interlayer insulating films and wiring forming step to form wirings, it is possible to manufacture a semiconductor device including LDMOSFET 100 E.
  • the etching amount of the concave portion 40 needs to be adjusted in the step of forming the concave portion 40 (refer to FIG. 20 ).
  • the film thickness “t2” of the “thin film portion” is made equal to the film thickness of the gate dielectric film 12 , for example, as shown in FIG.
  • the concave portion 40 in the step of forming the concave portion 40 , may be formed so as to expose the semiconductor substrate 1 at the bottom of the concave portion 40 without finely adjusting the etching amount of the concave portion 40 . This is because “over etching” is also allowed, the advantage that the etching step for forming the concave portion is facilitated is obtained.
  • the film thickness “t2” of the “thin film portion” can be automatically made equal to the film thickness of the gate dielectric film 12 of the other regions.
  • the embodiment includes the following embodiments.
  • a method of manufacturing a semiconductor device includes:
  • a method of manufacturing a semiconductor device includes:
  • a method of manufacturing a semiconductor device includes:
  • a method of manufacturing a semiconductor device includes:
  • a method of manufacturing a semiconductor device includes:

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Abstract

A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
The disclosure of Japanese Patent Application No. 2021-085964 filed on May 21, 2021, including the specification, drawings and abstract is incorporated herein by reference in its entirety.
BACKGROUND
The present invention relates to a semiconductor device and, for example, to techniques valid for application to semiconductor device including laterally diffused MOSFET (LDMOSFET: Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor).
There are disclosed techniques listed below.
    • [Non-Patent Document 1] Keita Takahashi, Kanako Komatsu, Toshihiro Sakamoto, Koji Kimura and Fumitomo Matsuoka “Hot carrier Induced Off-state Leakage Current Increase of LDMOS and Approach to Overcome the Phenomenon”, Proceedings of the 30th International Symposium on Power Semiconductor Devices & ICs May 13-17, 2018, Chicago, USA
    • Non-Patent Document 1 discloses, according to LDMOSFET of employing a step insulating film (Step-OX), that an increase of off-leakage current due to hot carrier injection causing an increase of power consumption and failure of the circuit operation can be suppressed.
SUMMARY
As described in the above-described Non-Patent Document 1, LDMOSFET employing a step insulating film can suppress an increase of off-leakage current as compared with LDMOSFET employing an STI structure, by replacing the STI structure with a step insulating film.
However, even in LDMOSFET of employing a step insulating film, since it cannot be sufficiently suppressed hot carrier injection into the step insulating film, there is room for improvement from the viewpoint of improving the performance of semiconductor device including LDMOSFET.
A semiconductor device according to one embodiment includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, and a high dielectric constant film having a higher dielectric constant than silicon and in contact with the step insulating film.
According to one embodiment, the performance of semiconductor device including LDMOSFET can be improved.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flowchart for explaining the mechanism of increase of the on-resistance of LDMOSFET when hot carriers are injected into the step insulating film.
FIG. 2 is a diagram explaining the basic concept in the present embodiment.
FIG. 3 is a diagram schematically showing a state in which electrons flow in LDMOSFET where the potential control film is not existed.
FIG. 4 is a diagram schematically showing a state in which electrons flow in LDMOSFET in which the basic concept of providing a potential control film is embodied.
FIG. 5 is a cross-sectional view showing the device structure of LDMOSFET in the present embodiment.
FIG. 6A is a figure schematically showing a band structure at the surface of the n-type resurf layer when, for example, a gate dielectric film made of a silicon oxide film is formed on the n-type resurf layer.
FIG. 63 is a figure schematically showing a band structure at the surface of the n-type resurf layer when a gate dielectric film made of a silicon oxide film and a high dielectric constant film are formed on the n-type resurf layer.
FIGS. 7A and 7B are diagrams schematically showing band structures in which the Fermi levels of FIGS. 6A and 6B are adjusted to the same energy level.
FIG. 8 is a cross-sectional view showing a manufacturing process of semiconductor device in the present embodiment.
FIG. 9 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 8 .
FIG. 10 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 9 .
FIG. 11 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 10 .
FIG. 12 is a cross-sectional view showing the device structure of LDMOSFET in the first modified example.
FIG. 13 is a cross-sectional view showing the manufacturing process of semiconductor device in the first modified example.
FIG. 14 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 13 .
FIG. 15 is a cross-sectional view showing the device structure of LDMOSFET in the second modified example.
FIG. 16 is a cross-sectional view showing the manufacturing process of semiconductor device in the second modified example.
FIG. 17 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 16 .
FIG. 18 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 17 .
FIG. 19 is a cross-sectional view showing the device structure of LDMOSFET in the third modified example.
FIG. 20 is a cross-sectional view showing the manufacturing process of semiconductor device in the third modified example.
FIG. 21 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 20 .
FIG. 22 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 21 .
FIG. 23 is a cross-sectional view showing the device structure of LDMOSFET in the fourth modified example.
FIG. 24 cross-sectional view showing the manufacturing process of semiconductor device in the fourth modified example.
FIG. 25 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 24 .
FIG. 26 is a cross-sectional view showing the manufacturing process of semiconductor device following FIG. 25 .
 DETAILED DESCRIPTION
In all the drawings for explaining the embodiments, the same members are denoted by the same reference numerals in principle, and repetitive descriptions thereof are omitted. Note that even plan view may be hatched for the sake of clarity.
Study of Improvement
The present inventors have found a new room for improvement regarding the on-resistance is increased by hot carriers are injected into the step insulating film in LDMOSFET employing the step insulating film. Therefore, the mechanism that the on-resistance of LDMOSFET is increased when hot carriers are injected into the step insulating film, will be described.
FIG. 1 is a flowchart for explaining the mechanism of increase of the on-resistance of LDMOSFET when hot carriers are injected into the step insulating film.
In FIG. 1 , first, LDMOSFET turns on by applying a gate voltage above the threshold voltage to the gate electrode in a state that a high voltage applied between the source and drain of LDMOSFET (S101). This causes electrons to flow from the source through the channel to the drain. At this time, hot carriers are generated as a result of electrons accelerated by the high voltage applied between the source and drain (S102). In particular, since the corner portion vicinity of the step insulating film is a high electric field, the hot carriers generated by accelerating with the high electric field overcomes the potential barrier by the step insulating film and the hot carriers are injected into the step insulating film (S103). Thus, a fixed charge (negative charge) is trapped in the step insulating film (S104). Consequently, since the step insulating film is charged negatively (minus), depletion phenomena occurs on the surface of the n-type resurf layer in contact with the step insulating film (S105). Then, since this depletion region functions as an insulating region, electrons flowing from the source through the channel to the drain will be bypassed so as to avoid the depletion region formed on the surface of the re-type resurf layer (S106).
As described above, the on-resistance of LDMOSFET is increased by the “factor 1” of depletion of the n-type resurf layer caused by hot carriers are injected into the step insulating film, and by the “factor 2” that the distance becomes longer because the path through which electrons flow is alternate path (S107). By such a mechanism, in LDMOSFET of employing a step insulating film, by hot carriers are injected into the step insulating film, it becomes apparent room for improvement that the on-resistance is increased.
Therefore, in the present embodiment, it is devised for room for improvement regarding the increase of on-resistance that exists in above described. LDMOSFET employing the step insulating film. Hereinafter, the technical idea in the present embodiment to which the devise is applied will be described.
Basic Concept of Present Embodiment
The basic concept of the present embodiment is that a potential control film is provided in LDMOSFET to form a potential barrier for electrons on the surface of the semiconductor substrate located under the step insulating film. This allows the electron-flowing current path to be shifted from “the surface of the semiconductor substrate” to “the inner part of the semiconductor substrate (inside the bulk)” by the potential barrier formed on the surface of the semiconductor substrate located under the step insulating film. That is, because the potential barrier moves electrons away from the surface of the semiconductor substrate, the current path through which the electrons flow shifts from “the surface of the semiconductor substrate” to “the inner part of the semiconductor substrate (inside the bulk)”. This means that the current path through which the electrons flow moves away from the interface between the step insulating film and the semiconductor substrate, thereby suppressing the injection of hot carriers into the step insulating film. Consequently, according to the basic concept, it is possible to suppress the increase of the on-resistance of LDMOSFET caused by the injection of hot carriers into the step insulating film.
Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 2 is a diagram for explaining the basic concept in the present embodiment. In FIG. 2 , LDMOSEFT 100 has a semiconductor substrate 1. In the semiconductor substrate 1, a p-type resurf layer 10 and an n-type resurf layer 11 which formed on the p-type resurf layer 10 are formed. The n-type resurf layer 11 is also referred to as an n-type drift layer. A gate dielectric film 12 is formed on the semiconductor substrate 1, and a potential control film 13 is formed on the gate dielectric film 12. The potential control film 13 is in contact with the step insulating film 14, and a field plate portion 15 in contact with the step insulating film 14 and a gate electrode 16 in contact with the potential control film 13 are integrally formed. In addition, a drain region 17 formed of an n-type semiconductor region is formed in the n-type resurf layer 11 so as to be aligned with the step insulating film 14. Furthermore, a p-type body region 18 is formed in the semiconductor substrate 1, and a source region formed of an n-type semiconductor region and a body contact region 20 formed of a p-type semiconductor region are formed so as to be included in the p-type body region 18.
The basic concept in the present embodiment is to form a potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 by the potential control film 13 provided in LDMOSFET 100 configured as described above. Specifically, as shown in the right part of FIG. 2 , the potential at the surface of the semiconductor substrate 1 is shifted from the solid line A to the broken line B by the presence of the potential control film 13. In this situation, the potential at the surface of the semiconductor substrate 1 is shifted toward high energy when viewed from the electron. This means that the repulsive force which electrons receive from the potential shifted toward high energy at the surface of the semiconductor substrate 1 is increased. This causes the current path through which the electrons flow to shift from “the surface of the semiconductor substrate 1” to “the inner part of the semiconductor substrate 1 (inside the bulk).” This means that the current path through which the electrons flow moves away from the interface between the step insulating film and the semiconductor substrate, thereby suppressing the injection of hot carriers into the step insulating film.
For example, FIG. 3 is a diagram schematically showing a state in which electrons flow in a LDMOSFET where the potential control film 13 is not provided.
As shown in FIG. 3 , electrons flow from the source region 19 through the channel formed on the surface of the p-type body region 18 toward the drain region 17. At this time, as shown in FIG. 3 , hot carriers generated by the high voltage applied between the drain region 17 and the source region 19 are injected into the step insulating film 14 by the high electric field in the vicinity of the corner portion of the step insulating film 14. As a result, in LDMOSFET shown in FIG. 3 , the on-resistance caused by the hot carriers injected into the step insulating film 14 is increased.
On the other hand, FIG. 4 is a diagram schematically showing a state in which electrons flow in a LDMOSFET in which the basic concept of providing the potential control film 13 is embodied.
As shown in FIG. 4 , electrons flow from the source region 19 through a channel formed on the surface of the p-type body region 18 toward the drain region 17. At this time, in LDMOSFET shown in FIG. 4 , the potential control film 13 forms a potential barrier PB that exerts a repulsive force on electrons on the surface of the semiconductor substrate 1. Consequently, as shown in FIG. 4 , the current path through which the electrons flow shifts from “the surface of the semiconductor substrate 1” to “the inner part of the semiconductor substrate 1 (inside the bulk).” As a result, the current path through which the electrons flow is moved away from the interface between the step insulating film 14 and the semiconductor substrate 1, so that the hot carriers are suppressed from being injected into the step insulating film 14. Therefore, in LDMOSFET shown FIG. 4 , it is possible co suppress the increase of the on-resistance caused by the injection of hot carriers into the step insulating film 14.
From the above, it can be seen that the basic concept of forming potential barrier PB for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 by the potential control film 13 is an effective technical idea from the viewpoint of reducing on-resistance. Hereinafter, an example of an implementation mode in which this basic concept is embodied will be described.
Device Structure of LDMOSFET
FIG. 5 is a cross-sectional view showing the schematic device structure of LDMOSFET 100A.
In FIG. 5 , LDMOSFET has, for example, a semiconductor substrate 1 made of silicon. The semiconductor substrate 1 has a p-type resurf layer 10, and an n-type resurf layer 11 formed on the p-type resurf layer 10 (n-type drift layer). A gate dielectric film 12 formed of, for example, a silicon oxide film is formed on the semiconductor substrate 1.
A gate electrode 16 formed of, for example, an n-type polysilicon film is formed on the gate dielectric film 12. Here, “the gate electrode 16 formed “on” the gate dielectric film 12” is used in a broad intention including not only the configuration of the gate electrode 16 formed directly above the gate dielectric film 12, but also, for example as shown in FIG. 5 the configuration in which a high dielectric constant film 30 is formed on the gate dielectric film 12 and the gate electrode 16 is formed on the high dielectric constant film 30.
Specifically, in FIG. 5 , a high dielectric constant film 30 is formed on the gate dielectric film 12, the gate electrode 16 is formed on the high dielectric constant film 30.
Here, the “high dielectric constant film 30” in this specification is defined as a film having a dielectric constant higher than that of silicon. In the present embodiment, as shown in FIG. 5 , the high dielectric constant film 30 includes a “first portion” sandwiched between the gate dielectric film 12 and the gate electrode 16, and a “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12.
Next, LDMOSFET 100A includes a field plate portion 5 which is integrally formed with the gate electrode 16, and a step insulating 14 in contact with the field plate portion 15. The step insulating film 14 is formed of, for example, a silicon oxide film. The high dielectric constant film 30 is in contact with the step insulating film 14.
Subsequently, as shown in FIG. 5 , a drain region 17 formed of an n-type semiconductor region aligned with the step insulating film 14 is formed in the n-type resurf layer 11. Furthermore, the p-type body region 18 formed of a p-type semiconductor region is formed in the semiconductor substrate 1, and in the p-type body region 18, the source region 19 which is an n-type semiconductor region and the body contact region 20 which is a p-type semiconductor region, are formed. The source region 19 and the body contact region 20 are electrically connected to each other, and, for example, a ground potential of 0 V is supplied thereto. As a result, the ground potential is also supplied to the p-type body region 18 electrically connected to the body contact region 20. On the other hand, a positive potential is supplied to the drain region 17.
Here, the high dielectric constant film 30 shown in FIG. 5 is an example of the potential control film 13 shown in FIG. 2 . That is, the high dielectric constant film 30 functions as the potential control film 13 for forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14. More specifically, as will be described later, the high dielectric constant film 30 has a function of forming a potential barrier on the surface by shifting the Fermi level on the surface of the semiconductor substrate 1 located under the step insulating film 14. The high dielectric constant film 30 having such a function includes, for example, any of HfSiO, HfSiON, HfAlON, Y2O3 or Al2O3.
As described above, LDMOSFET 100A is configured.
Operation of LDMOSFET
Next, the operation of LDMOSFET 100A is described, First, the on-operation of LDMOSFET 100A will be described. In FIG. 5 , in a state of supplying a positive potential to the drain region 17 while supplying a ground potential to the source region 19, a gate voltage above the threshold voltage is applied to the gate electrode 16. Then, the inversion layer (n-type layer) serving as a channel layer is formed on the surface of the p-type body region 18 located under the gate electrode 16. Thus, electrons flow in the path of the source region 19, channel layer (inversion layer), n-type resurf layer 11 and drain region 17 in this order. In this way, LDMOSFET 100A is operated in on state.
Subsequently, the off-operation of LDMOSFET 100A will be described. In the on-state of LDMOSFET 100A, a smaller gate voltage (e.g., 0V) than the threshold voltage is applied to the gate electrode 16. Then, the inversion layer formed on the surface of the p-type body region 18 disappears. As a result, the path of the flow of electrons from the source region 19 to the drain region 17 is blocked. In this way, LDMOSFET 100A is turned off.
Feature in the Present Embodiment
Next, the feature points in the present embodiment will be described.
The feature point in the present embodiment is that, for example, as shown in FIG. 5 , a high dielectric constant film 30 is employed as a potential control film 13 for forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14. In other words, the feature point in the present embodiment is that a potential barrier is formed on the surface of the semiconductor substrate 1 located under the step insulating film 14 by the high dielectric constant film 30, and that the current path through which electrons flow is shifted from “the surface of the semiconductor substrate” to “the inner part of the semiconductor substrate (inside the bulk)” by this potential barrier. As a result, according to the present embodiment, the path through which electrons flow can be moved away from the interface between the step insulating film 14 and the semiconductor substrate 1, thereby suppressing hot carriers from being injected into the step insulating film 14. As a result, according to the present embodiment, it is possible to effectively suppress an increase of the on-resistance of LDMOSFET caused by the injection of hot carriers into the step insulating film 14.
Hereinafter, it will be described that the high dielectric constant film 30 functions as the potential control film 13.
FIG. 6A is a diagram schematically showing a band structure at the surface of the n-type resurf layer 11 when the gate dielectric film 12 formed of, for example, a silicon oxide film is formed on the n-type resurf layer 11. As shown in FIG. 6A, since the n-type resurf layer 11 is the n-type semiconductor layer, the Fermi level Ef is present in the vicinity of the lower end of conduction band.
However, on the n-type resurf layer 11, not only the gate dielectric film 12 formed of a silicon oxide film but also a high dielectric constant film 30 including, for example, HfSiO, HfSiON, HfAlON, Y2O3, or Al2O3 or the like in the constituent material and having a dielectric constant higher than that of silicon on this gate dielectric film 12 are formed, Fermi level Ef is moved away from the lower end of the conduction band, so-called “Fermi level pinning” phenomena occurs. Specifically, FIG. 6B is a diagram schematically showing a band structure on the surface of the n-type resurf layer 11 when the gate dielectric film 12 formed of a silicon oxide film and the high dielectric constant film 30 are formed on the n-type resurf layer 11. As shown in FIG. 6B, despite the n-type resurf layer 11 is n-type semiconductor layer, by “Fermi level pinning” due to the presence of the high dielectric constant film 30, it can be seen that the Fermi level Ef is shifted in a direction away from the lower end of conduction band. In the present embodiment, this “Fermi-level pinning” is used to form a potential barrier on the surface of the semiconductor substrate 1 located under the step insulating film 14. This point will be described below.
When matching the Fermi level Ef of FIGS. 6A and 6B to the same energy level, the Fermi level is as shown in FIGS. 7A and 7B. FIG. 7A is a diagram schematically showing a band structure at the surface of the n-type resurf layer 11 when, for example, a gate dielectric film 12 formed of a silicon oxide film is formed on the n-type resurf layer 11, and FIG. 75 is a diagram schematically showing a band structure at the surface of the n-type resurf layer 11 when a gate dielectric film 12 formed of a silicon oxide film and high dielectric constant film 30 are formed on the n-type resurf layer 11.
From FIGS. 7A and 7B, when forming a high dielectric constant film 30 on the n-type resurf layer 11, it can be seen by “Fermi level pinning”, the band structure at the surface of the n-type resurf layer 11 shifts a direction of electrically high energy. This means that by providing the high dielectric constant film 30, the energy level of the surface of the n-type resurf layer 11 is electrically raised, in other words, it means that the potential barrier for electrons is formed on the surface of the semiconductor substrate 1 located under the step insulating film 14. By such a mechanism, it is understood that the dielectric constant film 30 functions as the potential control film 13.
As described above, it can be said that the feature point in the present embodiment is that the potential barrier is formed on the surface of the semiconductor substrate 1 located under the step insulating film 14 by utilizing the phenomena “Fermi level pinning” caused by the high dielectric constant film 30. With this feature point, the path through which electrons flow can be moved away from the interface between the step insulating film 14 and the semiconductor substrate 1 by the repulsive force caused by the potential barrier. Therefore, according to the present embodiment, it is possible to suppress injection of hot carriers into the step insulating film 14, and as a result, it is possible to suppress an increase of on-resistance of LDMOSFET caused by injection of hot carriers into the step insulating film 14.
Method of Manufacturing Semiconductor Device Including LDMOSFET
Next, a method of manufacturing a semiconductor device including LDMOSFET will be described.
First, as shown in FIG. 8 , for example, a semiconductor substrate 1 made of silicon is prepared. After a sacrificial silicon oxide film. 35 is formed on the semiconductor substrate 1, a p-type resurf layer 10 and an n-type resurf layer 11 are formed in the semiconductor substrate 1 by ion implantation. Specifically, the p-type resurf layer 10 is formed by implanting boron as a p-type impurity (acceptor) into the semiconductor substrate 1. On the other hand, the n-type resurf layer 11 is formed by implanting phosphorus (P), which is an n-type impurity (donor), into the semiconductor substrate 1.
Next, as shown in FIG. 9 , a gate dielectric film 12 formed of a silicon oxide film is formed on the semiconductor substrate 1 by using, for example, a thermal oxidation method. Thereafter, a high dielectric constant film 30 formed by using an ALD (Atomic Layer Deposition) method or a CVD (Chemical Vapor Deposition) method. As the high dielectric constant film 30, for example, HfSiO film, HfSiON film, HfAlON film, Y2O3 film, and Al2O3 film can be mentioned. Then, for example, by using a CVD method, a silicon oxide film 14 a is formed on the high dielectric constant film 30.
Subsequently, as shown in FIG. 10 , the silicon oxide film 14 a is patterned by using a photolithography technique and an etching technique to form a step insulating film 14. Next, a polysilicon film is formed on the high dielectric constant film 30 so as to cover the step insulating film 14 by using, for example, a CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and the field plate portion 15 which are formed of a polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form a p-type body region 18.
Next, as shown in FIG. 5 , phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form a drain region 17 and a source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a body contact region 20 by using a photolithography technique and an ion implantation method. Thereafter, through an interlayer insulating film forming step to form interlayer insulating films and a wiring forming step to form wirings, it is possible to manufacture a semiconductor device including LDMOSFET 100A.
First Modified Example
In the above embodiment, for example, as shown in FIG. 5 , the high dielectric constant film 30 includes a “first portion” sandwiched between the gate dielectric film 12 and the gate electrode 16, and a “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12.
Here, the “second portion” of the high dielectric constant film 30 is important from the viewpoint of forming the potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14. On the other hand, the “first portion” of the high dielectric constant film 30 configures a stacked film with the gate dielectric film 12, and this stacked film influences threshold voltage for forming an inversion layer. That is, the “first portion” of the high dielectric constant film 30 is not essential from the viewpoint of forming the potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14. Rather, there is a disadvantage that the threshold voltage for forming the inversion layer is increased the “Fermi level pinning” caused by the “first portion” of the high dielectric constant film 30.
Therefore, FIG. 12 is a cross-sectional view schematically showing the device structure of LDMOSFET 1003 in the present first modified example. As shown in FIG. 12 , the high dielectric constant film 30 is composed of only the “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12. As a result, according to the present first modified example, it is possible to form the potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14, while suppressing the side effect that the threshold voltage for forming the inversion layer increases.
Method of Manufacturing Semiconductor Device Including LDMOSFET
In the semiconductor device including LDMOSFET in the present first modified example, the steps shown in FIGS. 8 and 9 are the same as in the above embodiment. Next, as shown in FIG. 13 , the high dielectric constant film 30 exposed from the step insulating film 14 is removed by using an etching technique. As a result, the high dielectric constant film 30 composed of only the “second portion” sandwiched between the step insulating film 14 and the gate dielectric film 12 can be formed.
Subsequently, a polysilicon film is formed on the gate dielectric film 12 so as to cover the step insulating film 14 by using, for example, a CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 which are formed of a polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body regions 18.
Next, as shown FIG. 12 , phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate to form the body contact region 20 by using a photolithography technique and an ion implantation method. Thereafter, through the interlayer insulating film forming step to form the interlayer insulating films and wiring forming step to form the wirings, it is possible to manufacture semiconductor device including LDMOSFET 100B.
Second Modified Example
Device Structure of LDMOSFET
FIG. 15 is a cross-sectional view schematically showing the device structure of LDMOSFET 1000 in the present second modified example. In FIG. 15 , the feature point in the second modified example is that a high dielectric constant film 30 is formed over the exposed gate dielectric film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. In particular, the film thickness of the high dielectric constant film 30 in the present second modified example is thicker than the film thickness of the high dielectric constant film 30 in the above embodiment and the first modified example. This is because ensuring the effect of forming potential barrier by increasing the film thickness of the high dielectric constant film 30 in the present second modified example, considering that the effect of forming a potential barrier on the surface of the semiconductor substrate 1 is decreased as a result of the high dielectric constant film 30 is disposed above rather than under the step insulating film 14. In this manner, LDMOSFET 100C in the present second modified example is configured.
Method of Manufacturing Semiconductor Device including LDMOSFET
In the semiconductor device including LDMOSFET in the present second modified example, the step shown in FIG. 8 is the same as the above embodiment. Next, as shown in FIG. 16 , after a silicon oxide film is formed on the semiconductor substrate 1 by using, for example, a CVD method, the silicon oxide film is patterned by using a photolithography technique and an etch technique to form a step insulating film 14. Thereafter, as shown in FIG. 17 , a gate dielectric film 12 is formed on the exposed surface of the semiconductor substrate 1 by using, for example, a thermal oxidization method.
Next, as shown in FIG. 18 , a polysilicon film is formed on the gate dielectric film 12 and the step insulating film 14 by using, for example, the CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 formed of the polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body region 18. Next, by using a photolithography technique and an ion implantation method, phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form the body contact region 20. Then, as shown in FIG. 15 , a high dielectric constant film 30 is formed so as to cover the exposed gate dielectric film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. Thereafter, through the interlayer insulating film forming step to form interlayer insulating films and wiring forming step to form wirings, it is possible to manufacture a semiconductor device including LDMOSFET 100C.
Advantage of Second Modified Example
Also in the present second modified example, while it is possible to form a potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14 by the high dielectric constant film 30 of which the film thickness is thick, it is possible to suppress the side effect that the threshold voltage for forming the inversion layer increased since there is no high dielectric constant film 30 under the gate electrode 16.
In particular, the present second modified example, since the step of patterning the high dielectric constant film 30 is not necessary as in the above-mentioned first modified example, it is possible to suppress an increase of threshold voltage for forming inversion layer without adding a patterning step while forming potential barrier for electrons on the surface of the semiconductor substrate 1 located under the step insulating film 14.
Third Modified Example
Device Structure of LDMOSFET
FIG. 19 is a cross-sectional view schematically showing the device structure of LDMOSFET 100D in the present third modified example. In FIG. 19 , the feature point of the present third modified example is that, as it is premise that the step insulating film 4 has the “contact portion” in contact with the field plate portion 15 and the “non-contact portion” projecting from the field plate portion 15, the “non-contact portion” is configured of the “thin film portion” in which the concave portion is formed and the “thick film portion” which is thicker than the “thin film portion”, and that the high dielectric constant film 30 is formed over the exposed gate dielectric film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. At this time, when the film thickness of the “thick film portion” is set to “t1” and the film thickness of the “thin film portion” is set to “t2”, the relationship of t2<t1 is established.
Method of Manufacturing Semiconductor Device including LDMOSFET
In the semiconductor device including LDMOSFET in the third modified example, until the step shown in FIG. 16 is the same as the second modified example. Thereafter, as shown in FIG. 20 , a concave portion 40 is formed in the step insulating film 14 by using a photolithography technique and an etching technique. Then, as shown in FIG. 21 , a gate dielectric film 12 is formed on the exposed surface of the semiconductor substrate 1 by using, for example, a thermal oxidization method.
Next, as shown in FIG. 22 , a polysilicon film is formed on the gate dielectric film and the step insulating film 14 by using, for example, the CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 formed of the polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body regions 18. Next, by using a photolithography technique and an ion implantation method, phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19, and boron, which is a p type impurity, is implanted into the semiconductor substrate 1 to form the body contact region 20. Then, as shown in FIG. 19 , a high dielectric constant film 30 is formed so as to cover the exposed gate dielectric film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. Thereafter, through the interlayer insulating film forming step to form interlayer insulating films and wiring forming step to form wirings, it is possible to manufacture a semiconductor device including LDMOSFET 100D.
Advantage of Third Modified Example
According to the present third modified example, the “thin film portion” in which the concave portion is formed is formed in the step insulating film 14, and the high dielectric constant film 30 is also formed inside the concave portion of the “thin film portion”. In this regard, since it is possible to ensure the effect of forming a potential barrier on the surface of the semiconductor substrate 1, in the present third modified example, the advantage that can reduce the film thickness of the high dielectric constant film 30 than second modified example is obtained.
Fourth Modified Example
Device Structure of LDMOSFET
FIG. 23 is a cross-sectional view schematically showing the device structure of LDMOSFET 100E in the present fourth modified example. In FIG. 23 , the feature point of the present fourth modified example is that the film thickness “t2” of the “thin film portion” including the concave portion provided in the step insulating film 14 is equal to the film thickness of the gate dielectric film 12.
Method of Manufacturing Semiconductor Device Including LDMOSFET
In the semiconductor device including LDMOSFET in the present fourth modified example, until the step shown in FIG. 16 is the same as the second modified example. Thereafter, as shown in FIG. 24 , a concave portion 40 is formed in the step insulating film 14 by using a photolithography technique and an etching technique. At this time, the concave portion 40 is formed such that the bottom of the concave portion 40 reaches the surface of the semiconductor substrate 1. Then, as shown in FIG. 25 , a gate dielectric film 12 is formed on the exposed surface of the semiconductor substrate 1 by using, for example, a thermal oxidization method. Here, the gate dielectric film 12 is also formed on the surface of the semiconductor substrate 1 exposed at the bottom of the concave portion 40.
The film thickness of the gate dielectric film 12 formed at the bottom of the concave portion 40 is equal to the film thickness of the gate dielectric film 12 formed on the other surface of the semiconductor substrate 1.
Next, as shown in FIG. 26 , a polysilicon film is formed on the gate dielectric film 12 and the step insulating film 14 by using, for example, the CVD method. Then, the polysilicon film is patterned by using photolithography and etching techniques. Thus, a gate electrode 16 and a field plate portion 15 formed of the polysilicon film are integrally formed. Thereafter, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 by using a photolithography technique and an oblique ion implantation method to form the p-type body regions 18. Next, by using a photolithography technique and an ion implantation method, phosphorus which is an n-type impurity is implanted into the semiconductor substrate 1 to form the drain region 17 and the source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form the body contact region 20. Then, as shown in FIG. 23 , a high dielectric constant film 30 is formed so as to cover the exposed gate dielectric film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. Thereafter, through the interlayer insulating film forming step to form interlayer insulating films and wiring forming step to form wirings, it is possible to manufacture a semiconductor device including LDMOSFET 100E.
Advantage of Fourth Modified Example
For example, in the above third modified example, since the film thickness “t2” of the “thin film portion” differs from the film thickness of the gate dielectric film 12, the etching amount of the concave portion 40 needs to be adjusted in the step of forming the concave portion 40 (refer to FIG. 20 ). On the other hand, in the present fourth modified example, since the film thickness “t2” of the “thin film portion” is made equal to the film thickness of the gate dielectric film 12, for example, as shown in FIG. 24 , in the step of forming the concave portion 40, the concave portion 40 may be formed so as to expose the semiconductor substrate 1 at the bottom of the concave portion 40 without finely adjusting the etching amount of the concave portion 40. This is because “over etching” is also allowed, the advantage that the etching step for forming the concave portion is facilitated is obtained. Then, in the present fourth modified example, by applying the thermal oxidation method to the exposed entire surface of the semiconductor substrate 1 including the surface of the semiconductor substrate 1 exposed from the bottom of the concave portion 40, since the gate dielectric film 12 is also formed at the bottom of the concave portion 40, the film thickness “t2” of the “thin film portion” can be automatically made equal to the film thickness of the gate dielectric film 12 of the other regions.
The invention made by the present inventor has been described above in detail based on the embodiment, but the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof.
The embodiment includes the following embodiments.
Appendix 1
Method of Manufacturing Semiconductor Device According to Embodiment
A method of manufacturing a semiconductor device, the method includes:
    • (a) forming a gate dielectric film on a semiconductor substrate;
    • (b) forming a high dielectric constant film having a higher dielectric constant than silicon on the gate dielectric film;
    • (c) forming a step insulating film in contact with the high dielectric constant film; and
    • (d) integrally forming a gate electrode in contact with the high dielectric constant film and a field plate portion in contact with the step insulating film.
Appendix 2
Method of Manufacturing Semiconductor Device According to First Modified Example
A method of manufacturing a semiconductor device, the method includes:
    • (a) forming a gate dielectric film on a semiconductor substrate;
    • (b) forming a high dielectric constant film having a higher dielectric constant than silicon on the gate dielectric film;
    • (c) forming a step insulating film in contact with the high dielectric constant film;
    • (d) removing the high dielectric constant film exposed from the step insulating film; and
    • (e) integrally forming a gate electrode in contact with the gate dielectric film and a field plate portion in contact with the step insulating film.
Appendix 3
Method of Manufacturing Semiconductor Device According to Second Modified Example
A method of manufacturing a semiconductor device, the method includes:
    • (a) forming a step insulating film on a semiconductor substrate;
    • (b) forming a gate dielectric film on the semiconductor substrate except for the step insulating film;
    • (c) integrally forming a gate electrode in contact with the gate dielectric film and a field plate portion in contact with the step insulating film; and
    • (d) forming a high dielectric constant film having a higher dielectric constant film than silicon so as to be in contact with the gate electrode, the field plate portion and the step insulating film,
Appendix 4
Method of Manufacturing Semiconductor Device According to Third Modified Example
A method of manufacturing a semiconductor device, the method includes:
    • (a) forming a step insulating film on a semiconductor substrate;
    • (b) forming a concave portion in the step insulating film;
    • (c) forming a gate dielectric film on the semiconductor substrate except for the step insulating film;
    • (d) integrally forming a gate electrode in contact with the gate dielectric film and a field plate portion in contact with the step insulating film, the field plate portion being not in contact with the concave portion; and
    • (e) forming a high dielectric constant film having a higher dielectric constant film than silicon so as to be in contact with the gate electrode, the field plate portion and the step insulating film.
Appendix 5
Method of Manufacturing Semiconductor Device According to Fourth Modified Example
A method of manufacturing a semiconductor device, the method includes:
    • (a) forming a step insulating film on a semiconductor substrate;
    • (b) forming a concave portion reaching the semiconductor substrate in the step insulating film;
    • (c) forming a gate dielectric film on the semiconductor substrate including a bottom of the concave portion;
    • (d) integrally forming a gate electrode in contact with the gate dielectric film and a field plate portion in contact with the step insulating film, the field plate portion being not in contact with the concave portion; and
    • (e) forming a high dielectric constant film having a higher dielectric constant film than silicon so as to be in contact with the gate electrode, the field plate portion, the step insulating film and an inner side surface of the concave portion.

Claims (10)

What is claimed is:
1. A semiconductor device comprising:
a semiconductor substrate;
a gate dielectric film formed on the semiconductor substrate;
a gate electrode formed over the gate dielectric film;
a field plate portion integrally formed with the gate electrode;
a step dielectric film in contact with the field plate portion; and
a high dielectric constant film having a higher dielectric constant than silicon, the high dielectric constant film being in contact with the step dielectric film,
wherein the high dielectric constant film includes:
a first portion sandwiched between the gate dielectric film and the gate electrode; and
a second portion sandwiched between the step dielectric film and the gate dielectric film.
2. The semiconductor device according to claim 1,
wherein the high dielectric constant film has a function of forming a potential barrier on a surface of the semiconductor substrate by shifting a Fermi level on the surface of the semiconductor substrate located under the step dielectric film.
3. The semiconductor device according to claim 1,
wherein a material of the high dielectric constant film includes any of HfSiO, HfSiON, HfAlON, Y2O3 or Al2O3.
4. The semiconductor device according to claim 1,
wherein the high dielectric constant film is formed of a portion sandwiched between the step dielectric film and the gate dielectric film.
5. The semiconductor device according to claim 1,
wherein the high dielectric constant film is a film covering the gate electrode, the field plate portion and the step dielectric film.
6. The semiconductor device according to claim 5,
wherein the step dielectric film includes:
a contact portion in contact with the field plate portion; and
a non-contact portion protruded from the field plate portion, and
wherein the non-contact portion includes:
a thin film portion on which a recess portion is formed; and
a thick film portion having a thicker film thickness than the thin film portion.
7. The semiconductor device according to claim 6,
wherein a film thickness of the thin film portion is equal to a film thickness of the gate dielectric film.
8. A semiconductor device comprising:
a semiconductor substrate;
a gate dielectric film formed on the semiconductor substrate;
a gate electrode formed over the gate dielectric film;
a field plate portion integrally formed with the gate electrode;
a step dielectric film in contact with the field plate portion; and
a potential control film in contact with the step dielectric film, the potential control film forming a potential barrier on a surface of the semiconductor substrate located under the step dielectric film.
9. The semiconductor device according to claim 8,
wherein the potential control film is a film forming the potential barrier on the surface of the semiconductor substrate by shifting a Fermi level on the surface of the semiconductor substrate located under the step dielectric film.
10. A semiconductor device comprising:
a semiconductor substrate;
a gate dielectric film formed on the semiconductor substrate;
a gate electrode formed over the gate dielectric film;
a field plate portion integrally formed with the gate electrode;
a step dielectric film in contact with the field plate portion; and
a high dielectric constant film having a higher dielectric constant than silicon, the high dielectric constant film being in contact with the step dielectric film,
wherein the high dielectric constant film has a function of forming a potential barrier on a surface of the semiconductor substrate by shifting a Fermi level on the surface of the semiconductor substrate located under the step dielectric film.
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