US11909313B2 - Voltage converter, storage device including voltage converter, and operating method of voltage converter - Google Patents
Voltage converter, storage device including voltage converter, and operating method of voltage converter Download PDFInfo
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- US11909313B2 US11909313B2 US17/346,769 US202117346769A US11909313B2 US 11909313 B2 US11909313 B2 US 11909313B2 US 202117346769 A US202117346769 A US 202117346769A US 11909313 B2 US11909313 B2 US 11909313B2
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- Embodiments of the present disclosure described herein relate to electronic devices, and more particularly, relate to voltage converters having improved power efficiency, storage devices including the voltage converter, and operating methods of the voltage converter.
- Electronic devices may operate based on power from the outside.
- an electronic device may convert an external power supply voltage supplied from the outside to an internal power supply voltage necessary for components therein and may use the internal power supply voltage.
- a required voltage converter may change depending on a kind of the electronic device.
- an electronic device that uses an internal power supply voltage greater than an external power supply voltage may require a boost converter as a voltage converter.
- An electronic device that uses an internal power supply voltage smaller than an external power supply voltage may require a buck converter as a voltage converter.
- An efficient switching manner of the buck converter or the boost converter may change depending on a difference between a level of an external power supply voltage and a level of an internal power supply voltage. Accordingly, there is required a voltage converter adaptively coping with various peripheral environments.
- Example embodiments of the present disclosure provide voltage converter shaving improved power efficiency, storage devices including the voltage converter, and operating methods of the voltage converter.
- an operating method of a voltage converter includes converting an input voltage to an output voltage and providing a load current corresponding to the output voltage in a pulse frequency modulation mode or a pulse width modulation mode, entering the pulse frequency modulation mode in response to an amount of the load current being less than or equal to a first threshold value, and entering the pulse width modulation mode in response to the amount of the load current being greater than a second threshold value.
- a voltage converter includes a first transistor connected between an input node and a switch node, a second transistors connected between the switch node and a ground node, an inductor connected between the switch node and an output node, a capacitor connected between the output node and the ground node, resistors connected with the output node, and configured to divide an output voltage of the output node to generate a feedback voltage, a comparator to compare the feedback voltage and a reference voltage to output a comparison signal, a mode control circuit to output a mode signal of a first level based on an amount of a load current supplied through the output node being less than or equal to a threshold and to output the mode signal of a second level based on the amount of the load current being greater than the threshold, a control logic circuit to generate a first control signal and a second control signal based on pulse frequency modulation based on the mode signal being at the first level and to generate the first control signal and the second control signal based on pulse width modulation based on the mode
- a storage device includes a nonvolatile memory device, a controller to control the nonvolatile memory device, and a power management integrated circuit to supply an output voltage to the nonvolatile memory device and the controller.
- the power management integrated circuit includes a first transistor connected between an input node and a switch node, a second transistor connected between the switch node and a ground node, an inductor connected between the switch node and an output node from which the output voltage is output, a capacitor connected between the output node and the ground node, resistors connected with the output node, and configured to divide the output voltage to generate a feedback voltage, a mode control circuit to output a mode signal of a first level based on an amount of a load current supplied through the output node being greater than a threshold and to output the mode signal of a second level based on the amount of the load current being less than or equal to the threshold, a control logic circuit to generate a first control signal and a second control signal based on pulse frequency modulation based on
- FIG. 1 illustrates a voltage converter according to some example embodiments of the present disclosure.
- FIG. 2 illustrates an example of an operating method of a voltage converter of FIG. 1 .
- FIG. 3 illustrates a control logic circuit according to some example embodiments of the present disclosure.
- FIG. 4 illustrates an example of a procedure in which a control logic circuit operates in a PFM mode.
- FIG. 5 illustrates a method in which signals of a control logic circuit are controlled in a PFM mode.
- FIG. 6 illustrates an example in which signals of a voltage converter are controlled by a control logic circuit in a PFM mode.
- FIG. 7 illustrates an example of a procedure in which a control logic circuit operates in a PWM mode.
- FIG. 8 illustrates a method in which signals of a control logic circuit are controlled in a PWM mode.
- FIG. 9 illustrates an example in which signals of a voltage converter are controlled by a control logic circuit in a PWM mode.
- FIG. 10 illustrates an example of a procedure in which a control logic circuit enters a PWM mode from a PFM mode.
- FIG. 11 illustrates a method in which signals of a control logic circuit are controlled in the process where a control logic circuit enters a PWM mode from a PFM mode.
- FIG. 12 illustrates an example in which signals of a voltage converter are controlled by a control logic circuit in the process where a control logic circuit enters a PWM mode from a PFM mode.
- FIG. 13 illustrates a diode sensor and a partial voltage converter associated with the diode sensor.
- FIG. 14 illustrates examples in which a detection signal is activated.
- FIG. 15 illustrates a mode control circuit according to some example embodiments of the present disclosure.
- FIG. 16 illustrates a state diagram of a mode control circuit.
- FIG. 17 illustrates an electronic device according to some example embodiments of the present disclosure.
- FIG. 1 illustrates a voltage converter 100 according to some example embodiments of the present disclosure.
- the voltage converter 100 may include a buck converter circuit 110 , a comparison circuit 120 , a zero current sensor 130 , a diode sensor 140 , a mode control circuit 150 , and a control logic circuit 160 .
- the buck converter circuit 110 may receive an input voltage VIN from an input node NI.
- the buck converter circuit 110 may convert the input voltage VIN and may output the converted voltage to an output node NO as an output voltage VOUT.
- the buck converter circuit 110 may step down the input voltage VIN and may output the stepped-down voltage as the output voltage VOUT.
- the buck converter circuit 110 may include a first power transistor 111 , a second power transistor 112 , a gate driver 113 , an inductor LN, a capacitor “C”, a first resistor R 1 , and a second resistor R 2 .
- the first power transistor 111 may be connected between (e.g., directly connected between) the input node NI and a switch node NSW.
- the first power transistor 111 may be a PMOS transistor.
- the first power transistor 111 may operate in response to a first drive signal DRV 1 output from the gate driver 113 .
- the second power transistor 112 may be connected between (e.g., directly connected between) the switch node NSW and a ground node to which a ground voltage VSS is supplied.
- the second power transistor 112 may be an NMOS transistor.
- the second power transistor 112 may operate in response to a second drive signal DRV 2 output from the gate driver 113 .
- the gate driver 113 may receive a first control signal CS 1 and a second control signal CS 2 from the control logic circuit 160 .
- the gate driver 113 may generate the first drive signal DRV 1 and the second drive signal DRV 2 based on the first control signal CS 1 and the second control signal CS 2 .
- the gate driver 113 may respectively apply the first drive signal DRV 1 and the second drive signal DRV 2 to a gate of the first power transistor 111 and a gate of the second power transistor 112 and thus may control the first power transistor 111 and the second power transistor 112 .
- the gate driver 113 may generate the first drive signal DRV 1 so as to follow at least a portion of a waveform of the first control signal CS 1 .
- the gate driver 113 may generate the second drive signal DRV 2 so as to follow at least a portion of a waveform of the second control signal CS 2 .
- the inductor LN may be connected between (e.g., directly connected between) the switch node NSW and the output node NO.
- a direction from the switch node NSW to the output node NO may be a positive direction of an inductor current IL.
- the capacitor “C” may be connected between (e.g., directly connected between) the output node NO and the ground node to which the ground voltage VSS is supplied.
- the first resistor R 1 and the second resistor R 2 may be connected between (e.g., directly connected between) the output node NO and the ground node to which the ground voltage VSS is supplied.
- a voltage of a feedback node NFB between the first resistor R 1 and the second resistor R 2 may be output as a feedback voltage VFB.
- the comparison circuit 120 may include a voltage generator 121 and a comparator 122 .
- the voltage generator 121 may generate a reference voltage VREF.
- the voltage generator 121 may output the reference voltage VREF thus generated to the comparator 122 .
- the voltage generator 121 may set a level of the reference voltage VREF such that the output voltage VOUT is the same (or, similar, for example, within ⁇ 10%) as a target level of the output voltage VOUT when the feedback voltage VFB is the same (or, similar, for example, within ⁇ 10%) as the reference voltage VREF.
- the comparator 122 may include a positive input (+) of receiving the feedback voltage VFB and a negative input ( ⁇ ) of receiving the reference voltage VREF.
- the comparator 122 may compare the feedback voltage VFB and the reference voltage VREF to output a comparison signal CPS. For example, when the feedback voltage VFB is not greater (e.g., less than or equal to) than the reference voltage VREF (or approaches to the reference voltage VREF within a preset (e.g., desired) voltage), the comparator 122 may output the comparison signal CPS of a first level (e.g., a low level). When the feedback voltage VFB is greater than the reference voltage VREF, the comparator 122 may output the comparison signal CPS of a second level (e.g., a high level).
- a first level e.g., a low level
- the comparator 122 may output the comparison signal CPS of a second level (e.g., a high level).
- the zero current sensor 130 may receive a switch voltage VSW of the switch node NSW of the buck converter circuit 110 . In response to the switch voltage VSW, the zero current sensor 130 may detect that no current flows to the switch node NSW. In response to detecting that no current flows to the switch node NSW, the zero current sensor 130 may output a zero current, signal ZCS of the second level (e.g., the high level). When a current flows to the switch node NSW, the zero current sensor 130 may output the zero current signal ZCS of the first level (e.g., the low level).
- the diode sensor 140 may receive the switch voltage VSW of the switch node NSW. In response to the switch voltage VSW, the diode sensor 140 may determine whether a load current (e.g., ILOAD) output through the output node NO is not greater (e.g., less than or equal to) than a threshold. When the load current ILOAD is greater than the threshold, the diode sensor 140 may output a detection signal DS of the first level (e.g., the low level). When the load current ILOAD is not greater (e.g., less than or equal to) than the threshold, the diode sensor 140 may output the detection signal DS of the second level (e.g., the high level).
- a load current e.g., ILOAD
- the diode sensor 140 may output the detection signal DS of the second level (e.g., the high level).
- the diode sensor 140 may be activated while a specific condition is satisfied.
- the specific condition at which the diode sensor 140 is activated will be more fully described with reference to FIGS. 13 and 14 .
- the mode control circuit 150 may receive the zero current signal ZCS from the zero current sensor 130 and may receive the detection signal DS from the diode sensor 140 . Also, the mode control circuit 150 may receive the first control signal CS 1 and the second control signal CS 2 from the control logic circuit 160 . The mode control circuit 150 may generate a mode signal MODE based on the zero current signal ZCS, the detection signal DS, the first control signal CS 1 , and the second control signal CS 2 .
- the mode control circuit 150 in response to the detection signal DS being deactivated (e.g., is maintained at the second level (or high level)), the mode control circuit 150 may control the mode signal MODE to the first level (or low level). In response to the zero current signal ZCS being deactivated (e.g., is maintained at the first level (or low level)), the mode control circuit 150 may control the mode signal MODE to the second level (or high level).
- the mode control circuit 150 may provide a hysteresis to transition between two modes. Accordingly, the stability of the voltage converter 100 may be improved.
- the control logic circuit 160 may receive the zero current signal ZCS from the zero current sensor 130 and may receive the mode signal MODE from the mode control circuit 150 . Also, the control logic circuit 160 may receive the input voltage VIN and the output voltage VOUT. The control logic circuit 160 may further receive the comparison signal CPS from the comparison circuit 120 . The control logic circuit 160 may control the first control signal CS 1 and the second control signal CS 2 in response to the comparison signal CPS, the zero current signal ZCS, the mode signal MODE, the input voltage VIN, and the output voltage VOUT.
- control logic circuit 160 may control the first control signal CS 1 and the second control signal CS 2 based on a period.
- the control logic circuit 160 may switch between a first mode and a second mode based on the mode signal MODE. In the first mode, the control logic circuit 160 may control the first control signal CS 1 and the second control signal CS 2 based on pulse frequency modulation (PFM) for adjusting a length of the period.
- PFM pulse frequency modulation
- control logic circuit 160 may complementarily control the first control signal CS 1 and the second control signal CS 2 within a fixed period.
- the control logic circuit 160 may control the first control signal CS 1 and the second control signal CS 2 based on pulse width modulation (PWM) for adjusting a length of a pulse width, in which the first control signal CS 1 or the second control signal CS 2 has the high level, within a fixed period.
- PWM pulse width modulation
- the voltage converter 100 may convert the input voltage VIN to the output voltage VOUT with improved power efficiency.
- the voltage converter 100 may have more improved power efficiency.
- FIG. 2 illustrates an example of an operating method of the voltage converter 100 of FIG. 1 .
- the voltage converter 100 may provide the load current ILOAD corresponding to the output voltage VOUT at the output node NO.
- the mode control circuit 150 may determine the amount of load current ILOAD. For example, the mode control circuit 150 may determine the amount of load current ILOAD, based on the zero current signal ZCS and the detection signal DS.
- the mode control circuit 150 may determine whether the amount of load current ILOAD is greater than a first threshold value TV 1 . For example, the mode control circuit 150 may determine whether the amount of load current ILOAD is greater than the first threshold value TV 1 , based on the detection signal DS.
- the detection signal DS may be deactivated to the second level (or high level), and the mode control circuit 150 may control the mode signal MODE to the first level (or low level).
- the control logic circuit 160 may enter the PFM mode and may control the first control signal CS 1 and the second control signal CS 2 based on the PFM.
- the mode control circuit 150 may determine whether the amount of load current ILOAD is greater than a second threshold value TV 2 . For example, the mode control circuit 150 may determine whether the amount of load current ILOAD is greater than the second threshold value TV 2 , based on the zero current signal ZCS.
- the zero current signal ZCS may be deactivated to the first level (or low level), and the mode control circuit 150 may control the mode signal MODE to the second level (or high level).
- the control logic circuit 160 may control the first control signal CS 1 and the second control signal CS 2 based on the PWM.
- the mode control circuit 150 may maintain the mode signal MODE. That is, the control logic circuit 160 may maintain a current mode, for example, the PFM mode or the PWM mode.
- the control logic circuit 160 may perform on-time control on the first control signal CS 1 and the second control signal CS 2 .
- the control logic circuit 160 may control a length of a time, during which the first power transistor 111 is turned on, within a period.
- the first power transistor 111 may have a turn-off interval within each period.
- the first power transistor 111 may be turned off during each period.
- the control logic circuit 160 may perform off-time control on the first control signal CS 1 and the second control signal CS 2 .
- the control logic circuit 160 may control a length of a time, during which the first power transistor 111 is turned off, within a period.
- the first power transistor 111 may have a turn-on interval within each period.
- the first power transistor 111 may be turned on during each period.
- FIG. 3 illustrates a control logic circuit 200 according to some example embodiments of the present disclosure.
- the control logic circuit 200 may correspond to the control logic circuit 160 of FIG. 1 .
- the control logic circuit 200 may include a first signal generator 211 , a second signal generator 212 , a first flip-flop 221 , a second flip-flop 222 , a first OR gate 231 , a second OR gate 232 , a first AND gate 241 , a second AND gate 242 , a latch 250 , a first inverter 261 , a second inverter 262 , a third inverter 263 , a fourth inverter 264 , a first pulse generator 271 , and a second pulse generator 272 .
- the first signal generator 211 may receive the input voltage VIN, the output voltage VOUT, and the first control signal CS 1 .
- the first signal generator 211 may output an output signal to a clock input of the first flip-flop 221 .
- the first signal generator 211 may transit the output signal to the high level in synchronization with a falling edge of the first control signal CS 1 .
- the first signal generator 211 may transit the output signal from the low level to the high level.
- the second delay time TD 2 may be determined by the input voltage VIN and the output voltage VOUT.
- the second delay time TD 2 may be determined by Equation 1 below.
- FS may indicate a switching frequency.
- the switching frequency may correspond to a period that the control logic circuit 200 uses to control the first control signal CS 1 and the second control signal CS 2 (e.g., may be the reverse of the frequency).
- the first signal generator 211 may transit the output signal from the high level to the low level.
- the first pulse generator 271 may operate in response to the first control signal CS 1 . For example, when the first control signal CS 1 transitions from the high level to the low level, that is, in synchronization with a falling edge thereof, the first pulse generator 271 may output a pulse that transitions from the high level to the low level and then transitions from the low level to the high level. The pulse generated by the first pulse generator 271 may be transferred to a reset input “R” of the first flip-flop 221 .
- the first flip-flop 221 may include the clock input to which the output signal of the first signal generator 211 is transferred, the reset input to which the output pulse of the first pulse generator 271 is transferred, a data input “D” to which a power supply voltage VDD is transferred, a non-reverse output “Q” connected with the first OR gate 231 , and a reverse output /Q of a floating state.
- the non-reverse output “Q” of the first flip-flop 221 may transition from the low level to the high level.
- the output signal of the first pulse generator 271 transferred to the reset input “R” transitions from the high level to the low level (e.g., in synchronization with a falling edge thereof)
- the non-reverse output “Q” of the first flip-flop 221 may transition from the high level to the low level.
- the first OR gate 231 may perform an OR operation on the non-reverse output “Q” of the first flip-flop 221 and the mode signal MODE. An output of the first OR gate 231 may be transferred to the first AND gate 241 .
- the first AND gate 241 may perform an AND operation on the output of the first OR gate 231 and the comparison signal CPS. An output of the first AND gate 241 may be transferred to the second inverter 262 and a reset input “R” of the latch 250 .
- the second signal generator 212 may receive the input voltage VIN, the output voltage VOUT, and a non-reverse output “Q” of the second flip-flop 222 .
- the second signal generator 212 may output an output signal to the second pulse generator 272 .
- the second signal generator 212 may transit the output signal to the high level in synchronization with a rising edge of the non-reverse output “Q” of the second flip-flop 222 .
- the second signal generator 212 may transit the output signal from the low level to the high level.
- the sixth delay time TD 6 may be determined by the input voltage VIN and the output voltage VOUT.
- the sixth delay time TD 6 may be determined by Equation 2 below.
- the second signal generator 212 may transit the output signal from the high level to the low level when the non-reverse output “Q” of the second flip-flop 222 transitions from the high level to the low level, or after the output signal transitions from the low level to the high level and then a given (e.g., desired) time passes.
- a specific delay time e.g., the sixth delay time TD 6 or a given (e.g., desired) time
- the second pulse generator 272 may operate in response to the output signal of the second signal generator 212 . For example, when the output signal of the second signal generator 212 transitions from the low level to the high level, that is, in synchronization with a rising edge thereof, the second pulse generator 272 may output a pulse that transitions from the low level to the high level and then transitions from the high level to the low level. The pulse generated by the second pulse generator 272 may be transferred to the first inverter 261 .
- the first inverter 261 may invert the pulse output from the second pulse generator 272 so as to be transferred to a reset input “R” of the second flip-flop 222 .
- the second flip-flop 222 may include a clock input to which the first control signal CS 1 is transferred, a data input “D” to which the power supply voltage VDD is transferred, the non-reverse output “Q” connected with the second signal generator 212 , and a reverse output /Q transferred to the second AND gate 242 .
- the non-reverse output “Q” of the second flip-flop 222 may transition from the low level to the high level, and the reverse output /Q of the second flip-flop 222 may transition from the high level to the low level.
- the output signal of the inverter 261 transitions from the high level to the low level (e.g., in synchronization with a falling edge thereof)
- the non-reverse output “Q” of the second flip-flop 222 may transition from the high level to the low level
- the reverse output /Q of the second flip-flop 222 may transition from the low level to the high level.
- the second inverter 262 may invert an output of the first AND gate 241 so as to be output to the second AND gate 242 .
- the second AND gate 242 may perform an AND operation on the output of the second inverter 262 and the reverse output /Q of the second flip-flop 222 .
- An output of the second AND gate 242 may be transferred to a set input “S” of the latch 250 .
- the latch 250 may include a first NOR gate 251 and a second NOR gate 252 .
- the first NOR gate 251 may perform a NOR operation on the reset input “R” and an output of the second NOR gate 252 .
- An output of the first NOR gate 251 may be a non-reverse output “Q” of the latch 250 .
- the second NOR gate 252 may perform a NOR operation on the set input “S” and the output of the first NOR gate 251 .
- An output of the second NOR gate 252 may be transferred to the first NOR gate 251 .
- the non-reverse output “Q” of the latch 250 may be transferred to the third inverter 263 and the second OR gate 232 .
- the third inverter 263 may invert the non-reverse output “Q” and may output the inverted output as the first control signal CS 1 .
- the second OR gate 232 may perform an OR operation on the non-reverse output “Q” of the latch 250 and the zero current signal ZCS. An output of the second OR gate 232 may be transferred to the fourth inverter 264 .
- the fourth inverter 264 may invert an output of the second OR gate 232 and may output the inverted output as the second control signal CS 2 .
- FIG. 4 illustrates an example of a procedure in which the control logic circuit 200 operates in the PFM mode.
- the control logic circuit 200 may transit the first control signal CS 1 from the high level to the low level in response to the comparison signal CPS being set to the low level.
- the control logic circuit 200 may transit the first control signal CS 1 from the low level to the high level and may transit the second control signal CS 2 from the low level to the high level.
- control logic circuit 200 may transit the second control signal CS 2 from the high level to the low level.
- FIG. 5 illustrates a method in which signals of the control logic circuit 200 are controlled in the PFM mode.
- FIG. 6 illustrates an example in which signals of the voltage converter 100 are controlled by the control logic circuit 200 in the PFM mode.
- a comparison of the feedback voltage VFB and the reference voltage VREF is shown.
- a comparison of the load current ILOAD and the inductor current IL is shown.
- a signal S_ 211 may be an output of the first signal generator 211 .
- a signal Q_ 221 may be the non-reverse output “Q” of the first flip-flop 221 .
- a signal S_ 241 may be an output of the first AND gate 241 .
- a signal S_ 242 may be an output of the second AND gate 242 .
- a signal Q_ 222 may be the non-reverse output “Q” of the second flip-flop 222 .
- a signal /Q_ 222 may be the reverse output /Q of the second flip-flop 222 .
- a signal S_ 272 may be an output of the second pulse generator 272 .
- the mode signal MODE may have the low level “L”.
- the first pulse generator 271 may output a pulse that transitions from the high level to the low level and then transitions from the low level to the high level.
- the non-reverse output Q_ 221 of the first flip-flop 221 may transition from the high level to the low level.
- the comparison signal CPS may transition from the high level to the low level.
- an output signal S_ 241 of the first AND gate 241 may transition from the high level to the low level.
- an output of the inverter 262 may transition from the low level to the high level.
- the reverse output /Q_ 222 of the second flip-flop 222 may be at the high level. Accordingly, the output signal S_ 242 of the second AND gate 242 may transition from the low level to the high level. That is, the latch 250 may be set, and an output of the latch 250 may transition from the low level to the high level.
- the output of the latch 250 may be output as the first control signal CS 1 through the third inverter 263 . Accordingly, as marked by operation S 12 , the first control signal CS 1 may transition from the high level to the low level in response to the comparison signal CPS being set to the low level. As the first control signal CS 1 transitions from the high level to the low level, the gate driver 113 may transit the first drive signal DRV 1 from the high level to the low level. Accordingly, the first power transistor 111 may be turned on.
- the inductor LN and the capacitor “C” may be connected with the input node NI through the first power transistor 111 and may be charged by the input voltage VIN. Because a current flows through the switch node NSW, the zero current signal ZCS may transition from the high level to the low level.
- an output of the second OR gate 232 may maintain the high level.
- the fourth inverter 264 may invert the output of the second OR gate 232 to output the second control signal CS 2 . Accordingly, the second control signal CS 2 may maintain the low level.
- the gate driver 113 may maintain the second drive signal DRV 2 at the low level. Accordingly, the second power transistor 112 may be turned off.
- the inductor current IL may increase, and the output voltage VOUT may increase.
- the feedback voltage VFB may also increase.
- the comparison signal CPS may transition from the low level to the high level.
- an absolute value of a slope at which the feedback voltage VFB decreases when the feedback voltage VFB is not greater (e.g., less than or equal to) than the reference voltage VREF (or approaches to the reference voltage VREF within a preset (e.g., desired) voltage) may be smaller than an absolute value of a slope at which the feedback voltage VFB increases as the first power transistor 111 is turned on. That is, when the feedback voltage VFB is not greater (e.g., less than or equal to) than the reference voltage VREF (or approaches to the reference voltage VREF within a preset (e.g., desired) voltage), the feedback voltage VFB may decrease relatively slowly.
- the comparator 122 may transit the comparison signal CPS from the high level to the low level without a delay.
- the first signal generator 211 may transit the output signal S_ 211 from the low level to the high level.
- the non-reverse output Q_ 221 of the first flip-flop 221 may transition from the low level to the high level. Accordingly, the output signal of the first OR gate 231 may also transition from the low level to the high level.
- the output signal S_ 241 of the first AND gate 241 may transition from the low level to the high level after the second delay time TD 2 (e.g., an on-time) passes from when the comparison signal CPS is set to the low level “L”.
- the second delay time TD 2 e.g., an on-time
- an output signal of the second inverter 262 may transition from the high level to the low level.
- the latch 250 may be reset.
- the non-reverse output “Q” of the latch 250 may transition from the high level to the low level. That is, as marked by operation S 15 , after the second delay time TD 2 (e.g., an on-time) passes from when the comparison signal CPS is set to the low level, the first control signal CS 1 may transition to the high level “H”.
- the gate driver 113 may transit the first drive signal DRV 1 from the low level to the high level. Accordingly, the first power transistor 111 may be turned off.
- the output of the second OR gate 232 is set to the low level. That is, as marked by operation S 16 , after the second delay time TD 2 (e.g., an on-time) passes from when the comparison signal CPS is set to the low level “L”, the second control signal CS 2 may transition to the high level “H”.
- the second delay time TD 2 e.g., an on-time
- the gate driver 113 may transit the second drive signal DRV 2 from the low level to the high level. Accordingly, the second power transistor 112 may be turned on.
- the inductor current IL may decrease, and the feedback voltage VFB may decrease.
- a slope at which the feedback voltage VFB decreases may be variable in a first phase and a second phase.
- a decreasing slope of the first phase may be greater than a decreasing slope of the second phase.
- a decrease of the feedback voltage VFB may be caused by a decrease of the amount of inductor current IL.
- the second phase may start at a time when the amount of inductor current IL is smaller than the load current ILOAD.
- a decrease of the feedback voltage VFB may be caused by the load current ILOAD. Because the PFM mode is selected when the amount of load current ILOAD is small, the decrease of the feedback voltage VFB due to the load current ILOAD may be smaller than the decrease of the feedback voltage VFB due to the decrease of the inductor current IL.
- the zero current sensor 130 may transit the zero current signal ZCS from the low level to the high level.
- the output of the second OR gate 232 may transition from the low level to the high level. That is, as marked by operation S 17 , the second control signal CS 2 may be set to the low level “L” in response to the zero current signal ZCS being set to the high level “H”.
- the gate driver 113 may transit the second drive signal DRV 2 from the high level to the low level. Accordingly, the second power transistor 112 may be turned off.
- the second signal generator 212 may transit the output signal from the low level to the high level.
- the second pulse generator 272 may output a pulse.
- the first inverter 261 may invert the output pulse of the second pulse generator 272 and may transfer the inverted pulse to the reset input “R” of the second flip-flop 222 .
- the non-reverse output “Q” of the second flip-flop 222 may transition from the high level to the low level, and the reverse output /Q of the second flip-flop 222 may transition from the low level to the high level.
- the second signal generator 212 may not adjust the output signal when the non-reverse output “Q” of the second flip-flop 222 transitions to the low level. Also, because the output signal S_ 241 of the first AND gate 241 is set to the high level already at the third time T 3 , a low-to-high transition of the reverse output /Q_ 222 of the second flip-flop 222 may not affect the output signal S_ 242 of the second AND gate 242 .
- the voltage converter 100 may differently control the first power transistor 111 and the second power transistor 112 in a first time interval, a second time interval, and a third time interval of each period “P”.
- the first time interval may include a time interval from the first time T 1 to the third time T 3 .
- the voltage converter 100 may turn on the first power transistor 111 and may turn off the second power transistor 112 .
- the voltage converter 100 may increase the output voltage VOUT.
- the second time interval may include a time interval from the third time T 3 to the fourth time T 4 .
- the voltage converter 100 may turn off the first power transistor 111 and may turn on the second power transistor 112 .
- the voltage converter 100 may decrease the output voltage VOUT.
- the third time interval may include the remaining time interval of each period “P” other than the first time interval and the second time interval.
- the voltage converter 100 may turn off the first power transistor 111 and may turn off the second power transistor 112 .
- the voltage converter 100 may provide charges charged in the inductor LN or the capacitor “C” to the load current ILOAD.
- the voltage converter 100 may perform the PFM operation of adjusting a length of the period “P” by adjusting a length of the third time length. For example, as the load current ILOAD increases, the voltage converter 100 may decrease a length of the third time length, and thus, a length of the period “P” may decrease. In some example embodiments, where the length of the third time interval decreases, a time taken to provide charges charged during the same time to the load current ILOAD may decrease. That is, a charging interval may decrease.
- the voltage converter 100 may increase a length of the third time length, and thus, a length of the period “P” may increase.
- a time taken to provide charges charged during the same time to the load current ILOAD may increase. That is, a charging interval may increase.
- FIG. 7 illustrates an example of a procedure in which the control logic circuit 200 operates in the PWM mode.
- the control logic circuit 200 in operation S 310 , in response to the comparison signal CPS being set to the high level, the control logic circuit 200 may transit the first control signal CS 1 from the low level to the high level and may transit the second control signal CS 2 from the low level to the high level.
- the control logic circuit 200 may transit the first control signal CS 1 from the high level to the low level and may transit the second control signal CS 2 from the high level to the low level.
- FIG. 8 illustrates a method in which signals of the control logic circuit 200 are controlled in the PWM mode.
- FIG. 9 illustrates an example in which signals of the voltage converter 100 are controlled by the control logic circuit 200 in the PWM mode.
- a comparison of the feedback voltage VFB and the reference voltage VREF is shown.
- a comparison of the load current ILOAD and the inductor current IL is shown.
- a signal S_ 211 may be an output of the first signal generator 211 .
- a signal S_ 241 may be an output of the first AND gate 241 .
- a signal S_ 242 may be an output of the second AND gate 242 .
- a signal Q_ 222 may be the non-reverse output “Q” of the second flip-flop 222 .
- a signal /Q_ 222 may be the reverse output /Q of the second flip-flop 222 .
- a signal S_ 272 may be an output of the second pulse generator 272 .
- the output signal S_ 211 of the first signal generator 211 and the non-reverse output Q_ 221 of the first flip-flop 221 are omitted.
- the mode signal MODE may have the high level “H”. Accordingly, the output signal of the first OR gate 231 may be at the high level “H”. Because the output signal S_ 211 of the first signal generator 211 and the non-reverse output Q_ 221 of the first flip-flop 221 do not affect the output signal of the first OR gate 231 , the output signal S_ 211 and the non-reverse output Q_ 221 are omitted in FIG. 9 .
- the mode signal MODE may have the high level “H”. Accordingly, the output signal S_ 241 of the first AND gate 241 may follow the comparison signal CPS. For example, the output signal S_ 241 of the first AND gate 241 may be the same (or, similar, for example, within ⁇ 10%) as the comparison signal CPS.
- Each period may include a first time interval and a second time interval.
- the feedback voltage VFB and the inductor current IL may increase; during the second time interval, the feedback voltage VFB and the inductor current IL may decrease.
- the second time interval following the first time interval is described in the first period P 1
- the first time interval preceding the second time interval is described in the second period P 2 .
- the feedback voltage VFB may be greater than the reference voltage VREF.
- the comparator 122 may transit the comparison signal CPS from the low level to the high level.
- the fourth delay time TD 4 may be an operation delay of the comparator 122 .
- the fourth delay time TD 4 may be the same as or similar (e.g., within ⁇ 10%) to the first delay time TD 1 of FIG. 6 .
- the output signal S_ 241 of the first AND gate 241 may transition to the high level “H” in response to the comparison signal CPS being set to the high level “H”.
- the latch 250 may be reset in response to the output signal S_ 241 of the first AND gate 241 transitioning from the low level to the high level.
- the non-reverse output “Q” of the latch 250 may be set to the low level, and the first control signal CS 1 may transition from the low level to the high level. That is, as marked by operation S 22 , the first control signal CS 1 may be set to the high level in response to the comparison signal CPS being set to the high level “H”.
- the inductor current IL may have a positive value, and the zero current signal ZCS may maintain the low level. Accordingly, the output signal of the second OR gate 232 may follow the output signal of the latch 250 .
- the output signal of the second OR gate 232 may be the same (or, similar, for example, within ⁇ 10%) as the output signal of the latch 250 . Accordingly, as marked by operation S 23 , the second control signal CS 2 may be set to the high level “H” in response to the comparison signal CPS being set to the high level “H”.
- the non-reverse output Q_ 222 of the second flip-flop 222 may transition from the low level to the high level. Also, as marked by operation S 25 , the reverse output /Q_ 222 of the second flip-flop 222 may transition from the high level to the low level.
- the feedback voltage VFB may be smaller than the reference voltage VREF.
- the comparator 122 may transit the comparison signal CPS from the high level to the low level.
- the fifth delay time TD 5 may be an operation delay of the comparator 122 .
- the fifth delay time TD 5 may be the same as or similar (for example, within ⁇ 10%) to the first delay time TD 1 of FIG. 6 or the fourth delay time TD 4 of FIG. 9 .
- the output signal S_ 241 of the first AND gate 241 may transition to the low level “L”.
- the output signal of the second inverter 262 may transition from the low level to the high level.
- a sixth delay time TD 6 (e.g., an off-time) passes from when the comparison signal CPS is set to the high level, at a fifth time T 5 (as marked by operation S 27 ), the second signal generator 212 may transit the output signal from the low level to the high level.
- the second pulse generator 272 may output a pulse that transitions from the low level to the high level and then transitions from the high level to the low level.
- the first inverter 261 may invert the output pulse of the second pulse generator 272 and may transfer the inverted pulse to the reset input “R” of the second flip-flop 222 .
- the non-reverse output Q_ 222 of the second flip-flop 222 may transition from the high level to the low level.
- the reverse output /Q_ 222 of the second flip-flop 222 may transition from the low level to the high level.
- the second signal generator 212 may not adjust the output signal when the non-reverse output Q_ 222 of the second flip-flop 222 transitions to the low level. Also, because the output signal S_ 241 of the first AND gate 241 is set to the low level already at the fourth time T 4 , the output signal S_ 242 of the second AND gate 242 may transition from the low level to the high level in response to a low-to-high transition of the reverse output /Q_ 222 of the second flip-flop 222 . That is, the latch 250 may be set.
- the non-reverse output “Q” of the latch 250 may transition from the low level to the high level. That is, as marked by operation S 29 , after the sixth delay time TD 6 (e.g., an off-time) passes from when the comparison signal CPS is set to the high level “H”, the first control signal CS 1 may transition to the low level “L”. Also, as marked by operation S 30 , after the sixth delay time TD 6 (e.g., an off-time) passes from when the comparison signal CPS is set to the high level “H”, the second control signal CS 2 may transition to the low level “L”.
- the sixth delay time TD 6 e.g., an off-time
- a length (or a frequency) of the period “P” may be fixed.
- the voltage converter 100 may differently control the first power transistor 111 and the second power transistor 112 in a first time interval and a second time interval of each period “P”.
- the first time interval may precede the second time interval.
- the voltage converter 100 may turn on the first power transistor 111 and may turn off the second power transistor 112 .
- the voltage converter 100 may increase the output voltage VOUT.
- the second time interval may follow the first time interval.
- the voltage converter 100 may turn off the first power transistor 111 and may turn on the second power transistor 112 .
- the voltage converter 100 may decrease the output voltage VOUT.
- the voltage converter 100 may perform the PWM operation of adjusting a duty (or a duty ratio) in the period “P” by adjusting a length of the first time interval and a length of the second time interval. For example, as the load current ILOAD increases, the voltage converter 100 may increase a length of the first time interval and may decrease a length of the second time interval. In some example embodiments, where the length of the first time interval increases, a time allocated to charge the inductor LN and the capacitor “C” may increase.
- the voltage converter 100 may decrease a length of the first time interval and may increase a length of the second time interval. In some example embodiments, where the length of the first time interval decreases, a time allocated to charge the inductor LN and the capacitor “C” may decrease.
- FIG. 10 illustrates an example of a procedure in which the control logic circuit 200 enters the PWM mode from the PFM mode.
- the control logic circuit 200 in operation S 410 , in response to the comparison signal CPS being set to the high level, the control logic circuit 200 may transit the first control signal CS 1 to the high level and may transit the second control signal CS 2 from the high level.
- control logic circuit 200 may transit the first control signal CS 1 to the low level and may transit the second control signal CS 2 to the low level.
- FIG. 11 illustrates a method in which signals of the control logic circuit 200 are controlled in the process where the control logic circuit 200 enters the PWM mode from the PFM mode.
- FIG. 12 illustrates an example in which signals of the voltage converter 100 are controlled by the control logic circuit 200 in the process where the control logic circuit 200 enters the PWM mode from the PFM mode.
- a comparison of the feedback voltage VFB and the reference voltage VREF is shown.
- a comparison of the load current ILOAD and the inductor current IL is shown.
- a signal S_ 211 may be an output of the first signal generator 211 .
- a signal Q_ 221 may be the non-reverse output “Q” of the first flip-flop 221 .
- a signal S_ 241 may be an output of the first AND gate 241 .
- a signal S_ 242 may be an output of the second AND gate 242 .
- a signal Q_ 222 may be the non-reverse output “Q” of the second flip-flop 222 .
- a signal /Q_ 222 may be the reverse output /Q of the second flip-flop 222 .
- a signal S_ 272 may be an output of the second pulse generator 272 .
- the mode signal MODE may have the low level “L”.
- the third time interval may be removed.
- the first pulse generator 271 may output a pulse that transitions from the high level to the low level and then transitions from the low level to the high level.
- the non-reverse output Q_ 221 of the first flip-flop 221 may transition from the high level to the low level.
- the first signal generator 211 may transit the output signal S_ 211 from the low level to the high level.
- the non-reverse output Q_ 221 of the first flip-flop 221 may transition from the low level to the high level. Accordingly, the output signal of the first OR gate 231 may also transition from the low level to the high level. Because the comparison signal CPS is at the low level, the output signal S_ 241 of the first AND gate 241 may maintain the low level.
- the feedback voltage VFB may be greater than the reference voltage VREF.
- the comparison signal CPS may transition from the low level to the high level.
- the seventh delay time TD 7 may be an operation delay of the comparator 122 .
- the seventh delay time TD 7 may be the same as or similar (for example, within ⁇ 10%) to the first delay time TD 1 of FIG. 6 or the fourth delay time TD 4 or the fifth delay time TD 5 of FIG. 9 .
- the output signal S_ 241 of the first AND gate 241 may transition to the high level “H”.
- the latch 250 may be reset in response to the output signal S_ 241 of the first AND gate 241 transitioning from the low level to the high level.
- the first control signal CS 1 may transition to the high level “H”.
- the second control signal CS 2 may transition to the high level in response to the comparison signal CPS transitioning to the high level “H”.
- the non-reverse output Q_ 222 of the second flip-flop 222 may transition from the low level to the high level.
- the feedback voltage VFB may be smaller than the reference voltage VREF.
- the comparison signal CPS may transition from the high level to the low level.
- the eighth delay time TD 8 may be an operation delay of the comparator 122 .
- the eighth delay time TD 8 may be the same as or similar (for example, within ⁇ 10%) to the first delay time TD 1 of FIG. 6 , the fourth delay time TD 4 or the fifth delay time TD 5 of FIG. 9 , or the seventh delay time TD 7 of FIG. 12 .
- the output signal S_ 241 of the first AND gate 241 may transition to the low level “L”.
- the output signal of the second inverter 262 may transition to the high level.
- the output signal of the second signal generator 212 may transition from the low level to the high level.
- the second pulse generator 272 may output a pulse that transitions from the low level to the high level and then transitions from the high level to the low level. That is, as marked by operation S 36 , after the third delay time TD 3 (e.g., an off-time) passes from when the comparison signal CPS transitions to the high level “H”, the reverse output /Q of the second flip-flop 222 may transition to the high level “H”.
- the third delay time TD 3 e.g., an off-time
- the output of the second AND gate 242 may transition from the low level to the high level. That is, the latch 250 may be set. That is, as marked by operation S 37 , after the third delay time TD 3 (e.g., an off-time) passes from when the comparison signal CPS transitions to the high level “H”, the first control signal CS 1 may transition to the low level “L”.
- the third delay time TD 3 e.g., an off-time
- the second control signal CS 2 may transition to the low level “L”.
- the inductor current IL may be “0”. Accordingly, the zero current sensor 130 may transit the zero current signal ZCS from the low level to the high level. Afterwards, as the inductor current IL increases, the zero current sensor 130 may transit the zero current signal ZCS from the high level to the low level.
- a delay of an off-time that the second signal generator 212 provides in the PFM mode may correspond to the third delay time TD 3 .
- a delay of an off-time that the second signal generator 212 provides in the PWM mode may correspond to the sixth delay time TD 6 .
- the third delay time TD 3 may be longer than the sixth delay time TD 6 .
- a hysteresis may be provided in mode switching of the voltage converter 100 by making a length of the third delay time TD 3 and a length of the sixth delay time TD 6 different.
- the voltage converter 100 may control the first control signal CS 1 and the second control signal CS 2 based on an off-time of the sixth delay time TD 6 .
- the voltage converter 100 may enter the PWM mode.
- the voltage converter 100 may not enter the PWM mode until lengths of the first and second time intervals further increase to such an extent as to cause switching illustrated in FIG. 12 (e.g., switching based on the third delay time TD 3 ) (e.g., until the load current ILOAD further increases).
- a difference between the third delay time TD 3 and the sixth delay time TD 6 may act as a hysteresis when entering the PWM mode from the PFM mode. Accordingly, an operating mode may be prevented from being changed due to a transient voltage change, noise, or ripple. For example, the occurrence of an operating mode changing due to a transient voltage change, noise or ripple may be reduced or prevented.
- FIG. 13 illustrates the diode sensor 140 and a partial voltage converter 100 a associated with the diode sensor 140 .
- the diode sensor 140 may include a first transistor 141 , a second transistor 142 , a third transistor 143 , a first current source 144 , and a second current source 145 .
- the first transistor 141 is connected between (e.g., directly connected between) the switch node NSW and the first current source 144 .
- a gate of the first transistor 141 may be connected with a node between the second transistor 142 and the third transistor 143 .
- a signal of a node between the first transistor 141 and the first current source 144 may be output as the detection signal DS.
- the second transistor 142 and the third transistor 143 may be connected between (e.g., directly connected between) the second current source 145 and the ground node to which the ground voltage VSS is supplied.
- a gate of the second transistor 142 and a gate of the third transistor 143 may be connected with a node between the second transistor 142 and the second current source 145 .
- the second current source 145 , the second transistor 142 , and the third transistor 143 may supply a positive voltage, which is smaller (or less) than a threshold voltage of the first transistor 141 , to the gate of the first transistor 141 .
- a voltage belonging to a range from 0.2 V to 0.3 V may be supplied to the gate of the first transistor 141 .
- FIG. 14 illustrates examples in which the detection signal DS is activated.
- the inductor current IL may have a positive value.
- the gate driver 113 may control the first drive signal DRV 1 and the second drive signal DRV 2 so as to have a dead time.
- the gate driver 113 when turning on the first power transistor 111 and turning off the second power transistor 112 , the gate driver 113 may turn off the first power transistor 111 and may turn on the second power transistor 112 after a given (e.g., desired) time during which both the first power transistor 111 and the second power transistor 112 are turned off.
- the gate driver 113 may turn off the first power transistor 111 , and may turn on the second power transistor 112 after a given (e.g., desired) time during which both the first power transistor 111 and the second power transistor 112 are turned off.
- a waveform of the switch voltage VSW of the switch node NSW may change depending on a direction of the inductor current IL, for example, depending on whether the inductor current IL is a positive current or a negative current.
- the switch voltage VSW may be smaller than the ground voltage VSS for a moment.
- the switch voltage VSW may be smaller than the ground voltage VSS due to a parasitic diode coming from the second power transistor 112 .
- the switch voltage VSW When the switch voltage VSW is smaller than the ground voltage VSS, the switch voltage VSW and a gate voltage of the first transistor 141 may exceed a threshold voltage of the first transistor 141 . Accordingly, the first transistor 141 may be turned on, and the detection signal DS may transition to the low level.
- the first transistor 141 When the switch voltage VSW is equal to or greater than the ground voltage VSS, the first transistor 141 may be turned off. Accordingly, the detection signal DS may be of the high level.
- the inductor current IL may decrease. However, the inductor current IL may maintain a positive value even in the second state ST 2 , and the detection signal DS may periodically transition to the low level and may then be set to the high level.
- an interval where the inductor current IL is a negative current may occur.
- the switch voltage VSW may be greater than a voltage of the high level. For example, because a parasitic diode does not occur at the second power transistor 112 , the switch voltage VSW may become a positive voltage.
- FIG. 15 illustrates a mode control circuit 300 according to some example embodiments of the present disclosure.
- the mode control circuit 300 may correspond to the mode control circuit 150 of FIG. 1 .
- the mode control circuit 300 may include 11-th to 1n-th flip-flops 311 to 31 n, 21-th to 2n-th flip-flops 321 to 32 n (n being a positive integer), a third flip-flop 330 , a fourth flip-flop 340 , an AND gate 350 , a first inverter 361 , a second inverter 362 , a third inverter 363 , and a fourth inverter 364 .
- An inverted version of the first control signal CS 1 may be transferred to a clock input of the 11-th flip-flop 311 through the first inverter 361 .
- the detection signal DS may be transferred to a reset input “R” of the 11-th flip-flop 311 .
- a reverse output /Q of the 11-th flip-flop 311 may be transferred to a data input “D” of the 11-th flip-flop 311 .
- a reverse output /Q of the 1(k ⁇ 1)-th flip-flop 31 ( k ⁇ 1) may be transferred to a clock input of the 1k-th flip-flop 31 k (k being a positive integer being more than 1 and equal to or less than n).
- the detection signal DS may be transferred to a reset input “R” of the 1k-th flip-flop 31 k .
- a reverse output /Q of the 1k-th flip-flop 31 k may be transferred to a data input “D” of the 1k-th flip-flop 31 k.
- a reverse output /Q of the 1(n ⁇ 1)-th flip-flop 31 ( n ⁇ 1) may be transferred to a clock input of the 1n-th flip-flop 31 n .
- the detection signal DS may be transferred to a reset input “R” of the 1n-th flip-flop 31 n .
- a reverse output /Q of the 1n-th flip-flop 31 n may be transferred to a data input “D” of the 1n-th flip-flop 31 n .
- the non-reverse output “Q” of the 1n-th flip-flop 31 n may be transferred to the second inverter 362 .
- An output of the second inverter 362 may be transferred to the AND gate 350 and to the fourth flip-flop 340 as a PFM enable signal EN_PFM.
- a non-reverse output “Q” of the 2n-th flip-flop 32 n may be transferred to a clock input of the third flip-flop 330 .
- An inverted version of the zero current signal ZCS may be transferred to a reset input “R” of the third flip-flop 330 through the fourth inverter 364 .
- the power supply voltage VDD may be transferred to a data input “D” of the third flip-flop 330 .
- a non-reverse output “Q” of the third flip-flop 330 may be transferred to the AND gate 350 as a PWM enable signal EN_PWM.
- the AND gate 350 may receive the output signal of the second inverter 362 and the PWM enable signal EN_PWM. An output of the AND gate 350 may be transferred to a clock input of the fourth flip-flop 340 .
- the PFM enable signal EN_PFM may be transferred to a reset input “R” of the fourth flip-flop 340 .
- the power supply voltage VDD may be transferred to a data input “D” of the fourth flip-flop 340 .
- a non-reverse output “Q” of the fourth flip-flop 340 may be the mode signal MODE.
- the 11-th to 1n-th flip-flops 311 to 31 n may be released from a reset state.
- the 11-th to 1n-th flip-flops 311 to 31 n may be reset at the same time.
- the reverse output /Q or the data input “D” of each of the 11-th to 1n-th flip-flops 311 to 31 n may be set to the high level.
- the 11-th to 1n-th flip-flops 311 to 31 n may be released from a reset state.
- the 11-th to 1n-th flip-flops 311 to 31 n may constitute a divider.
- a frequency of the 1k-th flip-flop 31 k may be 1/(2 ⁇ circumflex over ( ) ⁇ k) times a frequency of the first control signal CS 1 .
- the non-reverse output “Q” of the 1n-th flip-flop 31 n may transition from the low level to the high level.
- the PFM enable signal EN_PFM may transition from the high level to the low level. Accordingly, the fourth flip-flop 340 may be reset, and the mode signal MODE may be set to the low level.
- the first control signal CS 1 toggles, like the first state ST 1 or the second state ST 2 , when the load current ILOAD increases and thus the detection signal DS is set the low level, all the 11-th to 1n-th flip-flops 311 to 31 n may be reset. That is, only in some example embodiments, where the detection signal DS is not generated while the first control signal CS 1 toggles as much as 2 ⁇ circumflex over ( ) ⁇ n periods, the voltage converter 100 may enter the PFM mode.
- the 2 ⁇ circumflex over ( ) ⁇ n periods may act as a hysteresis.
- the 21-th to 2n-th flip-flops 321 to 32 n may be simultaneously reset in response to the zero current signal ZCS being set to the high level.
- the zero current signal ZCS may be set to the high level, and the 21-th to 2n-th flip-flops 321 to 32 n may be reset.
- the zero current signal ZCS may maintain the low level.
- the second control signal CS 2 toggles during 2 ⁇ circumflex over ( ) ⁇ n periods in a state where the zero current signal ZCS maintains the low level
- the non-reverse output “Q” of the 2n-th flip-flop 32 n may transition from the low level to the high level.
- the non-reverse output “Q” of the 2n-th flip-flop 32 n transitioning to the high level
- the non-reverse output “Q” of the third flip-flop 330 that is, the PWM enable signal EN_PWM may transition from the low level to the high level.
- an output of the AND gate 350 may transition from the low level to the high level.
- the fourth flip-flop 340 may output the mode signal MODE of the high level.
- the second control signal CS 2 toggles, like the third state ST 3 , when the load current ILOAD decreases and thus the zero current signal ZCS is set the high level, all the 21-th to 2n-th flip-flops 321 to 32 n may be reset. That is, only in some example embodiments, where the zero current signal ZCS is not generated while the second control signal CS 2 toggles as much as 2 ⁇ circumflex over ( ) ⁇ n periods, the voltage converter 100 may enter the PWM mode.
- the 2 ⁇ circumflex over ( ) ⁇ n periods may act as a hysteresis.
- the mode control circuit 300 may maintain a current mode.
- the mode control circuit 300 may maintain a current mode.
- FIG. 16 illustrates a state diagram of the mode control circuit 150 .
- the mode control circuit 150 may select the PFM mode.
- the mode control circuit 150 may count periods of the second control signal CS 2 .
- the mode control circuit 150 may reset a count and may maintain the PFM mode.
- the mode control circuit 150 may select the PWM mode.
- the mode control circuit 150 may count periods of the first control signal CS 1 .
- the mode control circuit 150 may reset a count and may maintain the PWM mode.
- the mode control circuit 150 may select the PFM mode.
- FIG. 17 illustrates an electronic device 400 according to some example embodiments of the present disclosure.
- the electronic device 400 may be a storage device.
- the electronic device 400 may include a nonvolatile memory device 410 , a buffer memory 420 , a controller 430 , and a power management integrated circuit (PMIC) 440 .
- PMIC power management integrated circuit
- the nonvolatile memory device 410 may include at least one of various nonvolatile memory devices such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device.
- various nonvolatile memory devices such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device.
- the buffer memory 420 may include at least one of various random access memories such as a dynamic random access memory (DRAM), a static RAM, a phase-change RAM, a ferroelectric RAM, a magnetic RAM, and a resistive RAM.
- DRAM dynamic random access memory
- static RAM static RAM
- phase-change RAM phase-change RAM
- ferroelectric RAM ferroelectric RAM
- magnetic RAM magnetic RAM
- resistive RAM resistive RAM
- the controller 430 may operate under control of an external host device.
- the controller 430 may provide the external host device with at least a portion of a storage space of the nonvolatile memory device 410 .
- the controller 430 may use the buffer memory 420 for various purposes, for example, as a working memory for storing metadata or codes, a cache memory between a nonvolatile memory device and an external host device, or a buffer memory.
- the PMIC 440 may supply a power to the nonvolatile memory device 410 , the buffer memory 420 , and the controller 430 .
- the PMIC 440 may include the voltage converter 100 according to some example embodiments of the present disclosure.
- the PMIC 440 may supply a power to the nonvolatile memory device 410 , the buffer memory 420 , and the controller 430 in the PFM mode or the PWM mode.
- the PMIC 440 may select one of the PFM mode and the PWM mode depending on the amount of load current that is used in the nonvolatile memory device 410 , the buffer memory 420 , and the controller 430 . Accordingly, the power efficiency of the electronic device 400 may be improved.
- the blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software.
- ASIC application specific IC
- FPGA field programmable gate array
- CPLD complex programmable logic device
- the blocks may include circuits implemented with semiconductor elements in an integrated circuit or circuits enrolled as intellectual property (IP).
- IP intellectual property
- any of the devices, controllers, generators, decoders, units, modules, or the like may be included in, may include, and/or may be implemented by one or more instances of processing circuitry such as hardware including logic circuits, a hardware/software combination such as a processor executing software; or a combination thereof.
- said one or more instances of processing circuitry may include, but are not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphic processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC) a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC), etc.
- CPU central processing unit
- AP application processor
- ALU arithmetic logic unit
- GPU graphic processing unit
- DSP digital signal processor
- microcomputer a field programmable gate array
- FPGA field programmable gate array
- SoC System-on-Chip
- ASIC application-specific integrated circuit
- any of the memories, memory units, or the like as described herein may include a non-transitory computer readable storage device, for example a solid state drive (SSD), storing a program of instructions, and the one or more instances of processing circuitry may be configured to execute the program of instructions to implement the functionality of some or all of any of the devices, controllers, decoders, units, modules, or the like according to any of the example embodiments as described herein, including any of the methods of operating any of same as described herein.
- SSD solid state drive
- a voltage converter may operate in a pulse frequency modulation mode and a pulse width modulation mode depending on the amount of load current. Accordingly, voltage converters having improved power efficiency, storage devices including the voltage converter, and operating methods of the voltage converter are provided.
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Abstract
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KR1020200144168A KR20220059982A (en) | 2020-11-02 | 2020-11-02 | Voltage converter, storage device including voltage converter, and operating method of voltage converter |
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CN114448244A (en) | 2022-05-06 |
KR20220059982A (en) | 2022-05-11 |
US20220140728A1 (en) | 2022-05-05 |
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