US11853758B2 - Techniques for decoupled access-execute near-memory processing - Google Patents

Techniques for decoupled access-execute near-memory processing Download PDF

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US11853758B2
US11853758B2 US16/585,521 US201916585521A US11853758B2 US 11853758 B2 US11853758 B2 US 11853758B2 US 201916585521 A US201916585521 A US 201916585521A US 11853758 B2 US11853758 B2 US 11853758B2
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memory
circuitry
access
compute
data
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US20200026513A1 (en
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Berkin Akin
Alaa R. Alameldeen
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Intel Corp
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Intel Corp
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Priority to EP20181133.8A priority patent/EP3798828A3/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
US16/585,521 2019-09-27 2019-09-27 Techniques for decoupled access-execute near-memory processing Active 2041-04-03 US11853758B2 (en)

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Application Number Priority Date Filing Date Title
US16/585,521 US11853758B2 (en) 2019-09-27 2019-09-27 Techniques for decoupled access-execute near-memory processing
EP20181133.8A EP3798828A3 (de) 2019-09-27 2020-06-19 Techniken für entkoppelte zugriffsausführung in der nahspeicherverarbeitung
CN202010592587.5A CN112579487A (zh) 2019-09-27 2020-06-24 用于去耦合的存取-执行近存储器处理的技术
US18/388,797 US20240078112A1 (en) 2019-09-27 2023-11-10 Techniques for decoupled access-execute near-memory processing

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US16/585,521 US11853758B2 (en) 2019-09-27 2019-09-27 Techniques for decoupled access-execute near-memory processing

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US11853758B2 true US11853758B2 (en) 2023-12-26

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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
GB2594498B (en) * 2020-04-30 2022-06-01 Advanced Risc Mach Ltd Instruction scheduling
US11720360B2 (en) * 2020-09-11 2023-08-08 Apple Inc. DSB operation with excluded region

Citations (8)

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US6145073A (en) * 1998-10-16 2000-11-07 Quintessence Architectures, Inc. Data flow integrated circuit architecture
US6728873B1 (en) * 2000-06-06 2004-04-27 International Business Machines Corporation System and method for providing multiprocessor speculation within a speculative branch path
US7334110B1 (en) * 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
US7437521B1 (en) * 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US20130305022A1 (en) * 2012-05-14 2013-11-14 International Business Machines Corporation Speeding Up Younger Store Instruction Execution after a Sync Instruction
US20150149718A1 (en) 2009-07-21 2015-05-28 Tadao Nakamura A lower energy consumption and high speed computer system and a marching main memory adapted for the computer system, without the memory bottleneck
US20160041906A1 (en) 2013-09-21 2016-02-11 Oracle International Corporation Sharding of in-memory objects across numa nodes
US9678673B2 (en) * 2013-03-28 2017-06-13 Hewlett Packard Enterprise Development Lp Coordinating replication of data stored in a non-volatile memory-based system

Patent Citations (8)

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Publication number Priority date Publication date Assignee Title
US6145073A (en) * 1998-10-16 2000-11-07 Quintessence Architectures, Inc. Data flow integrated circuit architecture
US6728873B1 (en) * 2000-06-06 2004-04-27 International Business Machines Corporation System and method for providing multiprocessor speculation within a speculative branch path
US7334110B1 (en) * 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
US7437521B1 (en) * 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US20150149718A1 (en) 2009-07-21 2015-05-28 Tadao Nakamura A lower energy consumption and high speed computer system and a marching main memory adapted for the computer system, without the memory bottleneck
US20130305022A1 (en) * 2012-05-14 2013-11-14 International Business Machines Corporation Speeding Up Younger Store Instruction Execution after a Sync Instruction
US9678673B2 (en) * 2013-03-28 2017-06-13 Hewlett Packard Enterprise Development Lp Coordinating replication of data stored in a non-volatile memory-based system
US20160041906A1 (en) 2013-09-21 2016-02-11 Oracle International Corporation Sharding of in-memory objects across numa nodes

Non-Patent Citations (4)

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Title
European Office Action for Patent Application No. 20181133.8, dated Dec. 9, 2021, 7 pages.
European Second Office Action for Patent Application No. 20181133.8, dated Apr. 5, 2023, 8 pages.
Extended European Search Report for Patent Application No. 20181133.8, dated Mar. 12, 2021, 11 pages.
Won W Ro et al., "Design and evaluation of a hierarchical decoupled architecture" , The Journal of Supercomputing, Kluwer Academic Publishers, BO, vol. 38, No. 3, Dec. 2, 2006, pp. 237-259.

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Publication number Publication date
CN112579487A (zh) 2021-03-30
EP3798828A2 (de) 2021-03-31
US20200026513A1 (en) 2020-01-23
EP3798828A3 (de) 2021-04-14
US20240078112A1 (en) 2024-03-07

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