US11764742B2 - Switching amplifier with adaptive supply-voltage scaling - Google Patents

Switching amplifier with adaptive supply-voltage scaling Download PDF

Info

Publication number
US11764742B2
US11764742B2 US17/673,822 US202217673822A US11764742B2 US 11764742 B2 US11764742 B2 US 11764742B2 US 202217673822 A US202217673822 A US 202217673822A US 11764742 B2 US11764742 B2 US 11764742B2
Authority
US
United States
Prior art keywords
signal
switching amplifier
pwm
supply voltage
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/673,822
Other versions
US20230261620A1 (en
Inventor
Tai-Haur Kuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Cheng Kung University NCKU
Original Assignee
National Cheng Kung University NCKU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Cheng Kung University NCKU filed Critical National Cheng Kung University NCKU
Priority to US17/673,822 priority Critical patent/US11764742B2/en
Assigned to NATIONAL CHENG KUNG UNIVERSITY reassignment NATIONAL CHENG KUNG UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUO, TAI-HAUR
Publication of US20230261620A1 publication Critical patent/US20230261620A1/en
Application granted granted Critical
Publication of US11764742B2 publication Critical patent/US11764742B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0222—Continuous control by using a signal derived from the input signal
    • H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/185—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/462—Indexing scheme relating to amplifiers the current being sensed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/471—Indexing scheme relating to amplifiers the voltage being sensed

Definitions

  • the present invention relates to a switching amplifier, and more particularly, to a switching amplifier with adaptive supply-voltage scaling to relax the timing non-idealities on the output signal.
  • Switching amplifiers provide characteristics of power saving and high efficiency of output signals.
  • the output pulse-width modulation (PWM) signals are affected by timing non-idealities, which are induced by the PWM modulator and the switching power stage.
  • the timing non-idealities include clock jitter, dead time and rise/fall time mismatch, which may reduce a signal-to-noise ratio (SNR), a dynamic range (DR) and linearity of the output signals.
  • SNR signal-to-noise ratio
  • DR dynamic range
  • the present invention therefore provides a switching amplifier to solve the abovementioned problem.
  • a switching amplifier comprises a controller, configured to receive an input signal and a reference signal, and to generate a control signal according to the input signal and the reference signal; a pulse-width modulation (PWM) modulator, coupled to the controller, configured to generate a PWM signal according to the input signal and the control signal; a power management unit, coupled to the controller, configured to receive a power supply and the control signal, and to provide an adaptive supply voltage according to the power supply and the control signal; and a switching power stage, coupled to the power management unit and the PWM modulator, configured to generate an output signal according to the PWM signal and the adaptive supply voltage.
  • PWM pulse-width modulation
  • FIG. 1 is a schematic diagram of a switching amplifier according to the prior art.
  • FIG. 2 is a schematic diagram of a full-bridge switching power stage of a switching amplifier.
  • FIG. 3 shows waveforms of the single-ended signal of each output node and the differential-mode signal of the switching power stage in the switching amplifier according to the prior art.
  • FIG. 4 is a schematic diagram of a switching amplifier according to an example of the present invention.
  • FIG. 5 shows waveforms of the single-ended signal of each output node and the differential-mode signal of the switching power stage in the switching amplifier according to an example of the present invention.
  • FIG. 6 shows the dynamic range versus the clock jitter plots with a switching amplifier according to the prior art and a switching amplifier according to an example of the present invention.
  • FIG. 1 is a schematic diagram of a switching amplifier 10 according to the prior art.
  • the switching amplifier 10 includes a pulse-width modulation (PWM) modulator 100 , a switching power stage 110 , a power management unit 120 and a load 130 .
  • the PWM modulator 100 generates a PWM signal according to the input signal V IN .
  • the power management unit 120 provides a constant supply voltage V DD to supply the switching power stage 110 according to a power supply V line .
  • the power management unit 120 may not be necessary in some applications.
  • the switching power stage 110 may be supplied by the power supply V line (i.e., the supply voltage V DD ) instead of being supplied by the power management unit 120 .
  • the switching power stage 110 generates an output signal V O according to the PWM signal and the supply voltage V DD , and drives the load 130 .
  • the switching power stage 110 comprises a plurality of power switches.
  • the switching power stage 110 may be a half-bridge topology or a full-bridge topology according to the arrangement of the plurality of power switches.
  • the switching amplifier 10 may be an open-loop configuration, or may be a closed-loop configuration if the output signal V O is fed back to the PWM modulator 100 .
  • FIG. 2 is a schematic diagram of a full bridge switching power stage 20 of a switching amplifier.
  • the full-bridge power stage 20 includes power switches M 1 , M 2 , M 3 and M 4 .
  • a signal modulated by a PWM modulator (e.g., the PWM modulator 100 ) drives the power switches M 1 , M 2 , M 3 and M 4 .
  • the power switches M 1 and M 2 are coupled to an output node V O,A
  • the power switches M 3 and M 4 are coupled to an output node V O,B .
  • the output nodes V O,A and V O,B are coupled to a supply voltage V DD , or are coupled to ground.
  • a differential-mode signal V O,diff is derived according to voltage differences of the output nodes V O,A and V O,B , and is coupled to a load 200 for outputting the signal.
  • FIG. 3 shows waveforms of the single-ended signal of each output node V O,A and V O,B and the differential-mode signal V O,diff of the switching power stage 110 in the switching amplifier 10 according to the prior art.
  • the switching power stage 110 may be the full-bridge switching power stage 20 , but is not limited thereto.
  • a plurality of pulse widths of the differential-mode signal V O,diff are changed according to the input signal V IN under the condition of the fixed supply voltage V DD .
  • the plurality of pulse widths of the differential-mode signal V O,diff become narrow when the input signal V IN is small (e.g., an absolute value of the input signal V IN is smaller than a reference signal V REF )
  • the timing non-idealities at the edges of the PWM signal occupy a large proportion to the differential-mode signal V O,diff .
  • the differential-mode signal V O,diff with narrow pulse widths may be easily affected by the timing non-idealities, which may reduce the SNR of the output signal and correspondingly degrades the dynamic range (DR) of the switching amplifier 10 .
  • FIG. 4 is a schematic diagram of a switching amplifier 40 according to an example of the present invention.
  • the switching amplifier 40 includes a controller 400 , a PWM modulator 410 , a power management unit 420 , a switching power stage 430 and a load 440 .
  • the controller 400 is configured to receive an input signal V IN and a reference signal V REF , and to generate a control signal V ctrl to the power management unit 420 and the PWM modulator 410 .
  • the PWM modulator 410 is coupled to the controller 400 , and is configured to generate a PWM signal according to the input signal V IN and the control signal V ctrl
  • the power management unit 420 is coupled to the controller 400 , and is configured to provide an adaptive supply voltage V DD according to a power supply V line and the control signal V ctrl
  • the switching power stage 430 is coupled to the power management unit 420 and the PWM modulator 410 , and is configured to generate an output signal V O according to the PWM signal and the adaptive supply voltage V DD . Then, the switching power stage 430 drives the output signal V O to the load 440 .
  • the switching power stage 430 includes a plurality of power switches.
  • the switching power stage 430 may be a half-bridge topology or a full-bridge topology according to the arrangement of the power switches.
  • the switching amplifier 40 may be an open-loop configuration, or may be a closed-loop configuration if the output signal V O is fed back to the PWM modulator 410 . That is, compared with the switching amplifier 10 according to the prior art, the switching amplifier 40 includes the controller 400 to affect the PWM signal generated by the PWM modulator 410 and the adaptive supply voltage V DD provided by the power management unit 420 .
  • a plurality of pulse widths of the PWM signal and the adaptive supply voltage V DD may be adjusted according to the control signal V ctrl under a condition that the power difference between the output signal V O and the input signal V IN remains unchanged.
  • FIG. 5 shows waveforms of the single-ended signal of each output node V O,A and V O,B and the differential-mode signal V O,diff of the switching power stage 430 in the switching amplifier 40 according to an example of the present invention.
  • the switching power stage 430 may be the full-bridge switching power stage 20 , but is not limited thereto.
  • the small input signal V IN e.g., an absolute value of the input signal V IN is smaller than the reference signal V REF
  • the plurality of pulse widths of the differential-mode signal V O,diff are doubled and the adaptive supply voltage V DD is halved (e.g., V DD /2).
  • the plurality of pulse widths of the differential-mode signal V O,diff are wider so as to reduce the effect of timing non-idealities.
  • the adaptive supply voltage V DD is lowered accordingly, which maintains the power of the differential-mode signal V O,diff the same as the power of the input signal V IN .
  • an adjustment of the plurality of pulse widths of the PWM signal may be slightly affected.
  • FIG. 6 shows the dynamic range versus the clock jitter plots with a switching amplifier 10 according to the prior art and a switching amplifier 40 according to an example of the present invention.
  • the clock jitter effect is relaxed by two-times, four-times and eight-times when the adaptive supply voltage V DD of the switching amplifier 40 is scaled down to half, one-fourth and one-eighth of V DD , respectively.
  • the controller 400 may detect a voltage or a current of the input signal V IN .
  • the adaptive supply voltage V DD and a plurality of pulse widths of the PWM signal may be determined according to whether an absolute value of the input signal V IN is smaller than the reference signal V REF .
  • the reference signal V REF includes (e.g., may be) at least one value, and the adaptive supply voltage V DD may be changed according to the input signal V IN and the at least one value of the reference signal V REF .
  • the reference signal V REF may include 8 values.
  • the adaptive supply voltage may be changed according to the 8 values of the reference signal V REF .
  • the adaptive supply voltage V DD is halved and the plurality of pulse widths of the PWM signal are doubled, if the absolute value of the input signal V IN is smaller than the reference signal V REF .
  • the adaptive supply voltage V DD and the plurality of pulse widths of the PWM signal are not changed, if the absolute value of the input signal V IN is not smaller than the reference signal V REF . That is, for small input signals (e.g., the absolute value of the input signal V IN is smaller than the reference signal V REF ) the plurality of pulse widths of the PWM signal are widened and the adaptive supply voltage V DD is lowered accordingly, which reduces the effect of timing non-idealities and maintains the power of the output signal unchanged.
  • the plurality of pulse widths of the PWM signal and the adaptive supply voltage maintains unchanged (i.e., the same as the supply voltage of the switching amplifier 10 according to the prior art).
  • an adjustment of the plurality of pulse widths of the PWM signal and an adjustment of the adaptive supply voltage V DD are complementary.
  • the adaptive supply voltage V DD may be reduced to V DD /3, and the plurality of pulse widths of the PWM signal may be tripled, but is not limited thereto.
  • the input signal V IN includes a digital signal (e.g. a pulse-code modulation (PCM) signal represented by a plurality of bits) or an analog signal, but is not limited thereto.
  • PCM pulse-code modulation
  • the power supply includes (e.g., may be) a direct-current (DC) power supply. In one example, the power supply includes (e.g., may be) an alternating-current (AC) power supply.
  • DC direct-current
  • AC alternating-current
  • the power management unit 420 includes a DC-DC buck converter, a DC-DC boost converter, a DC-DC buck-boost converter, or a low-dropout regulator (LDO) but is not limited thereto.
  • LDO low-dropout regulator
  • the output signal V O is not fed back to the PWM modulator 410 . That is, the switching amplifier 40 may be an open-loop configuration. The switching power stage 430 does not transmit the output signal V O back to the PWM modulator 410 .
  • the output signal V O is fed back to the PWM modulator 410 .
  • the switching amplifier 40 may be a closed-loop configuration with a feedback path from the switching power stage 430 to the PWM modulator 410 .
  • the switching power stage 430 transmits the output signal V O back to the PWM modulator 410 .
  • the PWM modulator 410 may generate the PWM signal according to the input signal V IN , the output signal V O , and the control signal V ctrl .
  • the switching amplifier 40 may be applied to audio applications. That is, the load 440 may be a speaker, but is not limited thereto.
  • the present invention provides a switching amplifier with adaptive supply-voltage scaling.
  • the pulse widths of the PWM signal and the adaptive supply voltage of the switching power stage are adjusted accordingly to reduce the timing non-idealities effect on the output signal.

Abstract

A switching amplifier comprises a controller, configured to receive an input signal and a reference signal, and to generate a control signal according to the input signal and the reference signal; a pulse-width modulation (PWM) modulator, coupled to the controller, configured to generate a PWM signal according to the input signal and the control signal; a power management unit, coupled to the controller, configured to receive a power supply and the control signal, and to provide an adaptive supply voltage according to the power supply and the control signal; and a switching power stage, coupled to the power management unit and the PWM modulator, configured to generate an output signal according to the PWM signal and the adaptive supply voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a switching amplifier, and more particularly, to a switching amplifier with adaptive supply-voltage scaling to relax the timing non-idealities on the output signal.
2. Description of the Prior Art
Switching amplifiers provide characteristics of power saving and high efficiency of output signals. However, the output pulse-width modulation (PWM) signals are affected by timing non-idealities, which are induced by the PWM modulator and the switching power stage. The timing non-idealities include clock jitter, dead time and rise/fall time mismatch, which may reduce a signal-to-noise ratio (SNR), a dynamic range (DR) and linearity of the output signals. Thus, how to reduce the timing non-idealities of the switching amplifier is a problem to be solved.
SUMMARY OF THE INVENTION
The present invention therefore provides a switching amplifier to solve the abovementioned problem.
A switching amplifier comprises a controller, configured to receive an input signal and a reference signal, and to generate a control signal according to the input signal and the reference signal; a pulse-width modulation (PWM) modulator, coupled to the controller, configured to generate a PWM signal according to the input signal and the control signal; a power management unit, coupled to the controller, configured to receive a power supply and the control signal, and to provide an adaptive supply voltage according to the power supply and the control signal; and a switching power stage, coupled to the power management unit and the PWM modulator, configured to generate an output signal according to the PWM signal and the adaptive supply voltage.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a switching amplifier according to the prior art.
FIG. 2 is a schematic diagram of a full-bridge switching power stage of a switching amplifier.
FIG. 3 shows waveforms of the single-ended signal of each output node and the differential-mode signal of the switching power stage in the switching amplifier according to the prior art.
FIG. 4 is a schematic diagram of a switching amplifier according to an example of the present invention.
FIG. 5 shows waveforms of the single-ended signal of each output node and the differential-mode signal of the switching power stage in the switching amplifier according to an example of the present invention.
FIG. 6 shows the dynamic range versus the clock jitter plots with a switching amplifier according to the prior art and a switching amplifier according to an example of the present invention.
 DETAILED DESCRIPTION
FIG. 1 is a schematic diagram of a switching amplifier 10 according to the prior art. The switching amplifier 10 includes a pulse-width modulation (PWM) modulator 100, a switching power stage 110, a power management unit 120 and a load 130. The PWM modulator 100 generates a PWM signal according to the input signal VIN. The power management unit 120 provides a constant supply voltage VDD to supply the switching power stage 110 according to a power supply Vline. The power management unit 120 may not be necessary in some applications.
The switching power stage 110 may be supplied by the power supply Vline (i.e., the supply voltage VDD) instead of being supplied by the power management unit 120. The switching power stage 110 generates an output signal VO according to the PWM signal and the supply voltage VDD, and drives the load 130. The switching power stage 110 comprises a plurality of power switches. The switching power stage 110 may be a half-bridge topology or a full-bridge topology according to the arrangement of the plurality of power switches. The switching amplifier 10 may be an open-loop configuration, or may be a closed-loop configuration if the output signal VO is fed back to the PWM modulator 100.
FIG. 2 is a schematic diagram of a full bridge switching power stage 20 of a switching amplifier. The full-bridge power stage 20 includes power switches M1, M2, M3 and M4. A signal modulated by a PWM modulator (e.g., the PWM modulator 100) drives the power switches M1, M2, M3 and M4. The power switches M1 and M2 are coupled to an output node VO,A, and the power switches M3 and M4 are coupled to an output node VO,B. The output nodes VO,A and VO,B are coupled to a supply voltage VDD, or are coupled to ground. A differential-mode signal VO,diff is derived according to voltage differences of the output nodes VO,A and VO,B, and is coupled to a load 200 for outputting the signal.
FIG. 3 shows waveforms of the single-ended signal of each output node VO,A and VO,B and the differential-mode signal VO,diff of the switching power stage 110 in the switching amplifier 10 according to the prior art. The switching power stage 110 may be the full-bridge switching power stage 20, but is not limited thereto. As shown in FIG. 3 , a plurality of pulse widths of the differential-mode signal VO,diff are changed according to the input signal VIN under the condition of the fixed supply voltage VDD. Thus, the plurality of pulse widths of the differential-mode signal VO,diff become narrow when the input signal VIN is small (e.g., an absolute value of the input signal VIN is smaller than a reference signal VREF) The timing non-idealities at the edges of the PWM signal occupy a large proportion to the differential-mode signal VO,diff. As a result, the differential-mode signal VO,diff with narrow pulse widths may be easily affected by the timing non-idealities, which may reduce the SNR of the output signal and correspondingly degrades the dynamic range (DR) of the switching amplifier 10.
FIG. 4 is a schematic diagram of a switching amplifier 40 according to an example of the present invention. The switching amplifier 40 includes a controller 400, a PWM modulator 410, a power management unit 420, a switching power stage 430 and a load 440. The controller 400 is configured to receive an input signal VIN and a reference signal VREF, and to generate a control signal Vctrl to the power management unit 420 and the PWM modulator 410. The PWM modulator 410 is coupled to the controller 400, and is configured to generate a PWM signal according to the input signal VIN and the control signal Vctrl The power management unit 420 is coupled to the controller 400, and is configured to provide an adaptive supply voltage VDD according to a power supply Vline and the control signal Vctrl The switching power stage 430 is coupled to the power management unit 420 and the PWM modulator 410, and is configured to generate an output signal VO according to the PWM signal and the adaptive supply voltage VDD. Then, the switching power stage 430 drives the output signal VO to the load 440. The switching power stage 430 includes a plurality of power switches. The switching power stage 430 may be a half-bridge topology or a full-bridge topology according to the arrangement of the power switches. The switching amplifier 40 may be an open-loop configuration, or may be a closed-loop configuration if the output signal VO is fed back to the PWM modulator 410. That is, compared with the switching amplifier 10 according to the prior art, the switching amplifier 40 includes the controller 400 to affect the PWM signal generated by the PWM modulator 410 and the adaptive supply voltage VDD provided by the power management unit 420. A plurality of pulse widths of the PWM signal and the adaptive supply voltage VDD may be adjusted according to the control signal Vctrl under a condition that the power difference between the output signal VO and the input signal VIN remains unchanged.
FIG. 5 shows waveforms of the single-ended signal of each output node VO,A and VO,B and the differential-mode signal VO,diff of the switching power stage 430 in the switching amplifier 40 according to an example of the present invention. The switching power stage 430 may be the full-bridge switching power stage 20, but is not limited thereto. As shown in FIG. 5 , for the small input signal VIN (e.g., an absolute value of the input signal VIN is smaller than the reference signal VREF) the plurality of pulse widths of the differential-mode signal VO,diff are doubled and the adaptive supply voltage VDD is halved (e.g., VDD/2). That is, compared with the waveforms of the switching amplifier 10 according to the prior art (please refer to the waveforms in FIG. 3 ), when the input signal VIN is small, the plurality of pulse widths of the differential-mode signal VO,diff are wider so as to reduce the effect of timing non-idealities. The adaptive supply voltage VDD is lowered accordingly, which maintains the power of the differential-mode signal VO,diff the same as the power of the input signal VIN. In addition, due to impedance change of the power switches with different adaptive supply voltage VDD, an adjustment of the plurality of pulse widths of the PWM signal may be slightly affected.
FIG. 6 shows the dynamic range versus the clock jitter plots with a switching amplifier 10 according to the prior art and a switching amplifier 40 according to an example of the present invention. As can be seen, the clock jitter effect is relaxed by two-times, four-times and eight-times when the adaptive supply voltage VDD of the switching amplifier 40 is scaled down to half, one-fourth and one-eighth of VDD, respectively.
In one example, the controller 400 may detect a voltage or a current of the input signal VIN.
In one example, the adaptive supply voltage VDD and a plurality of pulse widths of the PWM signal may be determined according to whether an absolute value of the input signal VIN is smaller than the reference signal VREF.
In one example, the reference signal VREF includes (e.g., may be) at least one value, and the adaptive supply voltage VDD may be changed according to the input signal VIN and the at least one value of the reference signal VREF. For example, the reference signal VREF may include 8 values. The adaptive supply voltage may be changed according to the 8 values of the reference signal VREF.
In one example, the adaptive supply voltage VDD is halved and the plurality of pulse widths of the PWM signal are doubled, if the absolute value of the input signal VIN is smaller than the reference signal VREF. In one example, the adaptive supply voltage VDD and the plurality of pulse widths of the PWM signal are not changed, if the absolute value of the input signal VIN is not smaller than the reference signal VREF. That is, for small input signals (e.g., the absolute value of the input signal VIN is smaller than the reference signal VREF) the plurality of pulse widths of the PWM signal are widened and the adaptive supply voltage VDD is lowered accordingly, which reduces the effect of timing non-idealities and maintains the power of the output signal unchanged. On the other hand, for large input signals (e.g., the absolute value of the input signal VIN is not smaller than the reference signal VREF) the plurality of pulse widths of the PWM signal and the adaptive supply voltage maintains unchanged (i.e., the same as the supply voltage of the switching amplifier 10 according to the prior art).
In one example, an adjustment of the plurality of pulse widths of the PWM signal and an adjustment of the adaptive supply voltage VDD are complementary. For example, the adaptive supply voltage VDD may be reduced to VDD/3, and the plurality of pulse widths of the PWM signal may be tripled, but is not limited thereto.
In one example, the input signal VIN includes a digital signal (e.g. a pulse-code modulation (PCM) signal represented by a plurality of bits) or an analog signal, but is not limited thereto.
In one example, the power supply includes (e.g., may be) a direct-current (DC) power supply. In one example, the power supply includes (e.g., may be) an alternating-current (AC) power supply.
In one example, the power management unit 420 includes a DC-DC buck converter, a DC-DC boost converter, a DC-DC buck-boost converter, or a low-dropout regulator (LDO) but is not limited thereto.
In one example, the output signal VO is not fed back to the PWM modulator 410. That is, the switching amplifier 40 may be an open-loop configuration. The switching power stage 430 does not transmit the output signal VO back to the PWM modulator 410.
In one example, the output signal VO is fed back to the PWM modulator 410. That is, the switching amplifier 40 may be a closed-loop configuration with a feedback path from the switching power stage 430 to the PWM modulator 410. The switching power stage 430 transmits the output signal VO back to the PWM modulator 410. The PWM modulator 410 may generate the PWM signal according to the input signal VIN, the output signal VO, and the control signal Vctrl.
In one example, the switching amplifier 40 may be applied to audio applications. That is, the load 440 may be a speaker, but is not limited thereto.
To sum up, the present invention provides a switching amplifier with adaptive supply-voltage scaling. The pulse widths of the PWM signal and the adaptive supply voltage of the switching power stage are adjusted accordingly to reduce the timing non-idealities effect on the output signal.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (14)

What is claimed is:
1. A switching amplifier, comprising:
a controller, configured to receive an input signal and a reference signal, and to generate a control signal according to the input signal and the reference signal;
a pulse-width modulation (PWM) modulator, coupled to the controller, configured to generate a PWM signal according to the input signal and the control signal;
a power management unit, coupled to the controller, configured to receive a power supply and the control signal, and to provide an adaptive supply voltage according to the power supply and the control signal; and
a switching power stage, coupled to the power management unit and the PWM modulator, configured to generate an output signal according to the PWM signal and the adaptive supply voltage;
wherein the controller generates the control signal to adjust a plurality of pulse widths of the PWM signal and the adaptive supply voltage, and an adjustment of the plurality of pulse widths of the PWM signal and an adjustment of the adaptive supply voltage are complementary.
2. The switching amplifier of claim 1, wherein the controller detects a voltage or a current of the input signal.
3. The switching amplifier of claim 1, wherein the switching power stage comprises a plurality of power switches.
4. The switching amplifier of claim 1, wherein the switching power stage comprises a half-bridge topology or a full-bridge topology.
5. The switching amplifier of claim 1, wherein the reference signal comprises at least one value, and the adaptive supply voltage is changed according to the input signal and the at least one value of the reference signal.
6. The switching amplifier of claim 1, wherein the adaptive supply voltage and the plurality of pulse widths of the PWM signal are determined according to whether an absolute value of the input signal is smaller than the reference signal.
7. The switching amplifier of claim 6, wherein the adaptive supply voltage is halved and the plurality of pulse widths of the PWM signal are doubled, if the absolute value of the input signal is smaller than the reference signal.
8. The switching amplifier of claim 6, wherein the adaptive supply voltage and the plurality of pulse widths of the PWM signal are not changed, if the absolute value of the input signal is not smaller than the reference signal.
9. The switching amplifier of claim 1, wherein the input signal comprises a digital signal or an analog signal.
10. The switching amplifier of claim 1, wherein the power supply comprises a direct-current (DC) power supply.
11. The switching amplifier of claim 1, wherein the power supply comprises an alternating-current (AC) power supply.
12. The switching amplifier of claim 1, wherein the power management unit comprises a DC-DC buck converter, a DC-DC boost converter, a DC-DC buck-boost converter or a low-dropout regulator (LDO).
13. The switching amplifier of claim 1, wherein the output signal is not fed back to the PWM modulator.
14. The switching amplifier of claim 1, wherein the output signal is fed back to the PWM modulator.
US17/673,822 2022-02-17 2022-02-17 Switching amplifier with adaptive supply-voltage scaling Active US11764742B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/673,822 US11764742B2 (en) 2022-02-17 2022-02-17 Switching amplifier with adaptive supply-voltage scaling

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17/673,822 US11764742B2 (en) 2022-02-17 2022-02-17 Switching amplifier with adaptive supply-voltage scaling

Publications (2)

Publication Number Publication Date
US20230261620A1 US20230261620A1 (en) 2023-08-17
US11764742B2 true US11764742B2 (en) 2023-09-19

Family

ID=87558148

Family Applications (1)

Application Number Title Priority Date Filing Date
US17/673,822 Active US11764742B2 (en) 2022-02-17 2022-02-17 Switching amplifier with adaptive supply-voltage scaling

Country Status (1)

Country Link
US (1) US11764742B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763811B2 (en) * 2018-07-25 2020-09-01 Cirrus Logic, Inc. Gain control in a class-D open-loop amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763811B2 (en) * 2018-07-25 2020-09-01 Cirrus Logic, Inc. Gain control in a class-D open-loop amplifier

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Jia-Ming Liu, Shih-Hsiung Chien, and Tai-Haur Kuo, "A 100 W 5.1-Channel Digital Class-D Audio Amplifier with Single-Chip Design," IEEE J. Solid-State Circuits, vol. 47, No. 6, pp. 1344-1354, Jun. 2012.
Yi-Zhi Qiu, Shih-Hsiung Chien, and Tai-Haur Kuo, "A 0.4-mA-Quiescent-Current, 0.00091%-THD+N Class-D Audio Amplifier with Low-Complexity Frequency Equalization for PWM-Residual-Aliasing Reduction," IEEE J. Solid-State Circuits, vol. 57, No. 2, pp. 423-433, Feb. 2022.

Also Published As

Publication number Publication date
US20230261620A1 (en) 2023-08-17

Similar Documents

Publication Publication Date Title
US10250135B2 (en) Fast response control circuit and control method thereof
US7923977B2 (en) DC-DC converters with transient response control
JP6001658B2 (en) Primary voltage sensing and control for converters
US8253395B2 (en) Bus voltage optimizer for switched power converter
TWI496387B (en) Switching regulator and control circuit and control method thereof
US7026800B2 (en) Feed-forward method for improving a transient response for a DC—DC power conversion and DC—DC voltage converter utilizing the same
US7772904B1 (en) Voltage level converter with mixed signal controller
JP5889307B2 (en) Switched mode power converter apparatus using bridge topology and control method thereof
US7741914B1 (en) Amplifier system with dynamically-adjusted supply voltage
TWI462439B (en) A kind of switch control circuit and the method thereof
US20140125306A1 (en) Switching Regulator Control with Nonlinear Feed-Forward Correction
TWI426689B (en) Switching regulator and control circuit and control method thereof
TWI419453B (en) Voltage converters and voltage generating methods
TWI474146B (en) Apparatus, controller, system and method for generating pwm control signal
US20110109398A1 (en) Fixed-frequency control circuit and method for pulse width modulation
US7688050B2 (en) Switching power supply controller with unidirectional transient gain change
US9900938B2 (en) LED lighting circuit with ripple reducer
TWI483531B (en) Power converter and operating method thereof
US10749433B2 (en) Current balance feedback circuit and method to improve the stability of a multi-phase converter
TWI435519B (en) Power converterhome and controlling methd using the same
US11764742B2 (en) Switching amplifier with adaptive supply-voltage scaling
US9146575B2 (en) Power converter and operating method thereof
US11081957B2 (en) Power converter with multi-mode timing control
JP4289422B2 (en) AC power supply device and integrated circuit for AC power supply device
CN217741558U (en) Loop compensation circuit applied to two-stage LC switching power supply and switching power supply device

Legal Events

Date Code Title Description
AS Assignment

Owner name: NATIONAL CHENG KUNG UNIVERSITY, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KUO, TAI-HAUR;REEL/FRAME:059029/0241

Effective date: 20220216

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO SMALL (ORIGINAL EVENT CODE: SMAL); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE