US11733606B2 - Method for performing a manufacturing process and associated apparatuses - Google Patents

Method for performing a manufacturing process and associated apparatuses Download PDF

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US11733606B2
US11733606B2 US16/972,073 US201916972073A US11733606B2 US 11733606 B2 US11733606 B2 US 11733606B2 US 201916972073 A US201916972073 A US 201916972073A US 11733606 B2 US11733606 B2 US 11733606B2
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features
patterning
structures
sub
setting
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US20210240073A1 (en
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Thomas Theeuwes
Koenraad VAN INGEN SCHENAU
Pieter Joseph Marie WÖLTGENS
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ASML Netherlands BV
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70283—Mask effects on the imaging process
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Definitions

  • the present invention relates to methods and apparatus for applying patterns to a substrate in a lithographic process.
  • a lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate.
  • a lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs).
  • a patterning device which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC.
  • This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate.
  • resist radiation-sensitive material
  • a single substrate will contain a network of adjacent target portions that are successively patterned.
  • lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning” ⁇ direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
  • parameters of the patterned substrate are measured.
  • Parameters may include, for example, the overlay error between successive layers formed in or on the patterned substrate and critical linewidth (CD) of developed photosensitive resist. This measurement may be performed on a product substrate and/or on a dedicated metrology target.
  • CD critical linewidth
  • a fast and non-invasive form of specialized inspection tool is a scatterometer in which a beam of radiation is directed onto a target on the surface of the substrate and properties of the scattered or reflected beam are measured. Two main types of scatterometer are known.
  • Spectroscopic scatterometers direct a broadband radiation beam onto the substrate and measure the spectrum (intensity as a function of wavelength) of the radiation scattered into a particular narrow angular range.
  • Angularly resolved scatterometers use a monochromatic radiation beam and measure the intensity of the scattered radiation as a function of angle.
  • Examples of known scatterometers include angle-resolved scatterometers of the type described in US2006033921A1 and US2010201963A1.
  • the targets used by such scatterometers are relatively large, e.g., 40 ⁇ m by 40 ⁇ m, gratings and the measurement beam generates a spot that is smaller than the grating (i.e., the grating is underfilled).
  • diffraction based overlay can be measured using such apparatus, as described in published patent application US2006066855A1. Diffraction-based overlay metrology using dark-field imaging of the diffraction orders enables overlay measurements on smaller targets.
  • Examples of dark field imaging metrology can be found in international patent applications WO 2009/078708 and WO 2009/106279 which documents are hereby incorporated by reference in their entirety. Further developments of the technique have been described in published patent publications US20110027704A, US20110043791A, US2011102753A1, US20120044470A, US20120123581A, US20130258310A, US20130271740A and WO2013178422A1. These targets can be smaller than the illumination spot and may be surrounded by product structures on a wafer. Multiple gratings can be measured in one image, using a composite grating target. The contents of all these applications are also incorporated herein by reference.
  • process control methods are used to monitor and control the process. Such process control techniques are typically performed to obtain corrections for control of the lithographic process. It would be desirable to improve such process control methods.
  • a method for assigning features into at least first features and second features said first features being for at least one first patterning device configured for use in a lithographic process to form corresponding first structures on a substrate and second features being for at least one second patterning device configured for use in a lithographic process to form corresponding second structures on the substrate, wherein said method comprises assigning said features into said first features and said second features based on a patterning characteristic of the features.
  • a set of patterning devices comprising: at least one first patterning device comprising first features configured for use in a lithographic process to form corresponding first structures on a substrate, wherein the first features comprise a first patterning characteristic; and at least one second patterning device configured for use in a lithographic process to form corresponding second structures on the substrate, wherein the second features comprise a second patterning characteristic; wherein said first features form a first pattern and said second features form a second pattern, said first and second patterns being complementary patterns for forming a layer of a device on the substrate.
  • a method for arranging features on at least one patterning device configured for use in a process of patterning a substrate, the method comprising: obtaining a process setting for applying structures onto the substrate corresponding to a first set of said features comprised within a region on the at least one patterning device; determining a compatibility of a second set of features with the first set of features based on an expected quality of patterning of the second set of features using the setting of the process; and determining a suitable position of the second set of features on the at least one patterning device based on the determined compatibility.
  • a processing device for determining a correction for control of at least one manufacturing apparatus configured to provide product structures to a substrate in a manufacturing process, the processing device being configured to perform the method of the first aspect.
  • a computer program comprising program instructions operable to perform the method of the first aspect when run on a suitable apparatus.
  • a manufacturing apparatus configured to provide product structures to a substrate in a manufacturing process, said manufacturing apparatus comprising the processing device of the second aspect.
  • FIG. 1 depicts a lithographic apparatus together with other apparatuses forming a production facility for semiconductor devices
  • FIG. 2 comprises a schematic diagram of a scatterometer for use in measuring targets according to embodiments of the invention.
  • FIG. 3 comprises three exemplary full-field arrangements, each comprising two sub-fields and a corresponding illumination profile for exposing each of the sub-fields.
  • FIG. 1 at 200 shows a lithographic apparatus LA as part of an industrial production facility implementing a high-volume, lithographic manufacturing process.
  • the manufacturing process is adapted for the manufacture of for semiconductor products (integrated circuits) on substrates such as semiconductor wafers.
  • substrates such as semiconductor wafers.
  • semiconductor products integrated circuits
  • FIG. 1 at 200 shows a lithographic apparatus LA as part of an industrial production facility implementing a high-volume, lithographic manufacturing process.
  • the manufacturing process is adapted for the manufacture of for semiconductor products (integrated circuits) on substrates such as semiconductor wafers.
  • substrates such as semiconductor wafers.
  • the skilled person will appreciate that a wide variety of products can be manufactured by processing different types of substrates in variants of this process.
  • the production of semiconductor products is used purely as an example which has great commercial significance today.
  • a measurement station MEA is shown at 202 and an exposure station EXP is shown at 204 .
  • a control unit LACU is shown at 206 .
  • each substrate visits the measurement station and the exposure station to have a pattern applied.
  • a projection system is used to transfer a product pattern from a patterning device MA onto the substrate using conditioned radiation and a projection system. This is done by forming an image of the pattern in a layer of radiation-sensitive resist material.
  • the term “projection system” used herein should be broadly interpreted as encompassing any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation being used, or for other factors such as the use of an immersion liquid or the use of a vacuum.
  • the patterning MA device may be a mask or reticle, which imparts a pattern to a radiation beam transmitted or reflected by the patterning device.
  • Well-known modes of operation include a stepping mode and a scanning mode.
  • the projection system may cooperate with support and positioning systems for the substrate and the patterning device in a variety of ways to apply a desired pattern to many target portions across a substrate.
  • Programmable patterning devices may be used instead of reticles having a fixed pattern.
  • the radiation for example may include electromagnetic radiation in the deep ultraviolet (DUV) or extreme ultraviolet (EUV) wavebands.
  • DUV deep ultraviolet
  • EUV extreme ultraviolet
  • the present disclosure is also applicable to other types of lithographic process, for example imprint lithography and direct writing lithography, for example by electron beam.
  • control unit LACU which controls all the movements and measurements of various actuators and sensors to receive substrates W and reticles MA and to implement the patterning operations.
  • LACU also includes signal processing and data processing capacity to implement desired calculations relevant to the operation of the apparatus.
  • control unit LACU will be realized as a system of many sub-units, each handling the real-time data acquisition, processing and control of a subsystem or component within the apparatus.
  • the substrate is processed in at the measurement station MEA so that various preparatory steps may be carried out.
  • the preparatory steps may include mapping the surface height of the substrate using a level sensor and measuring the position of alignment marks on the substrate using an alignment sensor.
  • the alignment marks are arranged nominally in a regular grid pattern. However, due to inaccuracies in creating the marks and also due to deformations of the substrate that occur throughout its processing, the marks deviate from the ideal grid. Consequently, in addition to measuring position and orientation of the substrate, the alignment sensor in practice must measure in detail the positions of many marks across the substrate area, if the apparatus is to print product features at the correct locations with very high accuracy.
  • the apparatus may be of a so-called dual stage type which has two substrate tables, each with a positioning system controlled by the control unit LACU. While one substrate on one substrate table is being exposed at the exposure station EXP, another substrate can be loaded onto the other substrate table at the measurement station MEA so that various preparatory steps may be carried out.
  • the measurement of alignment marks is therefore very time-consuming and the provision of two substrate tables enables a substantial increase in the throughput of the apparatus.
  • the position sensor IF is not capable of measuring the position of the substrate table while it is at the measurement station as well as at the exposure station, a second position sensor may be provided to enable the positions of the substrate table to be tracked at both stations.
  • Lithographic apparatus LA may for example is of a so-called dual stage type which has two substrate tables and two stations—an exposure station and a measurement station—between which the substrate tables can be exchanged.
  • apparatus 200 forms part of a “litho cell” or “litho cluster” that contains also a coating apparatus 208 for applying photosensitive resist and other coatings to substrates W for patterning by the apparatus 200 .
  • a baking apparatus 210 and developing apparatus 212 are provided for developing the exposed pattern into a physical resist pattern.
  • substrate handling systems take care of supporting the substrates and transferring them from one piece of apparatus to the next.
  • These apparatuses which are often collectively referred to as the track, are under the control of a track control unit which is itself controlled by a supervisory control system SCS, which also controls the lithographic apparatus via lithographic apparatus control unit LACU.
  • supervisory control system SCS receives recipe information R which provides in great detail a definition of the steps to be performed to create each patterned substrate.
  • patterned substrates 220 are transferred to other processing apparatuses such as are illustrated at 222 , 224 , 226 .
  • apparatus 222 in this embodiment is an etching station, and apparatus 224 performs a post-etch annealing step. Further physical and/or chemical processing steps are applied in further apparatuses, 226 , etc. Numerous types of operation can be required to make a real device, such as deposition of material, modification of surface material characteristics (oxidation, doping, ion implantation etc.), chemical-mechanical polishing (CMP), and so forth.
  • CMP chemical-mechanical polishing
  • the apparatus 226 may, in practice, represent a series of different processing steps performed in one or more apparatuses. As another example, apparatus and processing steps may be provided for the implementation of self-aligned multiple patterning, to produce multiple smaller features based on a precursor pattern laid down by the lithographic apparatus.
  • substrates 230 arriving at the litho cluster may be newly prepared substrates, or they may be substrates that have been processed previously in this cluster or in another apparatus entirely.
  • substrates 232 on leaving apparatus 226 may be returned for a subsequent patterning operation in the same litho cluster, they may be destined for patterning operations in a different cluster, or they may be finished products to be sent for dicing and packaging.
  • Each layer of the product structure requires a different set of process steps, and the apparatuses 226 used at each layer may be completely different in type. Further, even where the processing steps to be applied by the apparatus 226 are nominally the same, in a large facility, there may be several supposedly identical machines working in parallel to perform the step 226 on different substrates. Small differences in set-up or faults between these machines can mean that they influence different substrates in different ways. Even steps that are relatively common to each layer, such as etching (apparatus 222 ) may be implemented by several etching apparatuses that are nominally identical but working in parallel to maximize throughput. In practice, moreover, different layers require different etch processes, for example chemical etches, plasma etches, according to the details of the material to be etched, and special requirements such as, for example, anisotropic etching.
  • previous and/or subsequent processes may be performed in other lithography apparatuses, as just mentioned, and may even be performed in different types of lithography apparatus.
  • some layers in the device manufacturing process which are very demanding in parameters such as resolution and overlay may be performed in a more advanced lithography tool than other layers that are less demanding. Therefore some layers may be exposed in an immersion type lithography tool, while others are exposed in a ‘dry’ tool. Some layers may be exposed in a tool working at DUV wavelengths, while others are exposed using EUV wavelength radiation.
  • a manufacturing facility in which litho cell LC is located also includes metrology system which receives some or all of the substrates W that have been processed in the litho cell. Metrology results are provided directly or indirectly to the supervisory control system SCS. If errors are detected, adjustments may be made to exposures of subsequent substrates, especially if the metrology can be done soon and fast enough that other substrates of the same batch are still to be exposed.
  • already exposed substrates may be stripped and reworked to improve yield, or discarded, thereby avoiding performing further processing on substrates that are known to be faulty. In a case where only some target portions of a substrate are faulty, further exposures can be performed only on those target portions which are good.
  • a metrology apparatus 240 which is provided for making measurements of parameters of the products at desired stages in the manufacturing process.
  • a common example of a metrology station in a modem lithographic production facility is a scatterometer, for example a dark-field scatterometer, an angle-resolved scatterometer or a spectroscopic scatterometer, and it may be applied to measure properties of the developed substrates at 220 prior to etching in the apparatus 222 .
  • Using metrology apparatus 240 it may be determined, for example, that important performance parameters such as overlay or critical dimension (CD) do not meet specified accuracy requirements in the developed resist.
  • CD critical dimension
  • the metrology results 242 from the apparatus 240 can be used to maintain accurate performance of the patterning operations in the litho cluster, by supervisory control system SCS and/or control unit LACU 206 making small adjustments over time, thereby minimizing the risk of products being made out-of-specification, and requiring re-work.
  • metrology apparatus 240 and/or other metrology apparatuses can be applied to measure properties of the processed substrates 232 , 234 , and incoming substrates 230 .
  • the metrology apparatus can be used on the processed substrate to determine important parameters such as overlay or CD.
  • FIG. 2 ( a ) A metrology apparatus suitable for use in embodiments of the invention is shown in FIG. 2 ( a ) .
  • This is purely an example metrology apparatus and any suitable metrology apparatus for measuring a process parameter such as overlay on a substrate may be used.
  • a target T and diffracted rays of measurement radiation used to illuminate the target are illustrated in more detail in FIG. 2 ( b ) .
  • the metrology apparatus illustrated is of a type known as a dark field metrology apparatus.
  • the metrology apparatus may be a stand-alone device or incorporated in either the lithographic apparatus LA, e.g., at the measurement station, or the lithographic cell LC.
  • An optical axis, which has several branches throughout the apparatus, is represented by a dotted line O.
  • light emitted by source 11 is directed onto substrate W via a beam splitter 15 by an optical system comprising lenses 12 , 14 and objective lens 16 .
  • These lenses are arranged in a double sequence of a 4F arrangement.
  • a different lens arrangement can be used, provided that it still provides a substrate image onto a detector, and simultaneously allows for access of an intermediate pupil-plane for spatial-frequency filtering. Therefore, the angular range at which the radiation is incident on the substrate can be selected by defining a spatial intensity distribution in a plane that presents the spatial spectrum of the substrate plane, here referred to as a (conjugate) pupil plane.
  • aperture plate 13 of suitable form between lenses 12 and 14 , in a plane which is a back-projected image of the objective lens pupil plane.
  • aperture plate 13 has different forms, labeled 13 N and 13 S, allowing different illumination modes to be selected.
  • the illumination system in the present examples forms an off-axis illumination mode.
  • aperture plate 13 N provides off-axis from a direction designated, for the sake of description only, as ‘north’.
  • aperture plate 13 S is used to provide similar illumination, but from an opposite direction, labeled ‘south’.
  • Other modes of illumination are possible by using different apertures.
  • the rest of the pupil plane is desirably dark as any unnecessary light outside the desired illumination mode will interfere with the desired measurement signals.
  • target T is placed with substrate W normal to the optical axis O of objective lens 16 .
  • the substrate W may be supported by a support (not shown).
  • a ray of measurement radiation I impinging on target T from an angle off the axis O gives rise to a zeroth order ray (solid line 0 ) and two first order rays (dot-chain line +1 and double dot-chain line ⁇ 1). It should be remembered that with an overfilled small target, these rays are just one of many parallel rays covering the area of the substrate including metrology target T and other features.
  • the aperture in plate 13 has a finite width (necessary to admit a useful quantity of light, the incident rays I will in fact occupy a range of angles, and the diffracted rays 0 and +1/ ⁇ 1 will be spread out somewhat. According to the point spread function of a small target, each order +1 and ⁇ 1 will be further spread over a range of angles, not a single ideal ray as shown. Note that the grating pitches of the targets and the illumination angles can be designed or adjusted so that the first order rays entering the objective lens are closely aligned with the central optical axis. The rays illustrated in FIGS. 2 ( a ) and 2 ( b ) are shown somewhat off axis, purely to enable them to be more easily distinguished in the diagram.
  • both the first and second illumination modes are illustrated, by designating diametrically opposite apertures labeled as north (N) and south (S).
  • N north
  • S south
  • the incident ray I of measurement radiation is from the north side of the optical axis
  • the +1 diffracted rays which are labeled +1(N)
  • enter the objective lens 16 .
  • the second illumination mode is applied using aperture plate 13 S
  • the ⁇ 1 diffracted rays (labeled ⁇ 1(S)) are the ones which enter the lens 16 .
  • a second beam splitter 17 divides the diffracted beams into two measurement branches.
  • optical system 18 forms a diffraction spectrum (pupil plane image) of the target on first sensor 19 (e.g. a CCD or CMOS sensor) using the zeroth and first order diffractive beams.
  • first sensor 19 e.g. a CCD or CMOS sensor
  • the pupil plane image captured by sensor 19 can be used for many measurement purposes such as reconstruction used in methods described herein.
  • the pupil plane image can also be used for focusing the metrology apparatus and/or normalizing intensity measurements of the first order beam.
  • optical system 20 , 22 forms an image of the target T on sensor 23 (e.g. a CCD or CMOS sensor).
  • an aperture stop 21 is provided in a plane that is conjugate to the pupil-plane. Aperture stop 21 functions to block the zeroth order diffracted beam so that the image of the target formed on sensor 23 is formed only from the ⁇ 1 or +1 first order beam.
  • the images captured by sensors 19 and 23 are output to processor PU which processes the image, the function of which will depend on the particular type of measurements being performed. Note that the term ‘image’ is used here in a broad sense. An image of the grating lines as such will not be formed, if only one of the ⁇ 1 and +1 orders is present.
  • aperture plate 13 and field stop 21 shown in FIG. 2 are purely examples.
  • on-axis illumination of the targets is used and an aperture stop with an off-axis aperture is used to pass substantially only one first order of diffracted light to the sensor.
  • 2 nd , 3 rd and higher order beams can be used in measurements, instead of or in addition to the first order beams.
  • the target T may comprise a number of gratings, which may have differently biased overlay offsets in order to facilitate measurement of overlay between the layers in which the different parts of the composite gratings are formed.
  • the gratings may also differ in their orientation, so as to diffract incoming radiation in X and Y directions.
  • a target may comprise two X-direction gratings with biased overlay offsets +d and ⁇ d, and Y-direction gratings with biased overlay offsets +d and ⁇ d. Separate images of these gratings can be identified in the image captured by sensor 23 .
  • the intensities of those individual images can be measured, e.g., by averaging or summing selected pixel intensity values within the identified areas. Intensities and/or other properties of the images can be compared with one another. These results can be combined to measure different parameters of the lithographic process
  • Full field integrated circuit (IC) devices comprise multiple functional blocks or sub-regions having different characteristics and therefore different exposure requirements.
  • an IC comprising a central processing unit (CPU) and on-chip memory or graphical processing units (GPUs) may be formed in a single exposure per layer.
  • the logic sub-regions, memory sub-regions and/or GPU sub-regions of such an IC each define different functional sub-regions and have quite different characteristics.
  • memory sub-regions e.g., static random access memory—SRAM) or GPU sub-regions tend to comprise highly regular patterns having a uniform pitch, while logic sub-regions tend to comprise irregular patterns having various pitches.
  • SRAM static random access memory
  • GPU sub-regions tend to comprise highly regular patterns having a uniform pitch
  • logic sub-regions tend to comprise irregular patterns having various pitches.
  • the memory sub-regions, and other more regular sub-regions, when exposed on their own, can take advantage of particular exposure modes and settings (for example, particular illumination modes) which enable improved scaling of these sub-regions (e.g., making these sub-regions smaller on the substrate by increasing device density).
  • particular exposure modes and settings for example, particular illumination modes
  • the more stringent requirements for exposure of the logic sub-regions limit the exposure modes and settings to those which are more conventional, to ensure that the logic areas function correctly and the die will be yielding. This in turn imposes a limit on the achievable scaling of the memory sub-regions, and as such means that the optimal scaling will not be achieved such that the IC will occupy more area on the substrate than necessary.
  • field or “full field” simply refers to any region on the substrate on which product structures are being formed (in particular, over multiple exposures) in an IC manufacturing process, and as such may comprise two or more adjacent sub-fields (i.e., “stitched” sub-fields exposed adjacently on the substrate).
  • the different functional sub-regions e.g., cache, logic, GPU, CPU, AI, metrology targets
  • are divided e.g., into two categories) between the sub-fields such that different (e.g., optimized) exposure modes and/or settings can be used for the different sub-field exposures as appropriate.
  • the two sub-fields may be substantially non-overlapping, i.e., they may not overlap at all, or else have a small overlap in the stitching boundary area to accommodate stitched targets.
  • a stitched target may comprise a first half of an overlay-like target on the first sub-field (e.g., patterned from the first reticle) and a second (complementary) half of the overlay-like target on the second sub-field (e.g., patterned from the second reticle).
  • the relative positioning of the complementary patterns can then be measured to provide a measure of the relative positioning of the two sub-fields.
  • a method of performing a lithographic process to form structures on a substrate within a field on said substrate, said field comprising at least a first sub-field and second sub-field said method comprising: forming first structures (e.g., arranged in first functional sub-regions) in a layer on the first sub-field in a first patterning process; and forming second structures (e.g., arranged in second functional sub-regions) in said layer on the second sub-field in a second patterning process; wherein at least one process setting is varied between the first patterning process and second patterning process.
  • each of the first and second patterning processes may be formed via a double (or multiple) patterning process and comprise more than one exposure and/or etch steps (e.g., one or more of the sub-regions may be formed in a litho-etch-lito etch (LELE) process. It is envisaged that a patterning process in this context may comprise any number of LE steps.
  • a proposed method may comprise dividing the different functional sub-regions divided between the reticles based on a respective patterning characteristic of each sub-region.
  • the patterning characteristic may be based on their functional type or structure and therefore their expected quality of patterning (e.g., exposure quality) and exposure requirements.
  • the expected quality of patterning may, for example, be the expected quality of the structure of the sub-regions when exposed with a particular process setting.
  • the expected quality of patterning may be quantified in terms of meeting one or more criterion for one or more of process parameters such as: overlay, edge placement error (EPE), critical dimension uniformity (CDU), contrast.
  • EPE edge placement error
  • CDU critical dimension uniformity
  • a first patterning process or exposure may be performed using at least one first reticle with first patterns for (e.g., irregular or relatively less regular) first functional sub-regions such as logic sub-regions and a second patterning process or exposure may be performed using at least one second reticle with second patterns for (e.g., regular or relatively more regular) second functional sub-regions such as memory sub-regions/GPU sub-regions or metrology targets etc.
  • first patterns for (e.g., irregular or relatively less regular) first functional sub-regions such as logic sub-regions
  • second patterning process or exposure may be performed using at least one second reticle with second patterns for (e.g., regular or relatively more regular) second functional sub-regions such as memory sub-regions/GPU sub-regions or metrology targets etc.
  • Such an arrangement may result in the exposed field (layer) being divided into distinct sub-fields (e.g., distinct half-fields assuming two exposures), each sub-field comprising functional sub-regions with shared characteristics
  • an expected quality of patterning may be acceptable using a process setting (e.g., illumination mode) which enables denser scaling of the structures when exposing the second sub-field compared to that possible when exposing the first sub-field.
  • a process setting e.g., illumination mode
  • the assignment of functional sub-regions to one category (reticle) or another may be based on the functional type of the functional sub-region (i.e., is it memory/GPU or logic/CPU). Alternatively or in addition, this assignment may be based on an assessment of the regularity of the pattern corresponding to the functional sub-region. Alternatively or in addition, assignment of the functional sub-regions between reticles may be based on a more rigorous assessment, for example, based on a simulation of the patterning on the substrate (e.g., under different process settings), or based on imposed design rules for a particular sub-region. In this way, the process setting(s) can be optimized individually for each sub-field of a stitched die.
  • FIG. 3 shows a number of examples of a field 300 , 300 ′, 300 ′′ exposed according to such a method.
  • FIG. 3 ( a ) shows a field 300 comprising (e.g., one layer of) a single die.
  • a first sub-field 310 ( a ) comprises CPU circuitry which is largely irregular.
  • a second sub-field 310 ( b ) comprise GPU circuitry having largely regular, repeating patterns.
  • the first sub-field 310 ( a ) is exposed using a first illumination profile 320 ( a ) (e.g., annular) optimized for the irregular pattern.
  • the second sub-field 310 ( b ) is exposed using a second illumination profile 320 ( b ) optimized for the regular pattern (e.g., enabling a greater product density than for said first sub-field 310 ( a ), due to the lower complexity of the image being exposed there).
  • FIG. 3 ( b ) shows a field 300 ′ comprising first sub-field 310 ( a )′ having functional sub-regions of logic circuitry (largely irregular) and a second sub-field 310 ( b )′ comprising SRAM (regular).
  • the first sub-field 310 ( a )′ is exposed using a first illumination profile 320 ( a )′ optimized for the logic circuitry and the second sub-field 310 ( b )′ is exposed using a second illumination profile 320 ( b )′ optimized for the SRAM.
  • FIG. 3 ( c ) shows a field 300 ′′ comprising first sub-field 310 ( a )′′ having functional sub-regions of CPU circuitry (largely irregular) and a second sub-field 310 ( b )′′ comprising AI (e.g., neural network) circuitry (very regular).
  • AI e.g., neural network
  • the first sub-field 310 ( a )′′ is exposed using a first illumination profile 320 ( a )′′ optimized for the CPU circuitry and the second sub-field 310 ( b )′′ is exposed using a second illumination profile 320 ( b )′′ optimized for the AI circuitry.
  • the method comprises:
  • FIG. 3 shows such a boundary area 330 (i.e., either side of stitching boundary 340 dividing the two sub-fields).
  • the boundary area 330 may be maintained clear or relatively clear of structures (e.g., the functional sub-regions are arranged outside of the boundary area).
  • circuitry within the two sub-fields are not necessarily connected in the same layer, but rather some or all connections are made in another, connecting layer (e.g., based on a separate exposure using one or more additional reticles.
  • those connections critical for non-correctable proximity errors e.g., induced by the other exposure
  • the proposed connecting layer (which may comprise other product structures etc.) may be exposed in a single exposure, or (if not) using the same illumination such that the connections are formed correctly.
  • a method of dividing the functional sub-regions between reticles may also comprise dividing patterns to connect the first functional sub-regions of the first sub-field and the second functional sub-regions of the second sub-field, into a reticle for exposure of a different layer.
  • irregular functional sub-regions may be assigned to at least one first reticle for the first sub-field
  • regular functional sub-regions may be assigned to at least one second reticle for the second sub-field
  • the third layer may also be formed in more than one exposure, e.g., using a double patterning process.
  • the above example shows different pupil illumination modes for exposing the different sub-fields.
  • any aspect of the exposure process can be varied/optimized for between the different sub-fields.
  • one or more of the pupil or polarization mode, the focus or dose settings, etch parameter settings, post bake parameters settings, metrology parameter settings e.g., for alignment, post-exposure or post-processing metrology
  • metrology parameter settings e.g., for alignment, post-exposure or post-processing metrology
  • the alignment sensor wavelength or metrology recipe for post-exposure metrology may be optimized per sub-field.
  • control loops per exposure there may be different control loops per exposure, each based on its own estimation/modeling and/or optimization per exposure.
  • metrology data may also be divided according to which sub-field it corresponds, such that each control loop is based only on metrology data from its corresponding sub-field.
  • the metrology strategies may also be defined per sub-field. For example, where a sub-field comprises functional sub-regions which will generally be yielding over a large value range for a particular process parameter, then metrology for that process parameter (and targets therefor) may be dispensed with altogether.
  • focus targets and focus metrology may be dispensed with altogether for the sub-field, or only a very few targets measured.
  • fewer metrology targets (less dense metrology) may be performed on sub-fields where there is expected to be little intra-sub-field variation in the process parameter being measured/controlled and/or a control strategy may be employed based on a relatively simple (e.g., linear) model, compared to sub-fields which show greater intra-sub-field variation for that process parameter.
  • OPC optical proximity correction
  • the exposure routing of the functional sub-regions and sub-fields may be optimized for maximal throughput (e.g., so as to minimize overhead such as the number of reticle exchanges, illumination switches and the switch times), and to potentially also minimize the lens/wafer heating impact.
  • maximal throughput e.g., so as to minimize overhead such as the number of reticle exchanges, illumination switches and the switch times
  • Such a method may comprise:
  • the method may comprise optimizing the arrangement of the sub-regions on each reticle (following assignment of the sub-regions to different reticles) to maximize throughput.
  • the optimization is based on the respective process setting for exposure of that reticle and therefore the corresponding expected quality of patterning.
  • the assessment may be based on necessary, imposed, or preferred control characteristics for a sub-region (e.g., hardware characteristic such as the slit length, or software characteristics such as dose control to OPC).
  • more product structures can be fitted onto a single device.
  • more memory or GPUs can be fitted onto a single device, because more aggressively scaled sub-regions can be exposed.
  • the device area can be shrunk enabling more devices per wafer to be printed.
  • Such an approach may be particularly beneficial for (e.g., EUV) high NA systems which have smaller fields than more conventional systems.
  • EUV extreme ultraviolet
  • the field tends to require dividing between stitched exposures in any case, as the required full field area is greater than the maximum scanning area. Therefore, there would be no significant additional overhead in performing this method.
  • the sub-field area comprises the maximum scanning area of the system.
  • At least one process setting is varied between the first patterning process and second patterning process.
  • first sub-field and second sub-field comprise substantially adjacent sub-fields.
  • a method according to embodiment 1 or 2 wherein said first structures comprise a first patterning characteristic and said second structures comprise a second patterning characteristic, said first patterning characteristic being distinct from said second patterning characteristic. 4. A method according to embodiment 3, wherein said first patterning characteristic relates to an expected quality of patterning of the first structures following said first patterning process and said second patterning characteristic relates to an expected quality of patterning of the second structures following said second patterning process. 5. A method according to embodiment 3 or 4, wherein said first patterning characteristic relates to the degree of regularity of the first structures and said second patterning characteristic relates to the degree of regularity of the second structures. 6.
  • said first functional sub-regions comprise memory and/or graphical processing unit circuitry and said second functional sub-regions comprise logic and/or central processing unit circuitry.
  • the at least one process setting relates to an illumination and/or patterning process setting.
  • an illumination and/or patterning process setting comprises one or more of an illumination profile, a polarization setting, a focus setting, a dose setting, an etch control setting, and/or a post exposure bake setting. 10.
  • the at least one process setting relates to one or more of an alignment sensor setting, a metrology strategy, a metrology setting, a control model, an optical processing control setting.
  • said first patterning process is performed using at least one first patterning device and said second patterning process is formed using at least one second patterning device.
  • a method according to embodiment 14 comprising forming connections between at least some of said first structures to at least some of said second structures in a third patterning process of a second layer. 16.
  • a method for assigning features into at least first features and second features said first features being for at least one first patterning device configured for use in a lithographic process to form corresponding first structures on a substrate and second features being for at least one second patterning device configured for use in a lithographic process to form corresponding second structures on a substrate, wherein said method comprises assigning said features into said first features and said second features based on a patterning characteristic of the features. 17.
  • said patterning characteristic relates to an expected quality of patterning of the first structures and the second structures based on a corresponding process setting. 18.
  • a method according to embodiment 17, comprising performing an assessment of the expected quality of patterning of the first structures and the second structures based on a corresponding process setting; and performing the assignment of said features based on said assessment. 19.
  • a method according to embodiment 18, wherein the step of performing an assessment comprises simulating patterning of the first structures and the second structures onto a substrate.
  • 20. A method according to embodiment 18 or 19, wherein said assessment is based on imposed design rules for the first features and second features.
  • 21. A method according to embodiment 18 to 20, wherein said assessment is based on the degree of regularity of subsets of the features. 22.
  • an illumination and/or patterning process setting comprises one or more of an illumination profile, a polarization setting, a focus setting, a dose setting, an etch setting and a post-bake exposure setting.
  • the process setting relates to a monitoring and/or control setting.
  • the process setting relates to one or more of an alignment sensor setting, a metrology strategy, a metrology setting, a control model, an optical processing control setting. 26.
  • a method according to any of embodiments 16 to 25, comprising arranging the first features on said at least one first patterning device in one or more first functional sub-regions, and the second features on said at least one second patterning device in one or more second functional sub-regions, said functional sub-regions being differentiated by their intended function.
  • 27. A method according to embodiment 26, wherein said first functional sub-regions relate to memory or graphical processing unit circuitry and said second functional sub-regions relate to logic or central processing unit circuitry.
  • 28. comprising arranging said first features on said first patterning device outside of a boundary region defined along a boundary of the first patterning device and arranging said second features on said second patterning device outside of boundary region defined along a boundary of the second patterning device.
  • 29. comprising forming structures on a substrate within a field on said substrate, said field comprising at least a first sub-field and second sub-field, said method comprising:
  • At least one process setting is varied between the first patterning process and second patterning process; and wherein the first sub-field and second sub-field comprise substantially adjacent sub-fields.
  • a set of patterning devices comprising:
  • At least one first patterning device comprising first features configured for use in a lithographic process to form corresponding first structures on a substrate, wherein the first features comprise a first patterning characteristic
  • At least one second patterning device configured for use in a lithographic process to form corresponding second structures on a substrate, wherein the second features comprise a second patterning characteristic
  • first features form a first pattern and said second features form a second pattern, said first and second patterns being complementary patterns for forming a layer of a device.
  • an illumination and/or patterning step setting comprises one or more of an illumination profile, a polarization setting, a focus setting or a dose setting.
  • a set of patterning devices according to any of embodiments 31 to 34, wherein the process setting relates to one or more of an alignment sensor setting, a metrology strategy, a metrology setting, a control model, an optical processing control setting.
  • a set of patterning devices according to any of embodiments 30 to 35, wherein said patterning characteristic relates to the degree of regularity of the features.
  • a set of patterning devices according to any of embodiments 30 to 36, wherein the first features on said at least one first patterning device are arranged in one or more first functional sub-regions, and the second features on said at least one second patterning device are arranged in one or more second functional sub-regions, said functional sub-regions being differentiated by their intended function.
  • said first functional sub-regions relate to memory and/or graphical processing unit circuitry and said second functional sub-regions relate to logic and/or central processing unit circuitry.
  • a set of patterning devices according to any of embodiments 30 to 38, wherein said first features on said at least one first patterning device are arranged outside of a boundary region defined along a boundary of the at least one first patterning device and said second features on said at least one second patterning device are arranged outside of boundary region defined along a boundary of the at least one second patterning device.
  • a set of patterning devices comprising at least one third patterning device having a third pattern for forming connections to connect at least some of said first structures to at least some of said second structures.
  • the determined corrections may also be used for any process and by any integrated circuit (IC) manufacturing apparatus in an IC manufacturing process, e.g., an etch apparatus, which has an effect on the position and/or a dimension of the structures formed within a layer.
  • IC integrated circuit
  • UV radiation e.g., having a wavelength of or about 365, 355, 248, 193, 157 or 126 nm
  • EUV radiation e.g., having a wavelength in the range of 5-20 nm
  • particle beams such as ion beams or electron beams.
  • lens may refer to any one or combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic and electrostatic optical components.

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Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6251564B1 (en) * 1999-05-17 2001-06-26 United Microelectronics Corp. Method for forming a pattern with both logic-type and memory-type circuit
US6518180B1 (en) * 1998-10-23 2003-02-11 Hitachi, Ltd. Method for fabricating semiconductor device and method for forming mask suitable therefor
US20030039893A1 (en) 2001-08-22 2003-02-27 Jeff Farnsworth Exposed phase edge mask method for generating periodic structures with subwavelength feature
US20030142284A1 (en) 2002-01-28 2003-07-31 Taiwan Semiconductor Manufacturing Company Multiple mask step and scan aligner
US20060033921A1 (en) 2004-08-16 2006-02-16 Asml Netherlands B.V. Method and apparatus for angular-resolved spectroscopic lithography characterization
EP1804123A2 (de) 2005-12-29 2007-07-04 ASML MaskTools B.V. Verfahren, Programmprodukt und Vorrichtung für modellbasierte Geometriezerlegung zur Anwendung in einem Mehrfachbelichtungsvorgang
WO2009078708A1 (en) 2007-12-17 2009-06-25 Asml Netherlands B.V. Diffraction based overlay metrology tool and method
WO2009106279A1 (en) 2008-02-29 2009-09-03 Asml Netherlands B.V. Metrology method and apparatus, lithographic apparatus, and device manufacturing method
US20100201963A1 (en) 2009-02-11 2010-08-12 Asml Netherlands B.V. Inspection Apparatus, Lithographic Apparatus, Lithographic Processing Cell and Inspection Method
US20100291476A1 (en) 2009-05-13 2010-11-18 Synopsys, Inc. Patterning A Single Integrated Circuit Layer Using Automatically-Generated Masks And Multiple Masking Layers
US20100301457A1 (en) 2009-05-26 2010-12-02 Uwe Paul Schroeder Lithography Masks, Systems, and Manufacturing Methods
US20100308439A1 (en) 2009-06-04 2010-12-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dual wavelength exposure method and system for semiconductor device manufacturing
US20110027704A1 (en) 2009-07-31 2011-02-03 Asml Netherlands B.V. Methods and Scatterometers, Lithographic Systems, and Lithographic Processing Cells
US20110043791A1 (en) 2009-08-24 2011-02-24 Asml Netherlands B.V. Metrology Method and Apparatus, Lithographic Apparatus, Device Manufacturing Method and Substrate
US20110102753A1 (en) 2008-04-21 2011-05-05 Asml Netherlands B.V. Apparatus and Method of Measuring a Property of a Substrate
US20120044470A1 (en) 2010-08-18 2012-02-23 Asml Netherlands B.V. Substrate for Use in Metrology, Metrology Method and Device Manufacturing Method
US20120123581A1 (en) 2010-11-12 2012-05-17 Asml Netherlands B.V. Metrology Method and Inspection Apparatus, Lithographic System and Device Manufacturing Method
US20130258310A1 (en) 2012-03-27 2013-10-03 Asml Netherlands B.V. Metrology Method and Apparatus, Lithographic System and Device Manufacturing Method
US20130271740A1 (en) 2012-04-16 2013-10-17 Asml Netherlands B.V. Lithographic Apparatus, Substrate and Device Manufacturing Method
WO2013178422A1 (en) 2012-05-29 2013-12-05 Asml Netherlands B.V. Metrology method and apparatus, substrate, lithographic system and device manufacturing method
US20140244215A1 (en) * 2013-02-22 2014-08-28 Canon Kabushiki Kaisha Method for determining mask pattern, non-transitory recording medium, and information processing apparatus
US20150052492A1 (en) 2013-08-15 2015-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Routing method
WO2016205409A1 (en) 2015-06-19 2016-12-22 Qualcomm Incorporated Hybrid coloring methodology for multi-pattern technology

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518180B1 (en) * 1998-10-23 2003-02-11 Hitachi, Ltd. Method for fabricating semiconductor device and method for forming mask suitable therefor
US6251564B1 (en) * 1999-05-17 2001-06-26 United Microelectronics Corp. Method for forming a pattern with both logic-type and memory-type circuit
US20030039893A1 (en) 2001-08-22 2003-02-27 Jeff Farnsworth Exposed phase edge mask method for generating periodic structures with subwavelength feature
US20030142284A1 (en) 2002-01-28 2003-07-31 Taiwan Semiconductor Manufacturing Company Multiple mask step and scan aligner
US20060033921A1 (en) 2004-08-16 2006-02-16 Asml Netherlands B.V. Method and apparatus for angular-resolved spectroscopic lithography characterization
US20060066855A1 (en) 2004-08-16 2006-03-30 Asml Netherlands B.V. Method and apparatus for angular-resolved spectroscopic lithography characterization
EP1804123A2 (de) 2005-12-29 2007-07-04 ASML MaskTools B.V. Verfahren, Programmprodukt und Vorrichtung für modellbasierte Geometriezerlegung zur Anwendung in einem Mehrfachbelichtungsvorgang
WO2009078708A1 (en) 2007-12-17 2009-06-25 Asml Netherlands B.V. Diffraction based overlay metrology tool and method
WO2009106279A1 (en) 2008-02-29 2009-09-03 Asml Netherlands B.V. Metrology method and apparatus, lithographic apparatus, and device manufacturing method
US20110102753A1 (en) 2008-04-21 2011-05-05 Asml Netherlands B.V. Apparatus and Method of Measuring a Property of a Substrate
US20100201963A1 (en) 2009-02-11 2010-08-12 Asml Netherlands B.V. Inspection Apparatus, Lithographic Apparatus, Lithographic Processing Cell and Inspection Method
US20100291476A1 (en) 2009-05-13 2010-11-18 Synopsys, Inc. Patterning A Single Integrated Circuit Layer Using Automatically-Generated Masks And Multiple Masking Layers
US20100301457A1 (en) 2009-05-26 2010-12-02 Uwe Paul Schroeder Lithography Masks, Systems, and Manufacturing Methods
US20100308439A1 (en) 2009-06-04 2010-12-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dual wavelength exposure method and system for semiconductor device manufacturing
US20110027704A1 (en) 2009-07-31 2011-02-03 Asml Netherlands B.V. Methods and Scatterometers, Lithographic Systems, and Lithographic Processing Cells
US20110043791A1 (en) 2009-08-24 2011-02-24 Asml Netherlands B.V. Metrology Method and Apparatus, Lithographic Apparatus, Device Manufacturing Method and Substrate
US20120044470A1 (en) 2010-08-18 2012-02-23 Asml Netherlands B.V. Substrate for Use in Metrology, Metrology Method and Device Manufacturing Method
US20120123581A1 (en) 2010-11-12 2012-05-17 Asml Netherlands B.V. Metrology Method and Inspection Apparatus, Lithographic System and Device Manufacturing Method
US20130258310A1 (en) 2012-03-27 2013-10-03 Asml Netherlands B.V. Metrology Method and Apparatus, Lithographic System and Device Manufacturing Method
US20130271740A1 (en) 2012-04-16 2013-10-17 Asml Netherlands B.V. Lithographic Apparatus, Substrate and Device Manufacturing Method
WO2013178422A1 (en) 2012-05-29 2013-12-05 Asml Netherlands B.V. Metrology method and apparatus, substrate, lithographic system and device manufacturing method
US20140244215A1 (en) * 2013-02-22 2014-08-28 Canon Kabushiki Kaisha Method for determining mask pattern, non-transitory recording medium, and information processing apparatus
US20150052492A1 (en) 2013-08-15 2015-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Routing method
WO2016205409A1 (en) 2015-06-19 2016-12-22 Qualcomm Incorporated Hybrid coloring methodology for multi-pattern technology

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
International Search Report and Written Opinion issued in corresponding PCT Patent Application No. PCT/EP2019/060912, dated Jun. 12, 2019.

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