US11619605B2 - Display apparatus - Google Patents
Display apparatus Download PDFInfo
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- US11619605B2 US11619605B2 US16/727,086 US201916727086A US11619605B2 US 11619605 B2 US11619605 B2 US 11619605B2 US 201916727086 A US201916727086 A US 201916727086A US 11619605 B2 US11619605 B2 US 11619605B2
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- resistance measuring
- sealing unit
- substrate
- display apparatus
- measuring pattern
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/84—Passivation; Containers; Encapsulations
- H10K50/842—Containers
- H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
- G01N27/04—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
- G01N27/20—Investigating the presence of flaws
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- H01L27/3276—
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- H01L51/5246—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/84—Passivation; Containers; Encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/70—Testing, e.g. accelerated lifetime tests
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
Definitions
- Exemplary embodiments of the present inventive concept relate to a display apparatus, and more particularly, to a display apparatus including a sealing unit and resistance measuring patterns.
- a display apparatus may include display devices provided between a pair of substrates facing each other, and the pair of substrates may be bonded to each other by a sealing unit that surrounds the display devices and is coated.
- a defect may occur in a sealing material of the sealing unit.
- a display apparatus includes: a first substrate including a display area and a peripheral area; a second substrate overlapping the first substrate; a sealing unit surrounding the display area and disposed between the first substrate and the second substrate; and a first resistance measuring pattern located at an upper surface of the sealing unit, and a second resistance measuring pattern located at a lower surface of the sealing unit, wherein each of the first and second resistance measuring patterns extends along edges of the first substrate and has a rectangular shape including an open side.
- the display apparatus further includes a terminal portion arranged at an edge of the first substrate in the peripheral area, wherein the terminal portion is located at the open side of the first and second resistance measuring patterns.
- a data drive circuit is located at the terminal portion, and the data drive circuit is configured to compare an initial resistance value of the sealing unit with a resistance value measured by using the first and second resistance measuring patterns.
- an end portion of the first resistance measuring pattern and an end portion of the second resistance measuring pattern are respectively electrically connected to the terminal portion.
- the end portion of the first resistance measuring pattern and the end portion of the second resistance measuring pattern are spaced apart from each other by a predetermined distance.
- the first resistance measuring pattern and the second resistance measuring pattern respectively extend from the edges of the first substrate and edges of the second substrate toward the display area.
- a width of the second resistance measuring pattern is less than a width of the sealing unit.
- the display apparatus further includes a power supply line located between the first substrate and the sealing unit, wherein the sealing unit covers a portion of the power supply line, and the second resistance measuring pattern and the power supply line are located on a same layer and are apart from each other.
- At least one of the first and second resistance measuring patterns includes a plurality of fragments separated from one another.
- the first and second resistance measuring patterns each includes a bent portion.
- a display apparatus includes: a first substrate including a display area, and a peripheral area; a terminal portion disposed in the peripheral area; a second substrate disposed on the first substrate; a sealing unit located between the first substrate and the second substrate and surrounding the display area; and a first resistance measuring pattern located at an upper surface of the sealing unit, and a second resistance measuring pattern located at a lower surface of the sealing unit, wherein each of the first and second resistance measuring patterns is electrically connected to the terminal portion.
- the first and second resistance measuring patterns extends along edges of the first substrate and has a rectangular shape including an open side, and wherein the terminal portion is located at the open side of the first and second resistance measuring patterns.
- a data drive circuit is located at the terminal portion, and the data drive circuit is configured to compare an initial resistance value of the sealing unit with a resistance value measured by using the first and second resistance measuring patterns.
- an end portion of the first resistance measuring pattern and an end of the second resistance measuring pattern are electrically connected to the terminal portion, respectively.
- the end portion of the first resistance measuring pattern and the end portion of the second resistance measuring pattern are spaced apart from each other by a predetermined distance.
- the display apparatus further includes a power supply line located between the first substrate and the sealing unit, wherein the sealing unit covers a portion of the power supply line, and the second resistance measuring pattern and the power supply line are located on a same layer and include a same material.
- the first resistance measuring pattern and the second resistance measuring pattern respectively extend from edges of the first substrate and edges of the second substrate toward the display area.
- a width of the second resistance measuring pattern is less than a width of the sealing unit.
- At least one of the first and second resistance measuring patterns includes a plurality of fragments separated from one another.
- the first and second resistance measuring patterns each includes a bent portion.
- FIG. 1 is a schematic top-plan view illustrating a display apparatus according to an exemplary embodiment of the present inventive concept
- FIG. 2 is a circuit diagram of a pixel in the display apparatus according to an exemplary embodiment of the present inventive concept
- FIG. 3 is a schematic cross-sectional view taken along line I-I′ shown in FIG. 1 , according to an exemplary embodiment of the present inventive concept;
- FIG. 4 is a schematic cross-sectional view of a display apparatus, according to an exemplary embodiment of the present inventive concept
- FIG. 5 is a schematic top-plan view illustrating a resistance measuring pattern of the display apparatus shown in FIG. 1 , according to an exemplary embodiment of the present inventive concept;
- FIG. 6 is a schematic top-plan view illustrating a resistance measuring pattern of the display apparatus shown in FIG. 1 , according to an exemplary embodiment of the present inventive concept;
- FIG. 7 is a schematic top-plan view illustrating a resistance measuring pattern of the display apparatus shown in FIG. 1 , according to an exemplary embodiment of the present inventive concept.
- FIG. 8 is a schematic top-plan view illustrating a resistance measuring pattern of the display apparatus shown in FIG. 1 , according to an exemplary embodiment of the present inventive concept.
- an element e. g. a layer, a region, or a component
- the element may be directly on the other element, or an intervening layer, region, or component may be present between the element and the other element.
- FIG. 1 is a schematic top-plan view illustrating a display apparatus according to an exemplary embodiment of the present inventive concept
- FIG. 2 is a circuit diagram of a pixel in the display apparatus according to an exemplary embodiment of the present inventive concept.
- a display apparatus 1 includes a display area DA providing an image and a peripheral area PA at least partially surrounding the display area DA.
- a first substrate 100 includes the display area DA and the peripheral area DA.
- Pixels P each of which are connected to a scan line SL and a data line DL, are disposed in the display area DA.
- the scan line SL extends in the y direction
- the data line DL extends in the x direction that is substantially perpendicular to the y direction.
- Each pixel P may, for example, emit a red, green, blue, or white light.
- Each pixel P may include a light emitting element.
- a light emitting element may include an organic light-emitting diode.
- the pixel P may include a pixel circuit PC connected to the scan line SL and data line DL, and an organic light-emitting diode OLED connected to the pixel circuit PC.
- the pixel circuit PC includes a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst.
- the switching thin film transistor Ts is connected to the scan line SL and the data line DL and delivers a data signal input through the data line DL to the driving thin film transistor Td, in response to a scan signal that is input through the scan line SL.
- the storage capacitor Cst which is connected to the switching thin film transistor Ts and the driving voltage line PL, stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor Ts and a driving voltage ELVDD supplied to the driving voltage line PL.
- the driving thin film transistor Td is connected to the driving voltage line PL and the storage capacitor Cst and may control a driving current flowing from the driving voltage line PL through the organic light-emitting diode OLED, in response to a value of the voltage stored in the storage capacitor Cst.
- the organic light-emitting diode OLED may emit a light of a luminance in response to the driving current.
- the organic light-emitting diode OLED may, for example, emit red, green, blue, or white light.
- the present inventive concept is not limited thereto.
- the pixel circuit PC of the pixel P may be variously modified.
- the pixel circuit PC may include at least three thin film transistors and/or at least two storage capacitors.
- the peripheral area PA is arranged at an outer portion of the display area DA.
- the peripheral area PA may surround the display area DA.
- the peripheral area PA, in which the pixels P are not arranged, corresponds to a non-display area that does not provide an image.
- a drive circuit including, for example, driving units 20 and 22 , a terminal portion 40 , a driving power supply line 60 , and a common power supply line 70 may be disposed in the peripheral area PA.
- the driving units 20 and 22 may each include, for example, an emission drive circuit, a scan drive circuit, and the like.
- the emission drive circuit is disposed in the peripheral area PA of the first substrate 100 and generates an emission control signal and transmits the emission control signal to each pixel P through an emission control line.
- the emission drive circuits may respectively be disposed at left and right sides of the display area DA, but the present inventive concept is not limited thereto. In an exemplary embodiment of the present inventive concept, only one emission drive circuit may be provided.
- the scan drive circuit is disposed in the peripheral area PA of the first substrate 100 , and the scan drive circuit generates a scan signal and transmits the scan signal to each pixel P through the scan line SL.
- the scan drive circuits may respectively be at left and right sides of the display area DA, but the present inventive concept is not limited thereto. In an exemplary embodiment of the present inventive concept, only one scan drive circuit may be provided.
- the terminal portion 40 is disposed at an edge of the first substrate 100 and includes a plurality of terminals 41 , 42 , 43 a , 43 b , 44 , and 45 .
- the terminal portion 40 is disposed in the peripheral area PA and may be electrically connected to a flexible printed circuit board FPCB without being covered by an insulating layer.
- the terminal portion 40 may be disposed at a side of the first substrate 100 at which the driving units 20 and 22 are not located.
- the plurality of terminals 41 , 42 , 43 a , 43 b , 44 , and 45 may be arranged along a side of the first substrate 100 that extends along the y-direction, whereas the driving units 20 and 22 may be disposed along sides of the first substrate 100 that extend in the x-direction.
- the flexible printed board circuit FPCB electrically connects a controller 55 to the terminal portion 40 , and a signal or power is transmitted from the controller 55 transfers to connection lines 21 , 31 , 51 , 61 , and 71 connected to the terminal portion 40 .
- the controller 55 receives a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal and generates a control signal to control driving of the driving units 20 and 22 , and the generated control signal may be delivered to the driving units 20 and 22 through the terminal 44 and the connection lines 21 and 31 connected to the flexible printed circuit board FPCB.
- the controller 55 provides the driving voltage ELVDD and a common voltage ELVSS to the driving power supply line 60 and the common power supply line 70 , respectively.
- the driving voltage ELVDD may be provided to each pixel P through the driving voltage line PL connected to the driving power supply line 60
- the common voltage ELVSS may be provided to a common electrode of the pixel P.
- a data drive circuit 50 may be disposed on the flexible printed circuit board FPCB.
- the data drive circuit 50 provides a data signal to each pixel P and may be connected to the terminal portion 40 .
- the data signal of the data drive circuit 50 is provided to each pixel P through the connection line 51 connected to the terminal 41 and the data line DL connected to the connection line 51 .
- the data drive circuit 50 is disposed on the flexible printed circuit board FPCB, but the present inventive concept is not limited thereto.
- the data drive circuit 50 may be disposed in the peripheral area PA of the first substrate 100 .
- the driving power supply line 60 may be arranged in the peripheral area PA.
- the driving power supply line 60 may be disposed between the terminal portion 40 and a side of the display area DA facing the terminal portion 40 .
- the driving voltage ELVDD which is provided through the connection line 51 connected to the terminal 41 , may be provided to each pixel P through the driving voltage line PL.
- the common power supply line 70 may be disposed in the peripheral area PA and partially surround the display area DA.
- the common power supply line 70 has a loop-shape (e.g., a U-shape or a frame shape with an open side) in which a side of the display area DA adjacent to the terminal portion 40 is not surrounded by the common power supply line 70 .
- the common power supply line 70 may extend along edges of the first substrate 100 , except an edge at which the terminal portion 40 is located.
- the common power supply line 70 is electrically connected to the connection line 71 connected to the terminal 45 and provides the common voltage ELVSS to the common electrode (e.g., a cathode) of the organic light-emitting diode OLED in the pixel P.
- the connection lines 71 are in contact with an end and another end of the common power supply line 70 via contact holes CNT.
- the connection line 71 may have a loop-shape that partially surrounds the display area DA.
- the connection line 71 may not surround one side of the display area DA.
- the connection lines 71 may overlap the common power supply line 70 and may extend farther than the common power supply line 70 toward an end of the first substrate 100 , for example, the terminal portion 40 .
- a second substrate 300 facing the first substrate 100 is located above the first substrate 100 that includes the above-mentioned configuration, and a sealing unit 400 disposed is between the first substrate 100 and the second substrate 300 .
- the sealing unit 400 may surround the display area DA.
- a space formed by the first substrate 100 , the second substrate 300 , and the sealing unit 400 may be spatially separated from outside, and permeation of external moisture or impurities may be prevented.
- the sealing unit 400 may include an inorganic material frit, but the present inventive concept is not limited thereto.
- the sealing unit 400 may include epoxy and so on.
- the sealing unit 400 may at least partially overlap the common power supply line 70 , and thus, a dead area of the display apparatus 1 may be reduced.
- the sealing unit 400 is used for bonding the first substrate 100 and the second substrate 300 to each other.
- defects such as exfoliation occur in the sealing unit 400
- external moisture may permeate into the display apparatus 1 .
- performing complete enumeration on manufactured display apparatuses 1 just to identify the defect in the sealing unit 400 may excessively decrease the manufacturing yield of the display apparatus 1 .
- the pair of resistance measuring patterns 80 that are respectively disposed at the upper surface and the lower surface of the sealing unit 400 may at least partially surround the display area DA, and the terminal portion 40 may be disposed at the open side of the pair of resistance measuring patterns 80 .
- the terminal portion 40 and the like are located between the sealing unit 400 and an edge of the first substrate 100 that connects to flexible printed circuit board FPCB.
- the sealing unit 400 extends adjacent to other edges of the first substrate 100 . Accordingly, when an impact is applied to the first substrate 100 , at the edge of the first substrate 100 at which the terminal portion 40 is located, it is less likely that the sealing unit 400 may be damaged due to impacts than at the other edges of the first substrate 100 . Therefore, the pair of resistance measuring patterns 80 , which has a loop-shape in which an edge of the display area DA that is adjacent to the terminal portion 40 is not surrounded by the pair of resistance measuring patterns 80 , may extend along the edges of the first substrate 100 except the terminal portion 40 .
- the pair of resistance measuring patterns 80 may have a square shape with an open side, from a plan view.
- the pair of resistance measuring patterns 80 may be electrically connected to the terminal portion 40 .
- the pair of resistance measuring patterns 80 may be electrically connected to the flexible printed circuit board FPCB through connection lines 83 and 84 and terminals 43 a and 43 b .
- the connection lines 83 and 84 may respectively be connected to two end portions spaced apart from each other.
- connection line 83 when one connection line 83 is connected to an end portion of a first resistance measuring pattern at the upper surface of the sealing unit 400 , the other connection line 84 is connected to an end portion of a second resistance measuring pattern at the lower surface of the sealing unit 400 , and the end portion of the first resistance measuring pattern at the upper surface of the sealing unit 400 and the end portion of the second resistance measuring pattern at the lower surface of the sealing unit 400 are the two portions spaced apart from each other by a predetermined distance along the y-direction.
- the predetermined distance is the greatest or max distance from end to end.
- the data drive circuit 50 may measure a resistance of the sealing unit 400 by using the connection lines 83 and 84 and the terminals 43 a and 43 b .
- the data drive circuit 50 may store an initial resistance value of the sealing unit 400 measured right after the sealing unit 400 is formed and compare the stored initial resistance value with a resistance value (e.g., an actual resistance value) of the sealing unit 400 , which is the resistance value that is measured later.
- re-measuring a resistance value of the sealing unit 400 is performed, and the re-measured resistance value is compared with the initial resistance value. If the resistance value does not change, it is determined that no defect occurred in the sealing unit 400 , and if the resistance value changes, it is determined that a defect occurred in the sealing unit 400 .
- a defect such as a birdcaging occurs, a crack may occur in the sealing unit 400 and/or a gap may form at a position where the defect occurs. Due to the gap, the measured resistance of the sealing unit 400 may change. Accordingly, a defect occurring in the sealing unit 400 may be identified according to the change in the resistance value of the sealing unit 400 .
- a pixel circuit PC and a display device 200 in the pixel P are located on the first substrate 100 .
- the first substrate 100 may include various materials such as a glass material, a metal material, or a plastic material like polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and/or polyimide.
- the second substrate 300 may include a transparent material.
- the second substrate 300 may include various materials such as a glass material, a metal material, or a plastic material like PET, PEN, and/or polyimide.
- the first substrate 100 and the second substrate 300 may either include a same material or different materials.
- a buffer layer 101 may be formed on the first substrate 100 .
- the buffer layer 101 may block foreign materials or moisture from permeating through the first substrate 100 .
- the buffer layer 101 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON) and may include a single layer or a multi-layer.
- the buffer layer 101 may be formed to overlap the display area DA and the peripheral area PA.
- a thin film transistor 130 , a storage capacitor 140 , and a display device 200 which is electrically connected to the thin film transistor 130 and the storage capacitor 140 , may be disposed in the display area DA of the first substrate 100 .
- the thin film transistor 130 shown in FIG. 3 may correspond to the driving thin film transistor Td (see FIG. 2 ) provided in the pixel circuit PC, and the storage capacitor 140 may correspond to the storage capacitor Cst described with reference to FIG. 2 .
- the thin film transistor 130 includes a semiconductor layer 134 and a gate electrode 136 .
- the semiconductor layer 134 may include, for example, polysilicon.
- the semiconductor layer 134 may include a channel area 131 , a source area 132 , and a drain area 133 .
- the channel area 131 is disposed below the gate electrode 136 , and the source area 132 and the drain area 133 are respectively arranged at two opposite sides of the channel area 131 and doped with a higher concentration of an impurity than that of the channel area 131 .
- the impurity may include an N-type impurity or a P-type impurity.
- the source area 132 and the drain area 133 may be understood as a source electrode and the drain electrode of the thin film transistor 130 .
- the semiconductor layer 134 may include amorphous silicon or an organic semiconductor material.
- the semiconductor layer 134 may include an oxide semiconductor.
- the pixel circuit PC may further include the switching thin film transistor Ts (see FIG. 2 ).
- the semiconductor layer 134 of the thin film transistor 130 and a semiconductor layer of the switching thin film transistor Ts may include different materials.
- one may include a semiconductor layer and the other may include polysilicon.
- the present inventive concept is not limited thereto; for example, the semiconductor layer 134 of the thin film transistor 130 and the semiconductor layer of the switching film transistor Ts may include the same material as each other.
- a gate insulating layer 103 may be disposed between the semiconductor layer 134 and the gate electrode 136 .
- the gate insulating layer 103 may include an inorganic insulating layer such as SiON, SiOx, and/or SiNx, and the inorganic insulating layer may include a single layer or a multi-layer.
- the storage capacitor 140 includes a lower electrode 144 and an upper electrode 146 overlapping the lower electrode 144 .
- a first interlayer insulating layer 105 may be disposed between the lower electrode 144 and the upper electrode 146 .
- the first interlayer insulating layer 105 which has permittivity, may include an inorganic insulating layer including SiON, SiOx, and/or SiNx, and may include a single layer or a multi-layer.
- the storage capacitor 140 overlaps the thin film transistor 130 , and a lower electrode 144 is the gate electrode 136 of the thin film transistor 130 , but the present inventive concept is not limited thereto. In an exemplary embodiment of the present inventive concept, the storage capacitor 140 might not overlap the thin film transistor 130 , and the lower electrode 144 may be an independent element separate from the gate electrode 136 of the thin film transistor 130 .
- the storage capacitor 140 may be covered by a second interlayer insulating layer 107 .
- the second interlayer insulating layer 107 may include an inorganic insulating layer such as SiON, SiOx, and/or SiNx and may include a single layer or a multi-layer.
- the driving voltage line PL may be on a first organic insulating layer 111 .
- the driving voltage line PL which may include, for example, aluminum (Al), copper (Cu), titanium (Ti), and the like, may include a multi-layer or a single layer.
- the driving voltage line PL may include a multi-layer structure of Ti/Al/Ti.
- a lower driving voltage line PL 1 is disposed under the first organic insulating layer 111 .
- the lower driving voltage line PL 1 is electrically connected to the driving voltage line PL via a contact hole penetrating through the first organic insulating layer 111 , thereby preventing voltage drop of the driving voltage ELVDD provided through the driving voltage line PL.
- the lower driving voltage line PL 1 may include a material substantially identical to that of the data line DL.
- the lower driving power voltage line PL 1 and the data line DL may include Al, Cu, Ti, and the like and may include a multi-layer or a single layer.
- the lower driving voltage line PL 1 and the data line DL may include a multi-layer structure such as Ti/Al/Ti or TiN/Al/Ti.
- the first organic insulating layer 111 includes an organic insulating material.
- the organic insulating material may include a general purpose polymer such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acryl-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene based polymer, a vinyl alcohol-based polymer, and a blend thereof.
- PMMA poly(methyl methacrylate)
- PS polystyrene
- the driving voltage line PL is covered by a second organic insulating layer 113 , and the second organic insulating layer 113 may include an imide-based polymer, a general purpose polymer such as PMMA or PS, a polymer derivative having a phenol group, an acryl-based polymer, an aryl-ether based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene polymer, a vinyl alcohol-based polymer, and a blend thereof.
- the second organic insulating layer 113 may include polyimide.
- a pixel electrode 210 is arranged on the second organic insulating layer 113 .
- a pixel defining layer 120 is disposed on the pixel electrode 210 and may provide an area for an emission layer by including an opening corresponding to a pixel. For example, the opening may expose at least a center portion of the pixel electrode 210 .
- the pixel defining layer 120 may increase a distance between an edge of the pixel electrode 210 and the common electrode 230 , thereby preventing an arc and so on from being generated between the edge of the pixel electrode 210 and the common electrode 230 .
- the pixel defining layer 120 may, for example, include an organic material such as polyimide or hexamethyldisiloxane (HMDSO).
- the intermediate layer 220 may include a low molecular weight material or a high molecular weight material.
- the intermediate layer 220 may include a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), and the like are stacked in a single or complex structure, and may include various organic materials such as copper phthalocyanine (CuPc), N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3).
- CuPc copper phthalocyanine
- NPB N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine
- Alq3 tris-8-hydroxyquinoline aluminum
- the intermediate layer 220 when the intermediate layer 220 includes a high molecular weight material, the intermediate layer 220 may include an HTL and an EML.
- the HTL may include PEDOT
- the EML may include a high molecular weight material such as a poly-phenylenevinylene based material or a polyfluorene based material.
- a structure of the intermediate layer 220 is not limited thereto, and the intermediate layer 220 may have various structures.
- at least one of the above-mentioned layers included in the intermediate layer 220 may be integrally formed over a plurality of pixel electrodes 210 .
- the intermediate layer 220 may include layers that are patterned to respectively correspond to the plurality of pixel electrodes 210 .
- the common electrode 230 may be disposed above the display area DA so as to cover the display area DA.
- the common electrode 230 may be integrally formed to cover the plurality of pixels.
- the common electrode 230 may be disposed on the intermediate layer 220 .
- a filling material may be disposed between the common electrode 230 and the second substrate 300 .
- the filling material may, for example, include at least one of a photocurable epoxy-based material and/or an acrylate-based material, but the present inventive concept is not limited thereto.
- the driving unit 20 , the common power supply line 70 , and the like may be disposed in the peripheral area PA of the first substrate 100 .
- the driving unit 20 may include thin film transistors TFT and lines connected thereto.
- the thin film transistor TFT may be manufactured in a same process as that of the thin film transistor 130 of the pixel circuit PC.
- the common power supply line 70 may include a material substantially identical to that of the driving voltage line PL.
- the common power supply line 70 may include a multi-layer structure of Ti/Al/Ti.
- An outer end portion (e.g., a portion furthest from display device 200 ) of the common power supply line 70 may be covered by the sealing unit 400 , and an inner end portion (e.g., portion nearest the display device 200 ), which is opposite the outer end portion, may be covered by a conductive layer 212 .
- the conductive layer 212 may include a material substantially identical to that of the pixel electrode 210 .
- the conductive layer 212 may be connected to the common electrode 230 .
- the common power supply line 70 may extend toward the display area DA and be in direct contact with the common electrode 230 .
- the sealing unit 400 bonds the first substrate 100 and the second substrate 300 to each other.
- the sealing unit 400 may include frit, epoxy, and the like.
- the frit may be a paste including a material such as SiO and the like.
- the frit may further include an absorption material for absorbing a laser or an infrared ray, an organic binder, a filler for reducing the coefficient of thermal expansion, and the like. Through drying and plasticity processes, the organic binder and moisture may be removed from the frit in a paste state, and thus, the frit may be cured.
- An absorption material absorbing a laser or an infrared ray may include, for example, a transition metal compound.
- frit may be cured by a laser or the like to form the sealing unit 400 .
- the sealing unit 400 may cover an outer end portion of the common power supply line 70 and be in direct contact with a portion of the common power supply line 70 .
- the sealing unit 400 may overlap a portion of the common power supply line 70 . Accordingly, compared to another case in which the sealing unit 400 is located outside of the common power supply line 70 (e.g., not overlapping the common power supply line 70 ), a dead area of the display apparatus may be reduced by covering the common power supply line 70 with the sealing unit 400 .
- the pair of resistance measuring patterns 80 may be respectively at the upper surface and the lower surface of the sealing unit 400 .
- a first resistance measuring pattern 81 may be between the second substrate 300 and the upper surface of the sealing unit 400
- a second resistance measuring pattern 82 may be between the first substrate 100 and the lower surface of the sealing unit 400
- the first resistance measuring pattern 81 and the second resistance measuring pattern 82 may each extend from an outer surface of the sealing unit 400 toward the display area DA, and accordingly, at least whether defects occur at outer edges of the sealing unit 400 may be identified.
- the outer edges and the outer surface of the sealing unit 400 may be adjacent to the edges of the first substrate 100 .
- the cracks or exfoliation may be detected before external moisture permeates from outside into the display area DA.
- defects that may occur in the sealing unit 400 may be checked in advance before external moisture permeates from outside into the display area DA.
- the sealing unit 400 may overlap a portion of the common power supply line 70 , and therefore, to prevent a short circuit between the common power supply line 70 and the second resistance measuring pattern 82 located at a same layer, a width of the second resistance measuring pattern 82 may be smaller than the width of the sealing unit 400 .
- the sealing unit 400 may be disposed between the common power supply line 70 and the second measuring resistance pattern 82 . Accordingly, the common power supply line 70 and the second resistance measuring pattern 82 may be apart from each other.
- a width of the first resistance measuring pattern 81 may be substantially identical to a width of the second resistance measuring pattern 82 .
- the width of the first resistance measuring pattern 81 may be substantially identical to the width of the sealing unit 400 , and thus, a resistance over an entire portion of the sealing unit 400 may be measured.
- the first resistance measuring pattern 81 and the second resistance measuring pattern 82 may each include a metal material.
- the first resistance measuring pattern 81 and the second resistance measuring pattern 82 may each include a material substantially identical to that of the driving voltage line PL.
- FIG. 4 is a schematic cross-sectional view of a display apparatus 2 according to an exemplary embodiment of the present inventive concept.
- the second substrate 300 facing the first substrate 100 is disposed above the first substrate 100 , and the sealing unit 400 is disposed in the peripheral area PA between the first substrate 100 and the second substrate 300 .
- the sealing unit 400 may surround the display area DA.
- a space provided between the first substrate 100 , the second substrate 300 , and the sealing unit 400 may be spatially separated from outside to prevent external moisture or impurities from permeating into the display apparatus 2 .
- a thin film transistor (TFT) array layer, a pixel electrode PE, and a first orientation layer AL 1 may be formed on the first substrate 100 .
- the first substrate 100 may include a glass substrate and may also include a plastic substrate including PET, PEN, polyimide, and the like.
- the TFT array layer includes a switching device TFT, a plurality of gate lines, and a plurality of data lines.
- the switching device TFT which is a thin film transistor, includes an active layer AT, a gate electrode GE, a source electrode SE, and a drain electrode DE.
- a first insulating layer L 1 which is a gate insulating layer, is formed on the gate electrode GE, and the active layer AT is formed on the first insulating layer L 1 .
- the gate electrode GE and the source electrode SE and a second insulating layer L 2 are formed on the active layer AT.
- the gate electrode GE and the source electrode SE are spaced apart from each other, and the second insulating layer L 2 covers the gate electrode GE and the source electrode SE.
- FIG. 4 illustrates a bottom gate-type thin film transistor in which the gate electrode GE is disposed below the active layer AT, but the present inventive concept is not limited thereto, and various types of thin film transistors, for example, a top gate-type transistor, in which the gate electrode GE is disposed on the active layer AT, may be used.
- the active layer AT may include various materials.
- the active layer AT may include an inorganic semiconductor material such as amorphous silicon or crystalline silicon.
- the active layer AT may include an oxide semiconductor.
- the active layer AT may include an organic semiconductor material.
- the gate electrode GE, the source electrode SE, and the drain electrode DE may each include, for example, a single layer or a multi-layer including at least one of Al, platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), Ti, tungsten (W), and/or Cu.
- the first insulating layer L 1 and the second insulating material L 2 may each include various kinds of insulating materials.
- the first insulating layer L 1 and the second insulating layer L 2 may each include a single layer or a multi-layer structure including at least one of SiO 2 , SiNx, SiON, Al 7 O 3 , TiO 2 , Ta 2 O 5 , HfO 2 , ZrO 2 , BST, and/or PZT.
- a planarization layer 250 may be further provided on the TFT array layer, and the pixel electrode PE is located on the planarization layer 250 .
- the pixel electrode PE is connected to the drain electrode DE of the switching device TFT by penetrating through the planarization layer 250 and the second insulating layer L 2 .
- the first orientation layer AL 1 for orientation of liquid crystal molecules 213 may be formed on the pixel electrode PE.
- a blocking pattern BP, a color filter CF, an overcoating layer OC, and a common electrode CE are formed on the second substrate 300 , and a second orientation layer AL 2 for orientation of the liquid crystal molecules 213 may be formed on the common electrode CE.
- the second substrate 300 may include a glass substrate or a transparent plastic substrate, and an outer surface of the second substrate 300 is a display surface DS.
- the blocking pattern BP is located on the second substrate 300 , at a position corresponding to the area where the switching device TFT, the gate line, and the data lines are formed, and may block light.
- the position of the blocking pattern BP is only illustrative, and the blocking pattern BP may be on the first substrate 100 .
- the color filter CF is located on the second substrate 300 and filters color lights.
- the position of the color filter CF is only illustrative, and the color filter CF may be located on the first substrate 100 .
- the overcoating layer OC is located on the second substrate 300 .
- the overcoating layer OC may be disposed between the color filter CF and the second substrate 300 , and may planarize a surface of the second substrate 300 .
- the present inventive concept is not limited thereto.
- the common electrode CE is arranged on the second substrate 300 and faces the pixel electrode PE, and a common voltage, which is a reference voltage for providing the polarity of a voltage to be applied to the pixel electrode PE, is applied to the common electrode CE.
- a common voltage which is a reference voltage for providing the polarity of a voltage to be applied to the pixel electrode PE, is applied to the common electrode CE.
- the common electrode CE may extend parallel to the x and y directions.
- a liquid crystal layer 203 includes the liquid crystal molecules 213 .
- the liquid crystal layer 203 is a vertical orientation-mode liquid crystal layer, but the present inventive concept is not limited thereto, and the liquid crystal molecules 213 may be oriented in a horizontal direction and be arranged with a twist by 90 degrees between the pixel electrode PE and the common electrode CE.
- the display apparatus 2 may emit light.
- a polarization layer 270 may be disposed on a display surface DS of the second substrate 300 .
- the polarization layer 270 may polarize light emitted by the display apparatus 2 .
- the pair of resistance measuring patterns 80 may be at the upper surface and the lower surface of the sealing unit 400 .
- the first resistance measuring pattern 81 may be between the second substrate 300 and the upper surface of the sealing unit 400
- the second resistance measuring pattern 82 may be between the first substrate 100 and the lower surface of the sealing unit 400 .
- the first resistance measuring pattern 81 and the second resistance measuring pattern 82 may each extend from the outer surface of the sealing unit 400 toward the display area DA, and accordingly, defects in the sealing unit 400 may be detected. Accordingly, the defects, for example, a crack in the sealing unit 400 may be found before the crack completely penetrates the sealing unit 400 .
- FIG. 5 is a schematic top-plan view illustrating the resistance measuring pattern of the display apparatus 1 shown in FIG. 1 , according to an exemplary embodiment of the present inventive concept. For clarity, FIG. 5 illustrates some of elements in the display apparatus 1 of FIG. 1 .
- a pair of resistance measuring patterns may be respectively disposed at the upper surface and the lower surface of the sealing unit 400 located between the first substrate 100 and the second substrate, and as described above, defects occurring in the sealing unit 400 may be identified by using a resistance value of the sealing unit 400 measured by the pair of resistance measuring patterns.
- a change in the resistance value of the sealing unit 400 may be detected before visually checking the entire portion of the sealing unit 400 .
- a lot of time may be consumed and a portion of the sealing unit 400 at which the defect occurred may not be identified.
- At least one of the pair of resistance measuring patterns may include a plurality of fragments 80 a , 80 b , and 80 c that are separated from one another.
- Each of the plurality of fragments 80 a , 80 b , and 80 c has a configuration that is substantially identical to that of the resistance measuring pattern 80 (see, e.g., FIG. 1 ) described above.
- the plurality of fragments 80 a , 80 b , and 80 c of the pair of resistance measuring patterns may be located at each of the upper surface and the lower surface of the sealing unit 400 and may be used for measuring a resistance of the sealing unit 400 .
- the first resistance measuring pattern 81 see FIG. 3
- the second resistance measuring pattern 82 see FIG.
- the fragments 80 a , 80 b , and 80 c may each include fragments 80 a , 80 b , and 80 c separated from one another.
- the fragments 80 a , 80 b , and 80 c of the first resistance measuring pattern 81 (see FIG. 3 ) and the fragments 80 a , 80 b , and 80 c of the second resistance measuring pattern 82 (see FIG. 3 ) may correspond with one another.
- the fragments 80 a , 80 b , and 80 c of the first resistance measuring pattern 81 and the fragments 80 a , 80 b , and 80 c of the second resistance measuring pattern 82 may have the same shape and may overlap one another.
- resistances of the sealing unit 400 measured by the plurality of fragments 80 a , 80 b , and 80 c may be resistances of areas in which the first fragment 80 a , the second fragment 80 b , and the third fragment 80 c are respectively located.
- the first substrate 100 may have four corners, and a first fragment 80 a , a second fragment 80 b , and a third fragment 80 c may be respectively at left, right, and upper edges of the first substrate 100 .
- defects in the sealing unit 400 may be detected in a region of the sealing unit 400 in which the first fragment 80 a is located, and thus, when identifying the area in which the defect occurred, a search range of the sealing unit 400 may be reduced, and therefore, an inspection time period may be reduced.
- FIGS. 6 through 8 are schematic top-plan views illustrating the resistance measuring patterns in the display apparatus 1 of FIG. 1 according to exemplary embodiments of the present inventive concept. For clarity, FIGS. 6 through 8 illustrate some elements in the display apparatus 1 of FIG. 1 .
- the resistance measuring patterns of FIGS. 6 and 7 are different from that of FIG. 1 .
- the pair of resistance measuring patterns 80 may be respectively disposed at the upper surface and the lower surface of the sealing unit 400 disposed between the first substrate 100 and the second substrate 300 , and as described above, the defects occurring in the sealing unit 400 may be identified by using the resistance value of the sealing unit 400 that is measured by the pair of resistance measuring patterns 80 .
- the resistance measuring patterns 80 do not have a straight-line shape and a bent portion on the plane.
- the resistance measuring pattern 80 has a zigzag pattern or repeatedly alternates between opposing directions, and in FIG. 7 , the resistance measuring pattern 80 includes X-letter patterns that are continuously placed.
- the resistance measuring pattern 80 may include a lattice arrangement extending around the display area DA.
- the resistance measuring pattern 80 may extend around the display area DA and include polygonal shaped spaces.
- the resistance measuring pattern 80 when the resistance measuring pattern 80 includes bent portions, a total resistance amount of the resistance measuring pattern 80 increases, and thus, a detection rate for fine exfoliation of the sealing unit 400 may be increased.
- the resistance measuring pattern 80 includes the bent portion, an area occupied by the resistance measuring pattern 80 may increase, and thus, a detection area of the sealing unit 400 may increase.
- the resistance measuring pattern 80 shown in FIG. 8 further includes extending portions 85 respectively at two opposite ends.
- the extending portions 85 which extend from two opposite ends of the resistance measuring pattern 80 toward the terminal portion 40 (see FIG. 1 ), are separate from the terminal portion 40 (see FIG. 1 ).
- the detection area of the sealing unit 400 may increase.
- the resistance measuring pattern 80 is continuously formed, however, as shown and described in FIG. 5 , the display apparatus may include the fragments of the resistance measuring pattern.
- the resistance measuring pattern 80 described in FIGS. 6 and 8 may be applied to the display apparatus 1 that is shown and described in FIGS. 1 and 3 and to the display apparatus 2 that is shown and described in FIG. 4 .
- defects occurring in the sealing material may be checked at an early state, and accordingly, the display apparatus may be manufactured with a higher yield.
- the scope of the present inventive concept is not limited to the above-mentioned effects and results.
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
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KR10-2018-0171130 | 2018-12-27 | ||
KR1020180171130A KR20200081625A (en) | 2018-12-27 | 2018-12-27 | Display device |
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CN110752243B (en) * | 2019-10-31 | 2023-01-10 | 武汉天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
WO2021232411A1 (en) * | 2020-05-22 | 2021-11-25 | 京东方科技集团股份有限公司 | Display substrate, display panel, and display device |
US20220320234A1 (en) * | 2020-09-29 | 2022-10-06 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, manufacturing method thereof, and display device |
KR20220049683A (en) * | 2020-10-14 | 2022-04-22 | 삼성디스플레이 주식회사 | Display apparatus |
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US20200209177A1 (en) | 2020-07-02 |
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