US11380537B2 - Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer - Google Patents

Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer Download PDF

Info

Publication number
US11380537B2
US11380537B2 US16/265,709 US201916265709A US11380537B2 US 11380537 B2 US11380537 B2 US 11380537B2 US 201916265709 A US201916265709 A US 201916265709A US 11380537 B2 US11380537 B2 US 11380537B2
Authority
US
United States
Prior art keywords
cleaning composition
acetate
acid
content
quaternary ammonium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US16/265,709
Other versions
US20190198315A1 (en
Inventor
Hoyoung Kim
Hyo-Sun Lee
Soojin Kim
Keonyoung KIM
Jinhye Bae
Hoon Han
Tae Soo Kwon
Jung Hun Lim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to US16/265,709 priority Critical patent/US11380537B2/en
Publication of US20190198315A1 publication Critical patent/US20190198315A1/en
Application granted granted Critical
Publication of US11380537B2 publication Critical patent/US11380537B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H10P70/15—
    • H10P70/27—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • C11D11/0047—
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/02—Inorganic compounds
    • C11D7/04—Water-soluble compounds
    • C11D7/08—Acids
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/22—Organic compounds
    • C11D7/26—Organic compounds containing oxygen
    • C11D7/261—Alcohols; Phenols
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/22—Organic compounds
    • C11D7/26—Organic compounds containing oxygen
    • C11D7/264—Aldehydes; Ketones; Acetals or ketals
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/22—Organic compounds
    • C11D7/26—Organic compounds containing oxygen
    • C11D7/266—Esters or carbonates
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/22—Organic compounds
    • C11D7/32—Organic compounds containing nitrogen
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/22—Organic compounds
    • C11D7/32—Organic compounds containing nitrogen
    • C11D7/3209—Amines or imines with one to four nitrogen atoms; Quaternized amines
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/22—Organic compounds
    • C11D7/32—Organic compounds containing nitrogen
    • C11D7/3218—Alkanolamines or alkanolimines
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D7/00—Compositions of detergents based essentially on non-surface-active compounds
    • C11D7/50—Solvents
    • C11D7/5004—Organic solvents
    • C11D7/5027—Hydrocarbons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H10P70/20—
    • H10P72/0411—
    • H10P72/74—
    • H10P95/11—
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D2111/00—Cleaning compositions characterised by the objects to be cleaned; Cleaning compositions characterised by non-standard cleaning or washing processes
    • C11D2111/10—Objects to be cleaned
    • C11D2111/14—Hard surfaces
    • C11D2111/22—Electronic devices, e.g. PCBs or semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10252—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield
    • H10P50/642—
    • H10P52/00—
    • H10P52/402—
    • H10P72/7416—
    • H10P72/744—
    • H10W72/01271—
    • H10W72/01904—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/07236—
    • H10W72/07254—
    • H10W72/241—
    • H10W72/247—
    • H10W72/252—
    • H10W72/29—
    • H10W72/942—
    • H10W72/944—
    • H10W72/952—
    • H10W90/26—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—

Definitions

  • Embodiments of the inventive concepts relate to a method of processing a substrate, a method of cleaning a substrate, and a cleaning composition for an adhesive layer.
  • a semiconductor substrate may be processed to reduce a thickness of the semiconductor substrate. However, it may be beneficial to maintain electrical characteristics of the semiconductor substrate during the processing of the semiconductor substrate.
  • Embodiments of the inventive concepts may provide a method of processing a substrate, which is capable of improving a yield, and a cleaning composition used in the same.
  • a method of processing a substrate may include preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer.
  • the cleaning composition may include a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %, quaternary ammonium salt, and primary amine.
  • a cleaning composition for an adhesive layer may include a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %, quaternary ammonium salt, and primary amine.
  • a method of processing a substrate may include preparing a semiconductor substrate to which an adhesive layer adheres; and applying a cleaning composition to the semiconductor substrate to remove the adhesive layer.
  • the cleaning composition comprises: quaternary ammonium salt; and primary amine.
  • a method of processing a substrate may include providing a semiconductor substrate having a through-via, a pad, and a solder ball, wherein an adhesive layer adheres on a first surface of the semiconductor substrate and the solder ball; providing a cleaning composition on the semiconductor substrate; and removing an adhesive layer from the first surface of the semiconductor substrate and the solder ball with the cleaning composition.
  • the cleaning composition comprises: a polar solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %; quaternary ammonium salt; and primary amine.
  • FIGS. 1 to 5, 6A, 7A, and 9 are cross-sectional views illustrating a method of processing a substrate, according to some embodiments of the inventive concepts.
  • FIG. 6B is an enlarged view of a region ‘A’ of FIG. 6A .
  • FIG. 7B is an enlarged view of a region ‘A’ of FIG. 7A .
  • FIGS. 8A to 8C are schematic views illustrating a cleaning process according to some embodiments of the inventive concepts.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts.
  • first, second, third, etc. are used as labels to distinguish one element, component, region, layer or section from another element, component, region, layer or section (that may or may not be similar).
  • a first element, component, region, layer or section discussed below in one section of the specification (or claim) may be referred to as a second element, component, region, layer or section in another section of the specification (or another claim).
  • Embodiments may be illustrated herein with idealized views (although relative sizes may be exaggerated for clarity). It will be appreciated that actual implementation may vary from these exemplary views depending on manufacturing technologies and/or tolerances. Therefore, descriptions of certain features using terms such as “same,” “equal,” and geometric descriptions such as “planar,” “coplanar,” “cylindrical,” “square,” etc., as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, encompass acceptable variations from exact identicality, including nearly identical layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.
  • FIGS. 1 to 5, 6A, 7A, and 9 are cross-sectional views illustrating a method of processing a substrate, according to some embodiments of the inventive concepts.
  • FIG. 6B is an enlarged view of a region ‘A’ of FIG. 6A .
  • FIG. 7B is an enlarged view of a region ‘A’ of FIG. 7A .
  • a semiconductor substrate 100 may be provided.
  • the semiconductor substrate 100 may have a first surface 100 a and a second surface 100 b which are opposite to each other.
  • the semiconductor substrate 100 may include silicon or germanium.
  • the semiconductor substrate 100 may be a wafer-level substrate.
  • the semiconductor substrate 100 may include a plurality of semiconductor chips 101 .
  • the semiconductor substrate 100 may be divided into a plurality of semiconductor chips 101 as shown in FIG. 9 .
  • the semiconductor substrate 100 may include a circuit layer 110 , solder balls 120 , pads 130 , and through-vias 140 .
  • the circuit layer 110 may be provided on the first surface 100 a of the semiconductor substrate 100 .
  • the circuit layer 110 may include an integrated circuit.
  • the circuit layer 110 may include a memory circuit, a logic circuit, or a combination thereof.
  • the through-vias 140 may penetrate at least a portion of the semiconductor substrate 100 from the first surface 100 a of the semiconductor substrate 100 . In some embodiments, the through-vias 140 may be spaced apart from the second surface 100 b of the semiconductor substrate 100 .
  • the solder balls 120 may be provided on the first surface 100 a of the semiconductor substrate 100 .
  • the solder balls 120 may be electrically connected to the through-vias 140 and/or the integrated circuit of the circuit layer 110 .
  • the solder balls 120 may include tin, silver, copper, or any alloy thereof.
  • the pads 130 may be disposed between the solder balls 120 and the through-vias 140 , respectively.
  • the pads 130 may include a metal such as copper or aluminum.
  • the semiconductor substrate 100 may be provided on a carrier substrate 300 .
  • the first surface 100 a of the semiconductor substrate 100 may face the carrier substrate 300 .
  • the carrier substrate 300 may include glass.
  • the carrier substrate 300 may include silicon.
  • An adhesive layer 200 may be provided between the semiconductor substrate 100 and the carrier substrate 300 .
  • the adhesive layer 200 may cover the first surface 100 a of the semiconductor substrate 100 and the solder balls 120 .
  • the semiconductor substrate 100 may be adhered to the carrier substrate 300 by the adhesive layer 200 .
  • the adhesive layer 200 may include a hardened insulating resin.
  • the adhesive layer 200 may be hardened after the adhesive layer 200 is disposed between the semiconductor substrate 100 and the carrier substrate 300 .
  • the adhesive layer 200 may be disposed on either the semiconductor substrate 100 or the carrier substrate 300 , and then the other substrate may be disposed on the adhesive layer 200 before hardening the adhesive layer 200 .
  • the adhesive layer 200 may include a compound having a carbonyl group.
  • the adhesive layer 200 may include acrylic polymer.
  • the adhesive layer 200 may include a plurality of layers. In this case, the plurality of layers may include the closest layer to the semiconductor substrate 100 , and the closest layer may include acrylic polymer.
  • the process of thinning the semiconductor substrate 100 may include a polishing process, a grinding process or an etching process, which is performed on the second surface 100 b of the semiconductor substrate 100 .
  • the polishing process may include a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the thinning process of the semiconductor substrate 100 may expose the through-vias 140 at the second surface 100 b of the semiconductor substrate 100 .
  • a conductive pad 150 may be formed on the second surface 100 b of the semiconductor substrate 100 so as to be connected to a through-via 140 .
  • the carrier substrate 300 may inhibit the semiconductor substrate 100 from being damaged by an external impact.
  • the carrier substrate 300 may protect the semiconductor substrate 100 from damage so that the carrier substrate 300 may help processing the semiconductor substrate 100 in the following steps of process or manufacture.
  • a crack 250 may be formed in the adhesive layer 200 .
  • the crack 250 may be formed to remove the adhesive layer 200 in a subsequent process which will be described below with reference to FIG. 5 .
  • light 400 may be irradiated to the adhesive layer 200 to form the crack 250 .
  • the light 400 may include ultraviolet.
  • a physical impact may be applied to the adhesive layer 200 to form the crack 250 .
  • a physical impact and/or a light energy e.g., laser
  • the carrier substrate 300 may be removed from the semiconductor substrate 100 and/or the adhesive layer 200 .
  • the carrier substrate 300 may be removed from the semiconductor substrate 100 and/or the adhesive layer 200 by a physical method, e.g., by a physical force.
  • the crack 250 may further propagate in the adhesive layer 200 .
  • the crack 250 may propagate between the adhesive layer 200 and the carrier substrate 300 .
  • the adhesive layer 200 may be removed from the semiconductor substrate 100 .
  • the adhesive layer 200 may be removed from the semiconductor substrate 100 by a physical method, e.g., by a physical force.
  • a rolling tape 500 may be provided on the adhesive layer 200 .
  • the adhesive layer 200 may be adhered to the rolling tape 500 . Due to the crack 250 , an adhesive strength between the adhesive layer 200 and the rolling tape 500 may be stronger than an adhesive strength between the adhesive layer 200 and the semiconductor substrate 100 .
  • the rolling tape 500 may horizontally move, e.g., on the adhesive layer 200 .
  • the rolling tape 500 may move to separate the adhesive layer 200 from the semiconductor substrate 100 .
  • a portion of the adhesive layer 200 may remain on the semiconductor substrate 100 and the solder balls 120 to form a residue 201 .
  • the residue 201 may leave on the first surface 100 a of the semiconductor substrate 100 and the solder balls 120 .
  • the residue 201 may include the same material as the adhesive layer 200 .
  • a cleaning process may be performed on the semiconductor substrate 100 to remove the residue 201 .
  • a cleaning composition may be provided on the first surface 100 a of the semiconductor substrate 100 .
  • the cleaning composition may include a solvent, quaternary ammonium salt, and primary amine.
  • the quaternary ammonium salt may include tetramethylammonium phosphate, tetramethylammonium chloride, tetramethylammonium nitrate, dicyclohexylamine nitride, dicyclohexylammonium nitride, or any combination thereof.
  • the primary amine may include 2-aminoethanol, benzylamine, ethylene diamine, butyldiethanolamine, butylamine, cyclohexylamine, methylamine hydrochloride, 2-aminoethyl dihydrogen phosphate, methoxyamine hydrochloride, 2-aminoethyl hydrogen sulfate, 3-chloroproplyamine hydrochloride, or any combination thereof.
  • FIGS. 8A to 8C are enlarged views of the residue to illustrate the cleaning process according to some embodiments of the inventive concepts. The descriptions of the same features as the ones mentioned above will be omitted for the purpose of ease and convenience of explanation. The cleaning process will be described with reference to FIGS. 6A, 6B, 7A, and 7B as well as FIGS. 8A to 8C .
  • the residue 201 may include an insulating resin.
  • the residue 201 may include acrylic polymer.
  • the residue 201 may have a chain or net structure.
  • the cleaning composition may be provided on the residue 201 .
  • the cleaning composition may include the solvent, the quaternary ammonium salt, and the primary amine.
  • the solvent may have polarity.
  • the solvent may permeate into the residue 201 , and thus the residue 201 may swell.
  • a content of the solvent in the cleaning composition may be equal to or greater than 40 wt % and less than 90 wt %. If the content of the solvent in the cleaning composition is less than 40 wt %, the residue 201 may not sufficiently swell.
  • the solvent may include a ketone compound.
  • the ketone compound may include acetone, diacetonealcohol, acetophenone, cyclohexanone, methylethylketone, butylethylketone, heptylmethylketone, hexylmethylketone, or any combination thereof.
  • the solvent may further include an acetate-based compound.
  • the ketone compound and the acetate-based compound may have polarities.
  • the acetate-based compound may include alkyl acetate or vinyl acetate.
  • the acetate-based compound may include at least one of methyl acetate, butyl acetate, ethyl acetate, pentyl acetate, octyl acetate, amyl acetate, heptyl acetate, n-decyl acetate, dodecyl acetate, pentin acetate, isobutyl acetate, vinyl acetate, isopropyl acetate, or ethylhexyl acetate.
  • the acetate-based compound may not have toxicity.
  • the cleaning composition may further include an inorganic acid.
  • the inorganic acid may include phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, iodic acid, bromic acid, acetic acid, perchloric acid, silicic acid, boric acid, fluoroboric acid, hexafluorophosphoric acid, or any combination thereof.
  • the inorganic acid may adjust a pH of the cleaning composition.
  • the pH of the cleaning composition may be adjusted by adjusting a content of the inorganic acid.
  • the inorganic acid may have a content of 15 wt % or less in the cleaning composition.
  • the content of the inorganic acid in the cleaning composition may range from 1 wt % to 15 wt %.
  • the content of the inorganic acid in the cleaning composition may be greater than 2 wt % and equal to or less than 15 wt %.
  • the pH of the cleaning composition may range from 7 to 8.
  • the solder balls 120 and/or the pads 130 may be damaged by an alkaline or acidic solution.
  • the pH of the cleaning composition may be adjusted to prevent or inhibit the solder balls 120 and/or the pads 130 (in FIGS. 6A and 6B ) from being damaged.
  • a semiconductor manufacturing apparatus (not shown) may be damaged (e.g., corroded) by an alkaline solution. In this case, the pH of the cleaning composition may be adjusted to prevent or inhibit the semiconductor manufacturing apparatus from being damaged.
  • the cleaning composition may further include a hydroxy-benzene-based compound.
  • the hydroxy-benzene-based compound may prevent or inhibit the solder balls 120 and/or the pads 130 from corroding during the cleaning process.
  • the hydroxy-benzene-based compound may include at least one of phenol, 2-ethylphenol, 3-ethylphenol, 4-ethylphenol, 2-aminophenol, 2-fluorophenol, 4-aminophenol, 4-amino-2-nitrophenol, 2,4-dinitrophenol, 4-hydroxybenzenesulfonic acid, catechol, hydroquinone, pyrogallol, gallic acid, methylgallate, ethylgallate, n-propylgallate, or n-butylgallate.
  • a content of the hydroxy-benzene-based compound may range 0.1 wt % to 20 wt % of the cleaning composition.
  • the cleaning composition may further include an amine compound.
  • the amine compound may be different from the quaternary ammonium salt and the primary amine.
  • the amine compound may include 1,6-hexanediamine, triethanolamine, triethylamine, diisopropyl amine, trimethylamine hydrochloride, or any combination thereof.
  • the cleaning composition may not include at least one of the acetate-based compound, the inorganic acid, the hydroxy-benzene-based compound, or the amine compound.
  • the quaternary ammonium salt 601 and the primary amine 602 may be provided into the residue 201 .
  • the quaternary ammonium salt 601 and the primary amine 602 may function as a remover of the residue 201 .
  • the residue 201 may react with the quaternary ammonium salt 601 and the primary amine 602 as the following chemical formula 1, and thus the residue 201 may be decomposed into imine.
  • each of “R 1 ”, “R 2 ”, “R 3 ”, “R 4 ”, “R 5 ”, and “R 6 ” may be independently selected from a group consisting of an alkyl group, an alkene group, an alkyne group, and an aromatic group.
  • “A ⁇ ” may be a negative ion.
  • a ⁇ may be an anion present in the quaternary ammonium salt 601 .
  • the quaternary ammonium salt 601 may include an ionic bond between a quaternary ammonium cation and an anion A ⁇ .
  • the residue 201 may swell, and thus the quaternary ammonium salt 601 and the primary amine 602 may easily and quickly react with the residue 201 .
  • a sum of a content of the quaternary ammonium salt 601 and a content of the primary amine 602 may range 1 wt % to 30 wt % in the cleaning composition. If the sum of the contents of the quaternary ammonium salt 601 and the primary amine 602 is less than 1 wt %, the residue 201 may not be removed well. If the sum of the contents of the quaternary ammonium salt 601 and the primary amine 602 is greater than 30 wt %, the content of the solvent may be reduced.
  • a weight ratio of the quaternary ammonium salt 601 :the primary amine 602 may range from 3:1 to 1:3.
  • the decomposed residue (e.g., imine) may be dissolved in the solvent.
  • the decomposed residue may be exhausted to the outside through the solvent.
  • the decomposed residue may be removed from the semiconductor substrate 100 into the solvent. If the content of the solvent is less than 40 wt % in the cleaning composition, the decomposed residue may not be exhausted to the outside but may be re-adsorbed on the semiconductor substrate 100 . For example, some of the decomposed residue may be re-attached on the semiconductor substrate 100 when the content of the solvent is not enough. If the content of the solvent is equal to or greater than 90 wt % in the cleaning composition, the contents of the quaternary ammonium salt 601 and the primary amine 602 may be reduced.
  • the residue 201 of FIGS. 6A and 8C may be removed by the cleaning process.
  • the solder balls 120 may not be damaged (e.g., corroded) by the cleaning composition.
  • the semiconductor substrate 100 may be sawed to separate the plurality of semiconductor chips 101 from each other.
  • the sawing process may be performed along a scribe lane (not shown) of the semiconductor substrate 100 .
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts.
  • the descriptions of the same technical features as the ones mentioned above will be omitted or mentioned briefly for the purpose of ease and convenience of explanation.
  • a semiconductor device 1 may include a package substrate 700 , a first semiconductor chip 102 , a second semiconductor chip 103 , a third semiconductor chip 104 , and a molding layer 800 .
  • the first semiconductor chip 102 and the second semiconductor chip 103 may be manufactured as described with reference to FIGS. 1 to 9 .
  • the package substrate 700 may include a printed circuit board (PCB) or a semiconductor chip.
  • a solder 710 may be provided on a top surface of the package substrate 700 .
  • An external terminal 720 may be provided on a bottom surface of the package substrate 700 .
  • the first semiconductor chip 102 may be mounted on the package substrate 700 .
  • the first semiconductor chip 102 may include a first circuit layer 112 , a first solder ball 122 , a first pad 132 , a first through-via 142 , and a first conductive pad 152 .
  • the first circuit layer 112 , the first solder ball 122 , the first pad 132 , the first through-via 142 , and the first conductive pad 152 may be the same as the circuit layer 110 , the solder ball 120 , the pad 130 , the through-via 140 , and the conductive pad 150 described with reference to FIGS. 1 to 9 , respectively.
  • the first semiconductor chip 102 may be disposed on the package substrate 700 in such a way that the first solder ball 122 is aligned with the solder 710 .
  • a reflow process may be performed on the first solder ball 122 and the solder 710 to form a connection terminal 750 .
  • the connection terminal 750 may electrically connect the package substrate 700 and the first semiconductor chip 102 to each other. If the residue 201 remains on the first solder ball 122 , electrical characteristics of the connection terminal 750 may be deteriorated. However, according to embodiments of the inventive concepts, the residue 201 may be removed by the cleaning process described with reference to FIGS. 8A to 8C , and thus the first semiconductor chip 102 may be stably electrically connected to the package substrate 700 . Since the first solder ball 122 is not damaged in the cleaning process, electrical characteristics of the semiconductor device 1 may be improved. In addition, a manufacture yield of the semiconductor device 1 may be improved.
  • the second semiconductor chip 103 may include a second circuit layer 113 , a second solder ball 123 , a second pad 133 , a second through-via 143 , and a second conductive pad 153 .
  • the second circuit layer 113 , the second solder ball 123 , the second pad 133 , the second through-via 143 , and the second conductive pad 153 may be the same as the circuit layer 110 , the solder ball 120 , the pad 130 , the through-via 140 , and the conductive pad 150 described with reference to FIGS. 2 to 9 , respectively.
  • the second semiconductor chip 103 may be electrically connected to the first semiconductor chip 102 through the second solder ball 123 and the first conductive pad 152 .
  • an additional connection solder (not shown) may be formed between the second solder ball 123 and the first conductive pad 152 , and a reflow process may be performed on the second solder ball 123 and/or the additional connection solder.
  • the third semiconductor chip 104 may be mounted on the second semiconductor chip 103 .
  • the third semiconductor chip 104 may include a third circuit layer 114 but may not include a through-via. In certain embodiments, the third semiconductor chip 104 may include a through-via.
  • Cleaning compositions represented in the following tables 1 and 2 were manufactured. An adhesive layer was adhered to a semiconductor substrate. At this time, an acrylic polymer adhesive tape was used as the adhesive layer. The adhesive layer was removed from the semiconductor substrate. Each of the cleaning compositions was provided to the semiconductor substrate, and the semiconductor substrate was left at an environment of a temperature of 25 degrees Celsius to 50 degrees Celsius for a time of 1 minute to 30 minutes. Thereafter, the semiconductor substrate was cleaned using isopropyl alcohol and deionized water for 1 minute to remove a residue. A nitrogen gas was supplied to the semiconductor substrate to dry the semiconductor substrate. A removal rate of the residue was measured.
  • An adhesive layer was formed and removed by the same methods as the comparative examples. Thereafter, a residue was removed using a cleaning composition, and a removal rate of the residue was measured.
  • cleaning compositions represented in the following table 3 were used.
  • the removal rates of the residues 201 of the experimental examples are higher than the removal rates of the residues 201 of the comparative examples.
  • the cleaning compositions of the comparative examples 1 to 6 includes dimethyl sulfoxide (DMSO), ethyl diglycol (EDG), N-methylpyrrolidone (NMP), and/or butyl di glycol (BDG) as solvents.
  • DMSO dimethyl sulfoxide
  • EDG ethyl diglycol
  • NMP N-methylpyrrolidone
  • BDG butyl di glycol
  • the cleaning compositions of the experimental examples includes ketone compounds and acetate compounds as solvents, and thus the removal rates of the residues 201 of the experimental examples were improved.
  • the cleaning compositions of the comparative examples 7 to 10 does not include one of quaternary ammonium salt and primary amine.
  • each of the cleaning compositions of the experimental examples includes the quaternary ammonium salt and the primary amine, and thus the removal rates of the residue 201 were improved.
  • contents of the solvents were 90 wt % or greater in the cleaning compositions.
  • a content of the remover may be reduced, e.g., less than 10 wt %.
  • the contents of the solvents were less than 90 wt % in the cleaning compositions of the experimental examples, and thus the removal rates of the residue 201 were improved.
  • the solvent contents of the cleaning composition may be less than 90 wt % of the whole composition.
  • contents of removers were greater than 30 wt % in the cleaning compositions.
  • the remover includes the quaternary ammonium salt and the primary amine.
  • contents of the removers were equal to or less than 30 wt % in the cleaning compositions of the experimental examples.
  • the removal rates of the residue 201 were improved.
  • a content of the solvent was less than 40 wt % in the cleaning composition. If the content of the solvent is less than 40 wt % in the cleaning composition, the residue may not sufficiently swell or the decomposed residue may be re-adsorbed on the semiconductor substrate 100 . However, since the contents of the solvents are equal to or greater than 40 wt % in the cleaning compositions of the experimental examples, the removal rates of the residue 201 may be improved.
  • the comparative example 15 showed a relatively high removal rate of the residue 201 .
  • a semiconductor manufacturing apparatus was damaged by the cleaning composition of the comparative example 15.
  • the cleaning composition of the comparative example 15 did not include the inorganic acid, and thus the cleaning composition of the comparative example 15 showed alkalinity.
  • a pH of the cleaning composition of the comparative example 15 was greater than 8.
  • the cleaning compositions of the experimental examples included the inorganic acids, and thus each of the cleaning compositions of the experimental examples had a pH of 7 to 8.
  • the semiconductor manufacturing apparatus was not damaged.
  • the cleaning compositions of the experimental examples include inorganic acids, the semiconductor manufacturing apparatus may not be damaged.
  • the removal rates of the residues 201 of the comparative examples 7 to 15 are higher than the removal rates of the residues 201 of the comparative examples 1 to 6.
  • the solvents of the comparative examples 7 to 15 include the ketone compound and/or the acetate compound.
  • the removal rates of the comparative examples 7 to 15 may be higher than the removal rates of the comparative examples 1 to 6.
  • a cleaning composition including ketone compound and/or acetate compound may have higher removal rate of residue 201 .
  • Cleaning compositions according to embodiments of the inventive concepts may have high removal rates with respect to the residue of the adhesive layer.
  • the cleaning compositions may quickly remove the residue of the adhesive layer.
  • the cleaning compositions may not damage the solder ball and/or the pad of the semiconductor substrate. Thus, a processing yield of the semiconductor substrate may be improved.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Oil, Petroleum & Natural Gas (AREA)
  • Wood Science & Technology (AREA)
  • Emergency Medicine (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Detergent Compositions (AREA)

Abstract

Embodiments of the inventive concepts provide a method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer. The method includes preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer. The cleaning composition includes a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less thaadminn 90 wt %, quaternary ammonium salt, and primary amine.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This U.S. non-provisional patent application is a continuation of and claims priority to U.S. patent application Ser. No. 15/841,946 filed on Dec. 14, 2017, now U.S. Pat. No. 10,332,740, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0170557, filed on Dec. 14, 2016, in the Korean Intellectual Property Office, the disclosure of each of these applications being hereby incorporated by reference in its entirety.
BACKGROUND
Embodiments of the inventive concepts relate to a method of processing a substrate, a method of cleaning a substrate, and a cleaning composition for an adhesive layer.
The number of electrode terminals of a semiconductor device has been increased and a pitch of the electrode terminals has been reduced. Thus, various methods of highly integrating semiconductor devices are being studied. A semiconductor substrate may be processed to reduce a thickness of the semiconductor substrate. However, it may be beneficial to maintain electrical characteristics of the semiconductor substrate during the processing of the semiconductor substrate.
SUMMARY
Embodiments of the inventive concepts may provide a method of processing a substrate, which is capable of improving a yield, and a cleaning composition used in the same.
In an aspect, a method of processing a substrate may include preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer. The cleaning composition may include a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %, quaternary ammonium salt, and primary amine.
In an aspect, a cleaning composition for an adhesive layer may include a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %, quaternary ammonium salt, and primary amine.
In an aspect, a method of processing a substrate may include preparing a semiconductor substrate to which an adhesive layer adheres; and applying a cleaning composition to the semiconductor substrate to remove the adhesive layer. The cleaning composition comprises: quaternary ammonium salt; and primary amine.
In an aspect, a method of processing a substrate may include providing a semiconductor substrate having a through-via, a pad, and a solder ball, wherein an adhesive layer adheres on a first surface of the semiconductor substrate and the solder ball; providing a cleaning composition on the semiconductor substrate; and removing an adhesive layer from the first surface of the semiconductor substrate and the solder ball with the cleaning composition. The cleaning composition comprises: a polar solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %; quaternary ammonium salt; and primary amine.
BRIEF DESCRIPTION OF THE DRAWINGS
The inventive concepts will become more apparent in view of the attached drawings and accompanying detailed description.
FIGS. 1 to 5, 6A, 7A, and 9 are cross-sectional views illustrating a method of processing a substrate, according to some embodiments of the inventive concepts.
FIG. 6B is an enlarged view of a region ‘A’ of FIG. 6A.
FIG. 7B is an enlarged view of a region ‘A’ of FIG. 7A.
FIGS. 8A to 8C are schematic views illustrating a cleaning process according to some embodiments of the inventive concepts.
FIG. 10 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts.
 DETAILED DESCRIPTION
The present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. The invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are just that—examples—and many implementations and variations are possible that do not require the details provided herein. It should also be emphasized that the disclosure provides details of alternative examples, but such listing of alternatives is not exhaustive. Furthermore, any consistency of detail between various examples should not be interpreted as requiring such detail—it is impracticable to list every possible variation for every feature described herein. The language of the claims should be referenced in determining the requirements of the invention.
In the drawings, like numbers refer to like elements throughout. Though the different figures show various features of exemplary embodiments, these figures and their features are not necessarily intended to be mutually exclusive from each other. Rather, certain features depicted and described in a particular figure may also be implemented with embodiment(s) depicted in different figure(s), even if such a combination is not separately illustrated. Referencing such features/figures with different embodiment labels (e.g. “first embodiment”) should not be interpreted as indicating certain features of one embodiment are mutually exclusive of and are not intended to be used with another embodiment.
Unless the context indicates otherwise, the terms first, second, third, etc., are used as labels to distinguish one element, component, region, layer or section from another element, component, region, layer or section (that may or may not be similar). Thus, a first element, component, region, layer or section discussed below in one section of the specification (or claim) may be referred to as a second element, component, region, layer or section in another section of the specification (or another claim).
It will be understood that when an element is referred to as being “connected,” “coupled to” or “on” another element, it can be directly connected/coupled to/on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element's or feature's positional relationship relative to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Thus, a device depicted and/or described herein to have element A below element B, is still deemed to have element A below element B no matter the orientation of the device in the real world.
Embodiments may be illustrated herein with idealized views (although relative sizes may be exaggerated for clarity). It will be appreciated that actual implementation may vary from these exemplary views depending on manufacturing technologies and/or tolerances. Therefore, descriptions of certain features using terms such as “same,” “equal,” and geometric descriptions such as “planar,” “coplanar,” “cylindrical,” “square,” etc., as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, encompass acceptable variations from exact identicality, including nearly identical layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill consistent with their meaning in the context of the relevant art and/or the present application.
Embodiments of the inventive concepts will be described hereinafter in detail.
FIGS. 1 to 5, 6A, 7A, and 9 are cross-sectional views illustrating a method of processing a substrate, according to some embodiments of the inventive concepts. FIG. 6B is an enlarged view of a region ‘A’ of FIG. 6A. FIG. 7B is an enlarged view of a region ‘A’ of FIG. 7A.
Referring to FIG. 1, a semiconductor substrate 100 may be provided. The semiconductor substrate 100 may have a first surface 100 a and a second surface 100 b which are opposite to each other. For example, the semiconductor substrate 100 may include silicon or germanium. The semiconductor substrate 100 may be a wafer-level substrate. The semiconductor substrate 100 may include a plurality of semiconductor chips 101. For example, in a later process, the semiconductor substrate 100 may be divided into a plurality of semiconductor chips 101 as shown in FIG. 9.
The semiconductor substrate 100 may include a circuit layer 110, solder balls 120, pads 130, and through-vias 140. The circuit layer 110 may be provided on the first surface 100 a of the semiconductor substrate 100. The circuit layer 110 may include an integrated circuit. For example, the circuit layer 110 may include a memory circuit, a logic circuit, or a combination thereof. The through-vias 140 may penetrate at least a portion of the semiconductor substrate 100 from the first surface 100 a of the semiconductor substrate 100. In some embodiments, the through-vias 140 may be spaced apart from the second surface 100 b of the semiconductor substrate 100.
The solder balls 120 may be provided on the first surface 100 a of the semiconductor substrate 100. The solder balls 120 may be electrically connected to the through-vias 140 and/or the integrated circuit of the circuit layer 110. The solder balls 120 may include tin, silver, copper, or any alloy thereof. The pads 130 may be disposed between the solder balls 120 and the through-vias 140, respectively. The pads 130 may include a metal such as copper or aluminum.
The semiconductor substrate 100 may be provided on a carrier substrate 300. At this time, the first surface 100 a of the semiconductor substrate 100 may face the carrier substrate 300. The carrier substrate 300 may include glass. Alternatively, the carrier substrate 300 may include silicon. An adhesive layer 200 may be provided between the semiconductor substrate 100 and the carrier substrate 300. The adhesive layer 200 may cover the first surface 100 a of the semiconductor substrate 100 and the solder balls 120. The semiconductor substrate 100 may be adhered to the carrier substrate 300 by the adhesive layer 200. The adhesive layer 200 may include a hardened insulating resin. For example, the adhesive layer 200 may be hardened after the adhesive layer 200 is disposed between the semiconductor substrate 100 and the carrier substrate 300. For example, the adhesive layer 200 may be disposed on either the semiconductor substrate 100 or the carrier substrate 300, and then the other substrate may be disposed on the adhesive layer 200 before hardening the adhesive layer 200. The adhesive layer 200 may include a compound having a carbonyl group. For example, the adhesive layer 200 may include acrylic polymer. Unlike FIG. 1, the adhesive layer 200 may include a plurality of layers. In this case, the plurality of layers may include the closest layer to the semiconductor substrate 100, and the closest layer may include acrylic polymer.
Referring to FIG. 2, a portion of the semiconductor substrate 100 may be removed to thin the semiconductor substrate 100. The process of thinning the semiconductor substrate 100 may include a polishing process, a grinding process or an etching process, which is performed on the second surface 100 b of the semiconductor substrate 100. The polishing process may include a chemical mechanical polishing (CMP) process. The thinning process of the semiconductor substrate 100 may expose the through-vias 140 at the second surface 100 b of the semiconductor substrate 100. A conductive pad 150 may be formed on the second surface 100 b of the semiconductor substrate 100 so as to be connected to a through-via 140. When the semiconductor substrate 100 is processed, the thinned semiconductor substrate 100 may be easily handled by the carrier substrate 300. For example, the carrier substrate 300 may inhibit the semiconductor substrate 100 from being damaged by an external impact. For example, the carrier substrate 300 may protect the semiconductor substrate 100 from damage so that the carrier substrate 300 may help processing the semiconductor substrate 100 in the following steps of process or manufacture.
Referring to FIG. 3, a crack 250 may be formed in the adhesive layer 200. The crack 250 may be formed to remove the adhesive layer 200 in a subsequent process which will be described below with reference to FIG. 5. In some embodiments, light 400 may be irradiated to the adhesive layer 200 to form the crack 250. The light 400 may include ultraviolet. In certain embodiments, a physical impact may be applied to the adhesive layer 200 to form the crack 250. For example, in certain embodiments, a physical impact and/or a light energy (e.g., laser) may be applied to the adhesive layer 200 to form a crack 250 and/or to separate the semiconductor substrate 100 and the carrier substrate 300 from each other.
Referring to FIG. 4, the carrier substrate 300 may be removed from the semiconductor substrate 100 and/or the adhesive layer 200. For example, the carrier substrate 300 may be removed from the semiconductor substrate 100 and/or the adhesive layer 200 by a physical method, e.g., by a physical force. When the carrier substrate 300 is removed from the adhesive layer 200, the crack 250 may further propagate in the adhesive layer 200. For example, the crack 250 may propagate between the adhesive layer 200 and the carrier substrate 300.
Referring to FIG. 5, the adhesive layer 200 may be removed from the semiconductor substrate 100. The adhesive layer 200 may be removed from the semiconductor substrate 100 by a physical method, e.g., by a physical force. For example, a rolling tape 500 may be provided on the adhesive layer 200. The adhesive layer 200 may be adhered to the rolling tape 500. Due to the crack 250, an adhesive strength between the adhesive layer 200 and the rolling tape 500 may be stronger than an adhesive strength between the adhesive layer 200 and the semiconductor substrate 100. The rolling tape 500 may horizontally move, e.g., on the adhesive layer 200. The rolling tape 500 may move to separate the adhesive layer 200 from the semiconductor substrate 100.
Referring to FIGS. 6A and 6B, a portion of the adhesive layer 200 may remain on the semiconductor substrate 100 and the solder balls 120 to form a residue 201. For example, the residue 201 may leave on the first surface 100 a of the semiconductor substrate 100 and the solder balls 120. The residue 201 may include the same material as the adhesive layer 200.
Referring to FIGS. 7A and 7B, a cleaning process may be performed on the semiconductor substrate 100 to remove the residue 201. In the cleaning process, a cleaning composition may be provided on the first surface 100 a of the semiconductor substrate 100. The cleaning composition may include a solvent, quaternary ammonium salt, and primary amine.
For example, the quaternary ammonium salt may include tetramethylammonium phosphate, tetramethylammonium chloride, tetramethylammonium nitrate, dicyclohexylamine nitride, dicyclohexylammonium nitride, or any combination thereof. The primary amine may include 2-aminoethanol, benzylamine, ethylene diamine, butyldiethanolamine, butylamine, cyclohexylamine, methylamine hydrochloride, 2-aminoethyl dihydrogen phosphate, methoxyamine hydrochloride, 2-aminoethyl hydrogen sulfate, 3-chloroproplyamine hydrochloride, or any combination thereof.
The cleaning composition according to some embodiments and the cleaning process using the same will be described hereinafter in more detail.
FIGS. 8A to 8C are enlarged views of the residue to illustrate the cleaning process according to some embodiments of the inventive concepts. The descriptions of the same features as the ones mentioned above will be omitted for the purpose of ease and convenience of explanation. The cleaning process will be described with reference to FIGS. 6A, 6B, 7A, and 7B as well as FIGS. 8A to 8C.
Referring to FIG. 8A, the residue 201 may include an insulating resin. For example, the residue 201 may include acrylic polymer. The residue 201 may have a chain or net structure.
Referring to FIG. 8B, the cleaning composition may be provided on the residue 201. As described above, the cleaning composition may include the solvent, the quaternary ammonium salt, and the primary amine. The solvent may have polarity. The solvent may permeate into the residue 201, and thus the residue 201 may swell. A content of the solvent in the cleaning composition may be equal to or greater than 40 wt % and less than 90 wt %. If the content of the solvent in the cleaning composition is less than 40 wt %, the residue 201 may not sufficiently swell. The solvent may include a ketone compound. For example, the ketone compound may include acetone, diacetonealcohol, acetophenone, cyclohexanone, methylethylketone, butylethylketone, heptylmethylketone, hexylmethylketone, or any combination thereof. The solvent may further include an acetate-based compound. The ketone compound and the acetate-based compound may have polarities. The acetate-based compound may include alkyl acetate or vinyl acetate. For example, the acetate-based compound may include at least one of methyl acetate, butyl acetate, ethyl acetate, pentyl acetate, octyl acetate, amyl acetate, heptyl acetate, n-decyl acetate, dodecyl acetate, pentin acetate, isobutyl acetate, vinyl acetate, isopropyl acetate, or ethylhexyl acetate. The acetate-based compound may not have toxicity.
The cleaning composition may further include an inorganic acid. The inorganic acid may include phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, iodic acid, bromic acid, acetic acid, perchloric acid, silicic acid, boric acid, fluoroboric acid, hexafluorophosphoric acid, or any combination thereof. The inorganic acid may adjust a pH of the cleaning composition. For example, the pH of the cleaning composition may be adjusted by adjusting a content of the inorganic acid. For example, the inorganic acid may have a content of 15 wt % or less in the cleaning composition. For example, the content of the inorganic acid in the cleaning composition may range from 1 wt % to 15 wt %. For example, the content of the inorganic acid in the cleaning composition may be greater than 2 wt % and equal to or less than 15 wt %. The pH of the cleaning composition may range from 7 to 8. The solder balls 120 and/or the pads 130 may be damaged by an alkaline or acidic solution. However, according to some embodiments of the inventive concepts, the pH of the cleaning composition may be adjusted to prevent or inhibit the solder balls 120 and/or the pads 130 (in FIGS. 6A and 6B) from being damaged. For example, a semiconductor manufacturing apparatus (not shown) may be damaged (e.g., corroded) by an alkaline solution. In this case, the pH of the cleaning composition may be adjusted to prevent or inhibit the semiconductor manufacturing apparatus from being damaged.
The cleaning composition may further include a hydroxy-benzene-based compound. The hydroxy-benzene-based compound may prevent or inhibit the solder balls 120 and/or the pads 130 from corroding during the cleaning process. The hydroxy-benzene-based compound may include at least one of phenol, 2-ethylphenol, 3-ethylphenol, 4-ethylphenol, 2-aminophenol, 2-fluorophenol, 4-aminophenol, 4-amino-2-nitrophenol, 2,4-dinitrophenol, 4-hydroxybenzenesulfonic acid, catechol, hydroquinone, pyrogallol, gallic acid, methylgallate, ethylgallate, n-propylgallate, or n-butylgallate. A content of the hydroxy-benzene-based compound may range 0.1 wt % to 20 wt % of the cleaning composition.
The cleaning composition may further include an amine compound. The amine compound may be different from the quaternary ammonium salt and the primary amine. For example, the amine compound may include 1,6-hexanediamine, triethanolamine, triethylamine, diisopropyl amine, trimethylamine hydrochloride, or any combination thereof.
In certain embodiments, the cleaning composition may not include at least one of the acetate-based compound, the inorganic acid, the hydroxy-benzene-based compound, or the amine compound.
Referring to FIG. 8C, the quaternary ammonium salt 601 and the primary amine 602 may be provided into the residue 201. The quaternary ammonium salt 601 and the primary amine 602 may function as a remover of the residue 201. The residue 201 may react with the quaternary ammonium salt 601 and the primary amine 602 as the following chemical formula 1, and thus the residue 201 may be decomposed into imine.
Figure US11380537-20220705-C00001
In the chemical formula 1, each of “R1”, “R2”, “R3”, “R4”, “R5”, and “R6” may be independently selected from a group consisting of an alkyl group, an alkene group, an alkyne group, and an aromatic group. “A−” may be a negative ion. For example, A− may be an anion present in the quaternary ammonium salt 601. For example, the quaternary ammonium salt 601 may include an ionic bond between a quaternary ammonium cation and an anion A−.
The residue 201 may swell, and thus the quaternary ammonium salt 601 and the primary amine 602 may easily and quickly react with the residue 201. A sum of a content of the quaternary ammonium salt 601 and a content of the primary amine 602 may range 1 wt % to 30 wt % in the cleaning composition. If the sum of the contents of the quaternary ammonium salt 601 and the primary amine 602 is less than 1 wt %, the residue 201 may not be removed well. If the sum of the contents of the quaternary ammonium salt 601 and the primary amine 602 is greater than 30 wt %, the content of the solvent may be reduced. A weight ratio of the quaternary ammonium salt 601:the primary amine 602 may range from 3:1 to 1:3.
Since the solvent has polarity, the decomposed residue (e.g., imine) may be dissolved in the solvent. The decomposed residue may be exhausted to the outside through the solvent. For example, the decomposed residue may be removed from the semiconductor substrate 100 into the solvent. If the content of the solvent is less than 40 wt % in the cleaning composition, the decomposed residue may not be exhausted to the outside but may be re-adsorbed on the semiconductor substrate 100. For example, some of the decomposed residue may be re-attached on the semiconductor substrate 100 when the content of the solvent is not enough. If the content of the solvent is equal to or greater than 90 wt % in the cleaning composition, the contents of the quaternary ammonium salt 601 and the primary amine 602 may be reduced.
Referring again to FIGS. 7A and 7B, the residue 201 of FIGS. 6A and 8C may be removed by the cleaning process. At this time, the solder balls 120 may not be damaged (e.g., corroded) by the cleaning composition.
Referring to FIG. 9, the semiconductor substrate 100 may be sawed to separate the plurality of semiconductor chips 101 from each other. The sawing process may be performed along a scribe lane (not shown) of the semiconductor substrate 100.
FIG. 10 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, the descriptions of the same technical features as the ones mentioned above will be omitted or mentioned briefly for the purpose of ease and convenience of explanation.
Referring to FIG. 10, a semiconductor device 1 may include a package substrate 700, a first semiconductor chip 102, a second semiconductor chip 103, a third semiconductor chip 104, and a molding layer 800. The first semiconductor chip 102 and the second semiconductor chip 103 may be manufactured as described with reference to FIGS. 1 to 9. In some embodiments, the package substrate 700 may include a printed circuit board (PCB) or a semiconductor chip. A solder 710 may be provided on a top surface of the package substrate 700. An external terminal 720 may be provided on a bottom surface of the package substrate 700.
The first semiconductor chip 102 may be mounted on the package substrate 700. The first semiconductor chip 102 may include a first circuit layer 112, a first solder ball 122, a first pad 132, a first through-via 142, and a first conductive pad 152. The first circuit layer 112, the first solder ball 122, the first pad 132, the first through-via 142, and the first conductive pad 152 may be the same as the circuit layer 110, the solder ball 120, the pad 130, the through-via 140, and the conductive pad 150 described with reference to FIGS. 1 to 9, respectively. The first semiconductor chip 102 may be disposed on the package substrate 700 in such a way that the first solder ball 122 is aligned with the solder 710. A reflow process may be performed on the first solder ball 122 and the solder 710 to form a connection terminal 750. The connection terminal 750 may electrically connect the package substrate 700 and the first semiconductor chip 102 to each other. If the residue 201 remains on the first solder ball 122, electrical characteristics of the connection terminal 750 may be deteriorated. However, according to embodiments of the inventive concepts, the residue 201 may be removed by the cleaning process described with reference to FIGS. 8A to 8C, and thus the first semiconductor chip 102 may be stably electrically connected to the package substrate 700. Since the first solder ball 122 is not damaged in the cleaning process, electrical characteristics of the semiconductor device 1 may be improved. In addition, a manufacture yield of the semiconductor device 1 may be improved.
The second semiconductor chip 103 may include a second circuit layer 113, a second solder ball 123, a second pad 133, a second through-via 143, and a second conductive pad 153. The second circuit layer 113, the second solder ball 123, the second pad 133, the second through-via 143, and the second conductive pad 153 may be the same as the circuit layer 110, the solder ball 120, the pad 130, the through-via 140, and the conductive pad 150 described with reference to FIGS. 2 to 9, respectively. The second semiconductor chip 103 may be electrically connected to the first semiconductor chip 102 through the second solder ball 123 and the first conductive pad 152. In certain embodiments, an additional connection solder (not shown) may be formed between the second solder ball 123 and the first conductive pad 152, and a reflow process may be performed on the second solder ball 123 and/or the additional connection solder. The third semiconductor chip 104 may be mounted on the second semiconductor chip 103. The third semiconductor chip 104 may include a third circuit layer 114 but may not include a through-via. In certain embodiments, the third semiconductor chip 104 may include a through-via.
Hereinafter, the method of cleaning a substrate using the cleaning composition will be described with reference to experimental examples of the inventive concepts and comparative examples.
Manufacture of Cleaning Composition and Cleaning of Substrate Comparative Examples
Cleaning compositions represented in the following tables 1 and 2 were manufactured. An adhesive layer was adhered to a semiconductor substrate. At this time, an acrylic polymer adhesive tape was used as the adhesive layer. The adhesive layer was removed from the semiconductor substrate. Each of the cleaning compositions was provided to the semiconductor substrate, and the semiconductor substrate was left at an environment of a temperature of 25 degrees Celsius to 50 degrees Celsius for a time of 1 minute to 30 minutes. Thereafter, the semiconductor substrate was cleaned using isopropyl alcohol and deionized water for 1 minute to remove a residue. A nitrogen gas was supplied to the semiconductor substrate to dry the semiconductor substrate. A removal rate of the residue was measured.
TABLE 1
Removal
Kind and Content (wt %) of Cleaning composition rate of
Comparative Solvent Remover Residue
example DMSO EDG NMP BDG TMAH HDZ HDA (%)
1 85 5 1.25 2.5 10
2 40 50 1.25 2.5 8
3 20 2.4 12 15
4 20 12 24 21
5 3 20 6 2.4 13
6 3 70 6 2.4 20
DMSO: Dimethyl sulfoxide
EDG: Ethyl diglycol
NMP: N-methylpyrrolidone
BDG: Butyl di glycol
TMAH: Tetramethylammonium hydroxide
HDZ: Hydrazine
HDA: Hydroxyl amine
TABLE 2
Kind and Content (wt %) of Cleaning composition
Remover Removal
Solvent Quaternary rate of
Comparative Ketone Acetate Hydroxy-benzene-based compound Inorganic Amine ammonium Primary Residue
example compound compound A B C acid compound salt amine (%)
7 53 24 — 6 — 10 — 7 — 30
8 46 24 — 6 — 10 — 14 — 55
9 53 24 — 6 — 10 — — 7 45
10 46 24 — 6 — 10 — — 14 70
11 68 24 — 6 — 1 — 0.5 0.5 35
12 66 24 — 6 — 2 — 1 1 40
13 6 24 — 6 — 30 — 17 17 60
14 20 24 — 6 10 20 20 60
15 — 86 2 — — 12 — 90
Ketone compound: Methyl ethyl ketone
Acetate-based compound: Isopropyl acetate
Hydroxy-benzene-based compound A: Propyl gallate
Hydroxy-benzene-based compound B: Methyl gallate
Hydroxy-benzene-based compound C: Catechol
Inorganic acid: phosphoric acid
Amine compound: Ethylenediamine
Quaternary ammonium salt: Tetramethylammonium hydroxide
Primary amine: 2-Aminoethanol
Experimental Examples
An adhesive layer was formed and removed by the same methods as the comparative examples. Thereafter, a residue was removed using a cleaning composition, and a removal rate of the residue was measured. However, in the experimental examples, cleaning compositions represented in the following table 3 were used.
TABLE 3
Kind and Content (wt %) of Cleaning composition
Remover Removal
Solvent Quaternary rate of
Experimental Ketone Acetate Hydroxy-benzene-based compound Inorganic Amine ammonium Primary Residue
example compound compound A B C acid compound salt amine (%)
1 50 24 2 — 10 — 7 7 70
2 48 24 — 4 — 10 — 7 7 80
3 46 24 — 6 — 10 — 7 7 90
4 33 24 — 6 10 13.5 13.5 80
5 46 24 — 6 — 10 — 3.5 10.5 75
6 46 24 — 6 10 10.5 3.5 80
7 64 24 — — 6 2.5 1.25 1.25 65
8 58 24 — — 6 5 3.50 3.50 75
9 16 24 — — 25 14.5 14.5 70
Ketone compound: Methyl ethyl ketone
Acetate-based compound: Isopropyl acetate
Hydroxy-benzene-based compound A: Propyl gallate
Hydroxy-benzene-based compound B: Methyl gallate
Hydroxy-benzene-based compound C: Catechol
Inorganic acid: phosphoric acid
Amine compound: Ethylenediamine
Quaternary ammonium salt: Tetramethylammonium hydroxide
Primary amine: 2-Aminoethanol
Referring to the tables 1 to 3 and FIGS. 6A, 6B, 7A, and 7B, the removal rates of the residues 201 of the experimental examples are higher than the removal rates of the residues 201 of the comparative examples. The cleaning compositions of the comparative examples 1 to 6 includes dimethyl sulfoxide (DMSO), ethyl diglycol (EDG), N-methylpyrrolidone (NMP), and/or butyl di glycol (BDG) as solvents. However, the cleaning compositions of the experimental examples includes ketone compounds and acetate compounds as solvents, and thus the removal rates of the residues 201 of the experimental examples were improved.
The cleaning compositions of the comparative examples 7 to 10 does not include one of quaternary ammonium salt and primary amine. However, each of the cleaning compositions of the experimental examples includes the quaternary ammonium salt and the primary amine, and thus the removal rates of the residue 201 were improved.
In the comparative examples 11 and 12, contents of the solvents were 90 wt % or greater in the cleaning compositions. When the content of the solvent is equal to or greater than 90 wt % in the cleaning composition, a content of the remover may be reduced, e.g., less than 10 wt %. However, the contents of the solvents were less than 90 wt % in the cleaning compositions of the experimental examples, and thus the removal rates of the residue 201 were improved. For example, for a better residue removal, it is beneficial that the solvent contents of the cleaning composition may be less than 90 wt % of the whole composition.
In the comparative examples 13 and 14, contents of removers were greater than 30 wt % in the cleaning compositions. Here, the remover includes the quaternary ammonium salt and the primary amine. However, contents of the removers were equal to or less than 30 wt % in the cleaning compositions of the experimental examples. Thus, the removal rates of the residue 201 were improved.
In the comparative example 13, a content of the solvent was less than 40 wt % in the cleaning composition. If the content of the solvent is less than 40 wt % in the cleaning composition, the residue may not sufficiently swell or the decomposed residue may be re-adsorbed on the semiconductor substrate 100. However, since the contents of the solvents are equal to or greater than 40 wt % in the cleaning compositions of the experimental examples, the removal rates of the residue 201 may be improved.
The comparative example 15 showed a relatively high removal rate of the residue 201. However, a semiconductor manufacturing apparatus was damaged by the cleaning composition of the comparative example 15. The cleaning composition of the comparative example 15 did not include the inorganic acid, and thus the cleaning composition of the comparative example 15 showed alkalinity. For example, a pH of the cleaning composition of the comparative example 15 was greater than 8. However, the cleaning compositions of the experimental examples included the inorganic acids, and thus each of the cleaning compositions of the experimental examples had a pH of 7 to 8. In the experimental examples, the semiconductor manufacturing apparatus was not damaged. For example, when the cleaning compositions of the experimental examples include inorganic acids, the semiconductor manufacturing apparatus may not be damaged.
The removal rates of the residues 201 of the comparative examples 7 to 15 are higher than the removal rates of the residues 201 of the comparative examples 1 to 6. The solvents of the comparative examples 7 to 15 include the ketone compound and/or the acetate compound. Thus, the removal rates of the comparative examples 7 to 15 may be higher than the removal rates of the comparative examples 1 to 6. For example, a cleaning composition including ketone compound and/or acetate compound may have higher removal rate of residue 201.
Cleaning compositions according to embodiments of the inventive concepts may have high removal rates with respect to the residue of the adhesive layer. The cleaning compositions may quickly remove the residue of the adhesive layer. The cleaning compositions may not damage the solder ball and/or the pad of the semiconductor substrate. Thus, a processing yield of the semiconductor substrate may be improved.
While the inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of the inventive concepts are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing descriptions.

Claims (8)

What is claimed is:
1. A cleaning composition, the cleaning composition comprising:
a polar solvent having a content that is equal to or greater than 40 wt % and less than 90 wt %, wherein the polar solvent is a mixture of a ketone compound and an acetate-based compound;
a quaternary ammonium salt selected from tetramethylammonium hydroxide, tetramethylammonium phosphate, dicyclohexylammonium nitride, or any combination thereof;
a primary amine selected from 2-aminoethanol, benzylamine, ethylene diamine, butyldiethanolamine, butylamine, cyclohexylamine, or any combination thereof;
an inorganic acid having a content that ranges from 1 wt % to 15 wt %, the inorganic acid selected from phosphoric acid, acetic acid, silicic acid, hexafluorophosphoric acid, or any combination thereof; and
a hydroxyl-benzene-based compound having a content that ranges from 0.1 wt % to 20 wt %, the hydroxyl-benzene-based compound selected from at least one of 4-hydroxybenzenesulfonic acid, catechol, hydroquinone, pyrogallol, gallic acid, methylgallate, ethylgallate, or n-propylgallate;
wherein a pH of the cleaning composition ranges from 7 to 8; and
wherein a weight ratio of the quaternary ammonium salt to the primary amine ranges from 3:1 to 1:3; and
wherein a sum of a content of the quaternary ammonium salt and a content of the primary amine ranges from 1 wt % to 30 wt %.
2. The cleaning composition of claim 1, wherein the acetate-based compound comprises alkyl acetate or vinyl acetate.
3. The cleaning composition of claim 1, further comprising
an amine compound comprising a material different from the quaternary ammonium salt and the primary amine.
4. The cleaning composition of claim 1, wherein the ketone compound comprises acetone, diacetonealcohol, acetophenone, cyclohexanone, methylethylketone, butyl ethylketone, heptylmethylketone, hexylmethylketone, or any combination thereof.
5. A cleaning composition for an adhesive layer, the cleaning composition comprising:
a polar solvent which is a mixture of a ketone compound and an acetate-based compound, the polar solvent having a content that is equal to or greater than 40 wt % and less than 90 wt %;
a quaternary ammonium salt selected from tetramethylammonium hydroxide, tetramethylammonium phosphate, dicyclohexylammonium nitride, or any combination thereof;
a primary amine selected from 2-aminoethanol, benzylamine, ethylene diamine, butyldiethanolamine, butylamine, cyclohexylamine, or any combination thereof;
a hydroxyl-benzene-based compound, a content of the hydroxyl-benzene-based compound ranging from 0.1 wt % to 20 wt %;
an inorganic acid having a content that ranges from 1 wt % to 15 wt %;
wherein a sum of a content of the quaternary ammonium salt and a content of the primary amine ranges from 1 wt % to 30 wt %;
wherein the inorganic acid is selected from phosphoric acid, acetic acid, silicic acid, hexafluorophosphoric acid, or any combination there, wherein the hydroxyl-benzene-based comprises at least one of 4-hydroxybenzenesulfonic acid, catechol, hydroquinone, pyrogallol, gallic acid, methylgallate, ethylgallate, or n-propylgallate;
wherein a weight ratio of the quaternary ammonium salt to the primary amine ranges from 3:1 to 1:3;
wherein a pH of the cleaning composition ranges from 7 to 8; and
wherein the quaternary ammonium salt and the primary amine are capable of reacting with a polymer adhesive residue to form an imine.
6. The cleaning composition of claim 5, further comprising an amine compound,
wherein the amine compound comprises a material different from the quaternary ammonium salt and the primary amine.
7. The cleaning composition of claim 5,
wherein the acetate-based compound is selected from at least one of ethyl acetate, octyl acetate, amyl acetate, vinyl acetate, isopropyl acetate, or ethylhexyl acetate.
8. The cleaning composition of claim 5, wherein the ketone compound is capable of swelling the polymer adhesive residue.
US16/265,709 2016-12-14 2019-02-01 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer Active 2038-06-30 US11380537B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/265,709 US11380537B2 (en) 2016-12-14 2019-02-01 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020160170557A KR102680736B1 (en) 2016-12-14 2016-12-14 Method for processing substrate and cleaner composition for adhension layer
KR10-2016-0170557 2016-12-14
US15/841,946 US10332740B2 (en) 2016-12-14 2017-12-14 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer
US16/265,709 US11380537B2 (en) 2016-12-14 2019-02-01 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/841,946 Continuation US10332740B2 (en) 2016-12-14 2017-12-14 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer

Publications (2)

Publication Number Publication Date
US20190198315A1 US20190198315A1 (en) 2019-06-27
US11380537B2 true US11380537B2 (en) 2022-07-05

Family

ID=62806003

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/841,946 Active US10332740B2 (en) 2016-12-14 2017-12-14 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer
US16/265,709 Active 2038-06-30 US11380537B2 (en) 2016-12-14 2019-02-01 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US15/841,946 Active US10332740B2 (en) 2016-12-14 2017-12-14 Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer

Country Status (2)

Country Link
US (2) US10332740B2 (en)
KR (1) KR102680736B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210320078A1 (en) * 2018-08-08 2021-10-14 Kuprion Inc. Electronics assemblies employing copper in multiple locations

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102195007B1 (en) * 2018-10-11 2020-12-29 세메스 주식회사 Substrate cleaning compositions, substrate cleaning method and substrate treating apparatus
KR20210107656A (en) * 2018-12-18 2021-09-01 가부시키가이샤 도쿠야마 silicon etchant
EP4131344A4 (en) * 2020-03-23 2024-04-10 Nissan Chemical Corporation SEMICONDUCTOR SUBSTRATE CLEANING METHOD, METHOD FOR PRODUCING A PROCESSED SEMICONDUCTOR SUBSTRATE, AND COMPOSITION FOR PEELING

Citations (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100503268B1 (en) 2002-10-29 2005-07-22 동우 화인켐 주식회사 Cleaning Solution Comprising Ether and Ketone for Removing Edge Beads and Washing Process Using the Same
US20060122084A1 (en) * 2004-12-06 2006-06-08 Park Jung-Dae Composition for removing photoresist, method of removing photoresist and method of manufacturing a semiconductor device using the same
KR100664403B1 (en) 2005-01-31 2007-01-03 테크노세미켐 주식회사 Etch residue cleaning composition and cleaning method using the same
US20100105595A1 (en) * 2008-10-29 2010-04-29 Wai Mun Lee Composition comprising chelating agents containing amidoxime compounds
US7951765B2 (en) 2005-08-13 2011-05-31 Techno Semichem Co., Ltd. Photoresist stripper composition for semiconductor manufacturing
US20110180747A1 (en) * 2009-10-24 2011-07-28 Wai Mun Lee Trioka Acid Semiconductor Cleaning Compositions and Methods of Use
US20120015857A1 (en) * 2009-01-28 2012-01-19 Advanced Technology Materials, Inc. Lithographic tool in situ clean formulations
KR101128856B1 (en) 2011-03-08 2012-03-23 주식회사 엘지생활건강 Environment-friendly solvent for water-cleaning and dry-cleaning, and composition for cleaning containing the same solvent
US20130123411A1 (en) * 2009-03-27 2013-05-16 Eastman Chemical Company Compositions and Methods for Removing Organic Substances
US8685908B2 (en) * 2011-02-28 2014-04-01 The Procter & Gamble Company Bar soap comprising pyrithione sources
US8685909B2 (en) 2006-09-21 2014-04-01 Advanced Technology Materials, Inc. Antioxidants for post-CMP cleaning formulations
US20140106137A1 (en) 2012-10-11 2014-04-17 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, wafer processing member, temporary adhering material for processing wafer, and manufacturing method of thin wafer
KR101413079B1 (en) 2010-10-07 2014-06-30 제일모직 주식회사 (meth)acrylate based polymer and photosensitive resist composition including the same
JP2014133855A (en) 2012-12-11 2014-07-24 Fujifilm Corp Remover of siloxane resin, method for removing siloxane resin using the same, and methods for manufacturing semiconductor substrate product and semiconductor element
US20150099216A1 (en) * 2013-10-04 2015-04-09 Shin-Etsu Chemical Co., Ltd. Method for manufacturing a resist composition
US20150111804A1 (en) * 2013-10-21 2015-04-23 Fujifilm Electronic Materials U.S.A., Inc. Cleaning formulations for removing residues on surfaces
US20150114429A1 (en) * 2012-05-18 2015-04-30 Atmi Taiwan Co., Ltd. Aqueous clean solution with low copper etch rate for organic residue removal improvement
KR20150111529A (en) 2014-03-25 2015-10-06 삼성전자주식회사 Cleaning composition applied to semiconductor device
US20160071762A1 (en) 2013-12-16 2016-03-10 Ingoo Kang Method of fabricating semiconductor device
WO2016068290A1 (en) * 2014-10-31 2016-05-06 関東化學株式会社 Composition for removing photoresist residue and/or polymer residue
US9352542B2 (en) 2012-02-07 2016-05-31 Tokyo Ohka Kogyo Co., Ltd. Processing method and processing apparatus
US20160326414A1 (en) 2014-01-29 2016-11-10 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer
US20170069521A1 (en) 2014-03-18 2017-03-09 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer
US20170101555A1 (en) 2015-10-08 2017-04-13 Shin-Etsu Chemical Co., Ltd. Temporary adhesion method and method for producing thin wafer
US20170110360A1 (en) 2015-10-19 2017-04-20 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer
US20190016999A1 (en) * 2015-08-03 2019-01-17 Fujifilm Electronic Materials U.S.A., Inc. Cleaning composition
US20190079409A1 (en) * 2016-06-03 2019-03-14 Fujifilm Corporation Treatment liquid, method for washing substrate, and method for removing resist

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100540525B1 (en) * 2000-04-26 2006-01-11 다이킨 고교 가부시키가이샤 Cleaning composition
JP5802106B2 (en) * 2010-11-15 2015-10-28 東京応化工業株式会社 Laminate and separation method
KR101974224B1 (en) * 2012-11-09 2019-05-02 동우 화인켐 주식회사 Composition for removing an adhesive polymer

Patent Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100503268B1 (en) 2002-10-29 2005-07-22 동우 화인켐 주식회사 Cleaning Solution Comprising Ether and Ketone for Removing Edge Beads and Washing Process Using the Same
US20060122084A1 (en) * 2004-12-06 2006-06-08 Park Jung-Dae Composition for removing photoresist, method of removing photoresist and method of manufacturing a semiconductor device using the same
KR100669866B1 (en) 2004-12-06 2007-01-16 삼성전자주식회사 Composition for removing photoresist, method for removing photoresist using same, and method for manufacturing semiconductor device
KR100664403B1 (en) 2005-01-31 2007-01-03 테크노세미켐 주식회사 Etch residue cleaning composition and cleaning method using the same
US7951765B2 (en) 2005-08-13 2011-05-31 Techno Semichem Co., Ltd. Photoresist stripper composition for semiconductor manufacturing
US8685909B2 (en) 2006-09-21 2014-04-01 Advanced Technology Materials, Inc. Antioxidants for post-CMP cleaning formulations
US20100105595A1 (en) * 2008-10-29 2010-04-29 Wai Mun Lee Composition comprising chelating agents containing amidoxime compounds
US20120015857A1 (en) * 2009-01-28 2012-01-19 Advanced Technology Materials, Inc. Lithographic tool in situ clean formulations
US20130123411A1 (en) * 2009-03-27 2013-05-16 Eastman Chemical Company Compositions and Methods for Removing Organic Substances
US20110180747A1 (en) * 2009-10-24 2011-07-28 Wai Mun Lee Trioka Acid Semiconductor Cleaning Compositions and Methods of Use
KR101413079B1 (en) 2010-10-07 2014-06-30 제일모직 주식회사 (meth)acrylate based polymer and photosensitive resist composition including the same
US8685908B2 (en) * 2011-02-28 2014-04-01 The Procter & Gamble Company Bar soap comprising pyrithione sources
KR101128856B1 (en) 2011-03-08 2012-03-23 주식회사 엘지생활건강 Environment-friendly solvent for water-cleaning and dry-cleaning, and composition for cleaning containing the same solvent
US8882853B2 (en) 2011-03-08 2014-11-11 Lg Household & Health Care Ltd. Environmentally-friendly solvent for washing and dry-cleaning, and laundry composition including the same
US9352542B2 (en) 2012-02-07 2016-05-31 Tokyo Ohka Kogyo Co., Ltd. Processing method and processing apparatus
US20150114429A1 (en) * 2012-05-18 2015-04-30 Atmi Taiwan Co., Ltd. Aqueous clean solution with low copper etch rate for organic residue removal improvement
US20140106137A1 (en) 2012-10-11 2014-04-17 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, wafer processing member, temporary adhering material for processing wafer, and manufacturing method of thin wafer
JP2014133855A (en) 2012-12-11 2014-07-24 Fujifilm Corp Remover of siloxane resin, method for removing siloxane resin using the same, and methods for manufacturing semiconductor substrate product and semiconductor element
US20150099216A1 (en) * 2013-10-04 2015-04-09 Shin-Etsu Chemical Co., Ltd. Method for manufacturing a resist composition
US20150111804A1 (en) * 2013-10-21 2015-04-23 Fujifilm Electronic Materials U.S.A., Inc. Cleaning formulations for removing residues on surfaces
US20160071762A1 (en) 2013-12-16 2016-03-10 Ingoo Kang Method of fabricating semiconductor device
US20160326414A1 (en) 2014-01-29 2016-11-10 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer
US20170069521A1 (en) 2014-03-18 2017-03-09 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer
KR20150111529A (en) 2014-03-25 2015-10-06 삼성전자주식회사 Cleaning composition applied to semiconductor device
WO2016068290A1 (en) * 2014-10-31 2016-05-06 関東化學株式会社 Composition for removing photoresist residue and/or polymer residue
US20180051237A1 (en) * 2014-10-31 2018-02-22 Kanto Kagaku Kabushiki Kaisha Composition for removing photoresist residue and/or polymer residue
US20190016999A1 (en) * 2015-08-03 2019-01-17 Fujifilm Electronic Materials U.S.A., Inc. Cleaning composition
US20170101555A1 (en) 2015-10-08 2017-04-13 Shin-Etsu Chemical Co., Ltd. Temporary adhesion method and method for producing thin wafer
US20170110360A1 (en) 2015-10-19 2017-04-20 Shin-Etsu Chemical Co., Ltd. Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer
US20190079409A1 (en) * 2016-06-03 2019-03-14 Fujifilm Corporation Treatment liquid, method for washing substrate, and method for removing resist

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210320078A1 (en) * 2018-08-08 2021-10-14 Kuprion Inc. Electronics assemblies employing copper in multiple locations
US11735548B2 (en) * 2018-08-08 2023-08-22 Kuprion Inc. Electronics assemblies employing copper in multiple locations

Also Published As

Publication number Publication date
US10332740B2 (en) 2019-06-25
KR20180069185A (en) 2018-06-25
KR102680736B1 (en) 2024-07-03
US20180211830A1 (en) 2018-07-26
US20190198315A1 (en) 2019-06-27

Similar Documents

Publication Publication Date Title
US11380537B2 (en) Method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer
US10570522B2 (en) Etching solution for copper or copper alloy
KR101878240B1 (en) Siloxane resin remover, siloxane resin removal method using siloxane resin remover, semiconductor substrate product and semiconductor element manufacturing method
CN110178212B (en) Stack substrate handling
US10490417B2 (en) Etching composition
TWI469220B (en) Composition and method for photoresist removal and residue removal in wafer level packaging
EP3320075B1 (en) Photoresist cleaning composition used in photolithography and a method for treating substrate therewith
KR20050025316A (en) Compositions for removing etching residue and use thereof
KR101375100B1 (en) Stripper composition for thick negative photoresist
US11499099B2 (en) Etching composition
US12448568B2 (en) Etching compositions
KR20140107602A (en) Etching method and etching liquid used therein
KR20220043131A (en) Composition for photoresist removal
EP3443418B1 (en) Aqueous solution and process for removing substances from substrates
US6908892B2 (en) Photoresist remover composition
US8012922B2 (en) Wet cleaning solution
KR100774276B1 (en) Compositions comprising tannic acid as corrosion inhibitor
US20230274946A1 (en) Etching compositions
CN118369621A (en) Resin mask stripping method
US20240222180A1 (en) Laminate, method for manufacturing laminate, and method for manufacturing semiconductor substrate
US20240279549A1 (en) Etching compositions
CN112480928A (en) Silicon etching composition and etching method for silicon substrate by using same

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4