US11315887B2

US11315887B2 - Semiconductor structure having dummy pattern around array area and method of manufacturing the same

Info

Publication number: US11315887B2
Application number: US16/902,726
Authority: US
Inventors: Ying-Cheng Chuang; Chung-Lin Huang
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2020-06-16
Filing date: 2020-06-16
Publication date: 2022-04-26
Also published as: US20220122928A1; US20210391282A1; US11557549B2

Abstract

The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

Description

TECHNICAL FIELD

The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. Particularly, the present disclosure relates to a semiconductor structure having a dummy pattern around an array area of a substrate and configured to relieve stress internal to the array area, and a method of manufacturing the semiconductor structure including forming the dummy pattern around the array area of the substrate.

DISCUSSION OF THE BACKGROUND

Semiconductor devices and integrated circuits are becoming more highly integrated. The fabrication of semiconductor devices involves sequentially depositing various material layers over a semiconductor wafer, and patterning the material layers using lithography and etching processes to form microelectronic components, including transistors, diodes, resistors and/or capacitors, on or in the semiconductor wafer.

The semiconductor industry continues to improve the integration density of the microelectronic components by continual reduction of minimum feature size, which allows more components to be integrated into a given area. Smaller package structures with smaller footprints are developed to package the semiconductor devices. In semiconductor memory devices, as the memory capacity of such devices increases, a critical dimension of patterns in the device is reduced. Such reduction may induce internal stress and may result in misalignment or damage to the elements in the device. It is therefore desirable to develop improvements that address the aforementioned challenges.

This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitute prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

In some embodiments, the first elongated member encircles the plurality of fins.

In some embodiments, the first elongated member has a width in a range between 150 nm and 1000 nm.

In some embodiments, the first elongated member extends along a boundary between the periphery region and the array area.

In some embodiments, the substrate includes a second elongated member protruding from the substrate and at least partially surrounding the plurality of fins.

In some embodiments, the second elongated member is disposed between the first elongated member and the plurality of fins.

In some embodiments, the second elongated member is at least partially disposed between two of the plurality of fins.

In some embodiments, the isolation is disposed between the first elongated member and the second elongated member.

In some embodiments, the plurality of fins, the first elongated member and the second elongated member are integrally formed.

In some embodiments, a top surface of the capping layer is substantially coplanar with a top surface of the isolation.

In some embodiments, the isolation is disposed between two of the plurality of fins.

In some embodiments, the first elongated member is a dummy pattern.

In some embodiments, the insulating layer and the isolation include oxide, and the capping layer includes nitride.

In some embodiments, the substrate includes a plurality of blocks protruding from the substrate, disposed in the peripheral region, covered by the capping layer and surrounded by the isolation.

In some embodiments, the plurality of fins, the first elongated member and the plurality of blocks are integrally formed.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes steps of providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.

In some embodiments, the formation of the isolation includes performing a planarizing process to expose a top surface of the capping layer through the isolation.

In some embodiments, the patterning of the hardmask stack includes disposing a photoresist over the hardmask stack, and removing portions of the hardmask stack exposed through the photoresist.

In some embodiments, the method includes removing portions of the substrate exposed through the capping layer and the insulating layer to form a second elongated member between the plurality of fins and the first elongated member.

In some embodiments, the plurality of fins, the first elongated member and the second elongated member are formed simultaneously.

In the present disclosure, a dummy pattern in an elongated configuration is formed to surround fins protruding from a substrate and disposed within an array area. A dummy elongated member is formed over the substrate and configured to relieve internal stress developed in an isolation between the fins in the array area. As such, distortion of the fins in the array area can be minimized. Therefore, reliability and overall performance of the semiconductor structure can be improved.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure are described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be utilized as a basis for modifying or designing other structures, or processes, for carrying out the purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit or scope of the disclosure as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims. The disclosure should also be understood to be coupled to the figures' reference numbers, which refer to similar elements throughout the description.

FIG. 1 is a perspective view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIG. 2 is an enlarged cross-sectional view of a portion AA′ of the semiconductor structure in FIG. 1.

FIG. 3 is an enlarged top view of a portion BB′ of the semiconductor structure in FIG. 1 showing a first elongated member in a first configuration.

FIG. 4 is an enlarged top view of the portion BB′ of the semiconductor structure in FIG. 1 showing the first elongated member in a second configuration.

FIG. 5 is an enlarged top view of a portion BB′ of the semiconductor structure in FIG. 1 showing the first elongated member in a third configuration.

FIG. 6 is a flow diagram illustrating a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

FIGS. 7 through 38 illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor structure in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

FIG. 1 is a schematic perspective view of a semiconductor structure 100 in accordance with some embodiments of the present disclosure. Further, FIG. 2 is an enlarged cross-sectional view of a portion AA′ of the semiconductor structure 100 in FIG. 1, and FIG. 3 is an enlarged top view of a portion BB′ of the semiconductor structure 100 in FIG. 1.

In some embodiments, the semiconductor structure 100 is a part of a die, a package or a device. In some embodiments, the semiconductor structure 100 is a part of a memory device. In some embodiments, the semiconductor structure 100 includes a substrate 101, an insulating layer 102, a capping layer 103 and an isolation 104.

In some embodiments, the substrate 101 is a semiconductive substrate. In some embodiments, the substrate 101 includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the substrate 101 includes bulk semiconductor material. In some embodiments, the substrate 101 is a silicon substrate. In some embodiments, the substrate 101 includes lightly doped monocrystalline silicon. In some embodiments, the substrate 101 is a p-type substrate.

Referring to FIG. 1, the substrate 101 includes a first surface 101 a and a second surface 101 b opposite to the first surface 101 a. In some embodiments, the first surface 101 a is a front side of the substrate 101, wherein electrical devices or components are subsequently formed over the first surface 101 a and configured to electrically connect to an external circuitry. In some embodiments, the second surface 101 b is a back side of the substrate 101, where electrical devices or components are absent.

In some embodiments, the substrate 101 defines a peripheral region 101 c and an array area 101 d at least partially surrounded by the peripheral region 101 c. In some embodiments, the peripheral region 101 c is adjacent to a periphery of the substrate 101, and the array area 101 d is adjacent to a central area of the substrate 101. In some embodiments, the array area 101 d may be used for fabricating field effect vertical transistors. In some embodiments, a boundary 101 e is disposed between the peripheral region 101 c and the array area 101 d.

Referring to FIGS. 1 to 3, the substrate 101 includes several fins 101 f, a first elongated member 101 g disposed in the array area 101 d, a second elongated member 101 h surrounding the fins 101 f, and several blocks 101 i in the peripheral region 101 c. In some embodiments, the fins 101 f, the first elongated member 101 g, the second elongated member 101 h and the blocks 101 i protrude from the substrate 101 or the first surface 101 a of the substrate 101. In some embodiments, the fins 101 f, the first elongated member 101 g, the second elongated member 101 h and the blocks 101 i are integrally formed.

In some embodiments, the fins 101 f are arranged in an array or matrix. In some embodiments, heights of the fins 101 f are consistent with each other. In some embodiments, the height of the fin 101 f is in a range between 30 nm and 200 nm. In some embodiments, a pitch between adjacent pairs of fins 101 f is consistent. In some embodiments, the fin 101 f has a cylindrical shape. In some embodiments, a cross section of the fin 101 f has a circular, oval, quadrilateral or polygonal shape.

In some embodiments, the first elongated member 101 g partially or entirely surrounds the fins 101 f. In some embodiments, the first elongated member 101 g encircles the fins 101 f. In some embodiments, the first elongated member 101 g extends along the boundary 101 e between the peripheral region 101 c and the array area 101 d. In some embodiments, the first elongated member 101 g is a dummy pattern, i.e., the first elongated member 101 g is electrically isolated from circuit or device of the semiconductor structure 100.

In some embodiments, the first elongated member 101 g has a width in a range between 150 nm and 1000 nm. In some embodiments, a distance between the first elongated member 101 g and the outermost fin among the fins 101 f is in a range between 100 nm and 500 nm. In some embodiments, a top cross section of the first elongated member 101 g is in a strip, frame or ring configuration. In some embodiments, the height of the fins 101 f is substantially same as a height of the first elongated member 101 g.

Referring to FIGS. 3 to 5, the first elongated member 101 g can be in various configurations. In some embodiments, as shown in FIG. 3, the first elongated member 101 g surrounds the fins 101 f in a strip configuration. In some embodiments, as shown in FIG. 4, the first elongated member 101 g is in a zig-zag configuration. In some embodiments, as shown in FIG. 5, the first elongated member 101 g comprises several segments, each of which extends along a portion of the boundary 101 e. In some embodiments, the segments are discontinuous and separated from each other.

In some embodiments, the second elongated member 101 h partially or entirely surrounds the fins 101 f. In some embodiments, the second elongated member 101 h encircles the fins 101 f. In some embodiments, the second elongated member 101 h extends between the first elongated member 101 g and the fins 101 f. In some embodiments, the second elongated member 101 h is at least partially disposed between two of the fins 101 f. In some embodiments, the second elongated member 101 h is proximal to the fins 101 f and distal to the first elongated member 101 g.

In some embodiments, the width of the first elongated member 101 g is substantially greater than a width of the second elongated member 101 h. In some embodiments, the second elongated member 101 h has a width in a range between 100 nm and 800 nm. In some embodiments, a distance between the second elongated member 101 h and the outermost fin among the fins 101 f is in a range between 50 nm and 500 nm. In some embodiments, a top cross section of the second elongated member 101 h is in a strip, frame or ring configuration. In some embodiments, the height of the fins 101 f is substantially same as a height of the second elongated member 101 h. In some embodiments, the height of the first elongated member 101 g is substantially same as the height of the second elongated member 101 h.

In some embodiments, the blocks 101 i protrude from the substrate 101 and are disposed in the peripheral region 101 c. In some embodiments, the blocks 101 i at least partially surround the array area 101 d. In some embodiments, a cross section of the block 101 has a quadrilateral or polygonal shape. In some embodiments, a width of the block 101 i is substantially greater than the width of the fin 101 f. In some embodiments, the height of the block 101 i is substantially same as the height of the fin 101 f. In some embodiments, the height of the block 101 i is substantially same as the height of the first elongated member 101 g.

Referring to FIG. 1, the insulating layer 102 is disposed over the substrate 101. In some embodiments, the insulating layer 102 is disposed in the peripheral region 101 c and the array area 101 d. In some embodiments, the insulating layer 102 is disposed over the fins 101 f, the first elongated member 101 g, the second elongated member 101 h and the blocks 101 i. In some embodiments, the insulating layer 102 covers and contacts the first surface 101 a, top surfaces of the fins 101 f, a top surface of the first elongated member 101 g, a top surface of the second elongated member 101 h and top surfaces of the block 101 i. In some embodiments, the insulating layer 102 includes oxide.

In some embodiments, the capping layer 103 is disposed over and in contact with the insulating layer 102. In some embodiments, the capping layer 103 is disposed in the peripheral region 101 c and the array area 101 d. In some embodiments, the capping layer 103 is disposed over the first surface 101 a, the top surfaces of the fins 101 f, the top surface of the first elongated member 101 g, the top surface of the second elongated member 101 h and the top surfaces of the block 101 i. In some embodiments, the capping layer 103 has a thickness substantially greater than a thickness of the insulating layer 102. In some embodiments, the capping layer 103 includes nitride.

In some embodiments, the isolation 104 surrounds the fins 101 f, the first elongated member 101 g, the second elongated member 101 h, the block 101 i, the insulating layer 102 and the capping layer 103. In some embodiments, the isolation 104 is disposed between the first elongated member 101 g and the second elongated member 101 h, between the fins 101 f and the second elongated member 101 h, and between the fins 101 f. In some embodiments, at least a portion of the top surface of the capping layer 103 is exposed through the isolation 104. In some embodiments, the top surface of the capping layer 103 is substantially coplanar with a top surface of the isolation 104. In some embodiments, the isolation 104 includes oxide. In some embodiments, the insulating layer 102 and the isolation 104 include same or different dielectric materials.

FIG. 6 is a flow diagram illustrating a method S200 of manufacturing a semiconductor structure 100 in accordance with some embodiments of the present disclosure. FIGS. 7 to 36 are schematic diagrams illustrating various fabrication stages according to the method S200 for manufacturing the semiconductor structure 100 in accordance with some embodiments of the present disclosure. The stages shown in FIGS. 7 to 36 are also illustrated schematically in the flow diagram in FIG. 6. In the subsequent discussion, the fabrication stages shown in FIGS. 7 to 36 are discussed in reference to the steps shown in FIG. 6. The method S200 includes a number of operations and the description and illustration are not deemed as a limitation of the sequence of the operations. The method S200 includes a number of steps (S201, S202, S203, S204, S205, S206, S207, S208, S209 and S210).

Referring to FIG. 7, a substrate 101 is provided or received according to step S201 in FIG. 6. In some embodiments, the substrate 101 includes bulk semiconductor material, for example silicon. In some embodiments, the substrate 101 may be lightly doped monocrystalline silicon. In some embodiments, the substrate 101 may be a p-type substrate.

In some embodiments, the substrate 101 defines a peripheral region 101 c and an array area 101 d at least partially surrounded by the peripheral region 101 c. In some embodiments, the substrate 101 defines a boundary 101 e between the peripheral region 101 c and the array area 101 d.

Referring to FIG. 7, an insulating layer 102 is disposed over the substrate 101 according to step S202 in FIG. 6. In some embodiments, the insulating layer 120 is in contact with the substrate 101. In some embodiments, the insulating layer 102 includes oxide such as silicon oxide. In some embodiments, the insulating layer 102 is formed using a chemical vapor deposition (CVD) process, a thermal oxidation process or any other suitable process.

Referring to FIG. 7, a capping layer 103 is disposed over the insulating layer 102 according to step S203 in FIG. 6. In some embodiments, the capping layer 103 is disposed on the insulating layer 102. In some embodiments, the capping layer 103 includes nitride, e.g., silicon nitride. In some embodiments, the capping layer 103 may be formed using a CVD process or any other suitable process.

Referring to FIG. 8, a first hardmask stack 105 is disposed on the capping layer 103 according to step S204 in FIG. 6. In some embodiments, the first hardmask stack 105 includes several layers stacked over each other. In some embodiments, the first hardmask stack 105 includes a first layer 105 a, a second layer 105 b, a third layer 105 c, a fourth layer 105 d, a fifth layer 105 e and a sixth layer 105 f. In some embodiments, the first layer 105 a, the second layer 105 b, the third layer 105 c, the fourth layer 105 d, the fifth layer 105 e and the sixth layer 105 f are sequentially formed over the capping layer 103.

In some embodiments, the first layer 105 a is disposed on the capping layer 103. In some embodiments, the first layer 105 a includes carbon. In some embodiments, the first layer 105 a is formed by a CVD process or any other suitable process. In some embodiments, the second layer 105 b is disposed over the first layer 105 a. In some embodiments, the second layer 105 b includes nitride. In some embodiments, the second layer 105 b is formed by a CVD process or any other suitable process. In some embodiments, the first layer 105 a and the second layer 105 b have different compositions from each other to enable selective etching of each relative to the other.

In some embodiments, the third layer 105 c is disposed on the second layer 105 b. In some embodiments, the third layer 105 c includes polysilicon. In some embodiments, the third layer 105 c is formed by a CVD process or any other suitable process. In some embodiments, the fourth layer 105 d is disposed on the third layer 105 c. In some embodiments, the fourth layer 105 d includes oxide, e.g., silicon oxide. In some embodiments, the fourth layer 105 d is formed by a CVD process or any other suitable process. In some embodiments, the deposition of the third layer 105 c and the fourth layer 105 d may be performed in-situ to save processing time and reduce possibility of contamination. As used herein, the term “in-situ” is used to refer to processes in which the substrate 101 being processed is not exposed to an external ambient (e.g., external to the processing system) environment.

In some embodiments, the fifth layer 105 e is disposed on the fourth layer 105 d. In some embodiments, the fifth layer 105 e includes carbon. In some embodiments, the fifth layer 105 e is a sacrificial layer. In some embodiments, the fifth layer 105 e may be formed using a CVD process or any other suitable process. In some embodiments, after the deposition of the fifth layer 105 e, a polish process may be performed to obtain a flat surface.

In some embodiments, the sixth layer 105 f is disposed on the fifth layer 105 e. In some embodiments, the sixth layer 105 f includes dielectric material such as nitride or oxynitride. In some embodiments, the sixth layer 105 f is an antireflective coating (ARC) layer. In some embodiments, the sixth layer 105 f may be formed by a plasma-enhanced CVD (PECVD) process.

Referring to FIG. 9, the first hardmask stack 105 is patterned according to step S205 in FIG. 6. In some embodiments, the patterning of the first hardmask stack 105 includes disposing a first photoresist 106 over the first hardmask stack 105, and removing portions of the first hardmask stack 105 exposed through the first photoresist 106. In some embodiments, the first photoresist 106 is patterned after the disposing of the first photoresist 106 and before the removal of portions of the first hardmask stack 105. In some embodiments, the first photoresist 106 is patterned by photolithography, etching or any other suitable process.

In some embodiments, the first photoresist 106 includes several slots 106 a over the first hardmask stack 105. In some embodiments, portions of the sixth layer 105 f are exposed through the first photoresist 106. In some embodiments, the sixth layer 105 f is formed between the fifth layer 105 e and the first photoresist 106 in order to eliminate problems associated with reflection of light when exposing the first photoresist 106. In some embodiments, the sixth layer 105 f may stabilize an etching selectivity of the fifth layer 105 e.

Referring to FIG. 10, portions of the fourth layer 105 d, the fifth layer 105 e and the sixth layer 105 f exposed through the first photoresist 106 are removed. In some embodiments, after the removal of the portions of the fourth layer 105 d, the fifth layer 105 e and the sixth layer 105 f exposed through the first photoresist 106, the first photoresist 106 and the remaining portion of the sixth layer 105 f are removed.

Referring to FIG. 11, an oxide layer 107 is disposed conformal to the fifth layer 105 e. In some embodiments, a coating 108 is disposed over the oxide layer 107. In some embodiments, the coating 108 is an antireflective coating (ARC).

Referring to FIG. 12 and FIG. 13 showing an enlarged view of a portion CC′ in FIG. 12, portions of the oxide layer 107 and portions of the fifth layer 105 e are sequentially removed. In some embodiments, the portions of the oxide layer 107 are removed by dry etching or any other suitable process. In some embodiments, some portions of the oxide layer 107 are left remaining on the fourth layer 105 d. As a result, a top surface of the oxide layer 107 is substantially coplanar with a top surface of the fourth layer 105 d. In some embodiments, portions of the fourth layer 105 d, portions of the third layer 105 c and portions of the second layer 105 b in the array area 101 d are sequentially removed. As such, several strips 109 protruding from the second layer 105 b are formed in the array area 101 d.

Referring to FIG. 14, a seventh layer 110 is disposed over the fourth layer 105 d and the oxide layer 107, and an eighth layer 111 is then disposed over the seventh layer 110. In some embodiments, the seventh layer 110 fills gaps between the strips 109. In some embodiments, the seventh layer 110 includes carbon. In some embodiments, the seventh layer 110 is a sacrificial layer. In some embodiments, the seventh layer 110 may be formed using a CVD process or any other suitable process. In some embodiments, after the deposition of the seventh layer 110, a polish process may be performed to obtain a flat surface.

In some embodiments, the eighth layer 111 is disposed on the seventh layer 110. In some embodiments, the eighth layer 111 includes dielectric material such as nitride or oxynitride. In some embodiments, the eighth layer 111 is an antireflective coating (ARC) layer. In some embodiments, the eighth layer 111 may be formed by a plasma-enhanced CVD (PECVD) process.

Referring to FIG. 15, a second photoresist 112 is disposed over the eighth layer 111. In some embodiments, the second photoresist 112 includes a first portion 112 a, a second portion 112 b and several third portions 112 c. In some embodiments, the second photoresist 112 is patterned by removing portions of the second photoresist 112 to form the first portion 112 a, the second portion 112 b and the third portions 112 c. In some embodiments, the second photoresist 112 is patterned by photolithography, etching or any other suitable process. In some embodiments, the first portion 112 a is disposed within the array area 101 d. In some embodiments, the second portion 112 b is disposed within the array area 101 d and extends along the boundary 101 e. In some embodiments, the third portions 112 c are disposed within the peripheral region 101 c.

After the disposing of the second photoresist 112 over the eighth layer 111, several removal steps are performed. FIGS. 16 to 22 are enlarged views of a portion DD′ in FIG. 15 and illustrate the removal steps performed at the portion DD′, and FIGS. 23 to 28 are enlarged views of a portion EE′ in FIG. 15 and illustrate the removal steps performed at the portion EE′.

Referring to FIG. 16, the second portion 112 b of the second photoresist 112 covers the eighth layer 111. Referring to FIG. 17, portions of the eighth layer 111 and portions of the seventh layer 110 exposed through the second portion 112 b of the second photoresist 112 are removed. In some embodiments, several openings 110 a are formed. In some embodiments, the remaining portion of the eighth layer 111 is removed after the formation of the openings 110 a.

In some embodiments, the eighth layer 111 is removed by dry etching or any other suitable process. In some embodiments, the second photoresist 112 is removed by an ashing process, a wet strip process or any other suitable process. In some embodiments, the second photoresist 112 may be chemically altered so that it no longer adheres to the remaining portion of the eighth layer 111. In some embodiments, the remaining portion of the eighth layer 111 is then removed to expose the remaining portion of the seventh layer 110.

Referring to FIG. 18, the remaining portion of the seventh layer 110 is removed and the strips 109 are exposed. In some embodiments, the remaining portion of the seventh layer 110 is removed by dry etching or any other suitable process. Referring to FIG. 19, portions of the second layer 105 b are further removed. In some embodiments, the portions of the second layer 105 b are removed by dry etching or any other suitable process. In some embodiments, several portions of the second layer 105 b are left remaining and are isolated from each other. In some embodiments, after the further removal of the portions of the second layer 105 b, the oxide layer 107, the fourth layer 105 d and the third layer 105 c are also removed.

Referring to FIG. 20, portions of the first layer 105 a exposed through the remaining portion of the second layer 105 b are removed. In some embodiments, the portions of the first layer 105 a are removed by dry etching or any other suitable process. In some embodiments, several portions of the first layer 105 a are left remaining and are isolated from each other. In some embodiments, the remaining portions of the second layer 105 b are removed after the removal of the portions of the first layer 105 a.

Referring to FIG. 21, portions of the capping layer 103 and portions of the insulating layer 102 exposed through the remaining portions of the first layer 105 a are removed. In some embodiments, the portions of the capping layer 103 and the portions of the insulating layer 102 are removed simultaneously, sequentially or separately. In some embodiments, the portions of the capping layer 103 are removed, and then the portions of the insulating layer 102 are removed. In some embodiments, the portions of the capping layer 103 are removed by dry etching or any other suitable process. In some embodiments, the portions of the insulating layer 102 are removed by dry etching or any other suitable process.

Referring to FIG. 22, portions of the substrate 101 exposed through the remaining portions of the insulating layer 102, the remaining portions of the capping layer 103 and the remaining portions of the first layer 105 a are removed to form several fins 101 f protruding from the substrate 101. In some embodiments, the portions of the substrate 101 are removed by dry etching or any other suitable process. In some embodiments, the fins 101 f are separated from each other. In some embodiments, the fin 101 f has a configuration similar to that of the fin 101 f described above or illustrated in FIG. 1.

As mentioned above, after the disposing of the second photoresist 112 over the eighth layer 111 as shown in FIG. 15, several removal steps are performed. FIGS. 23 to 28 are enlarged views of the portion EE′ in FIG. 15 and illustrate the removal steps performed at the portion EE′. In some embodiments, the removal steps performed at the portion EE′ are similar to the removal steps performed at the portion DD′ described above or illustrated in FIGS. 16 to 22.

Referring to FIG. 23, the first portion 112 a of the second photoresist 112 covers the eighth layer 111. Referring to FIG. 24, portions of the eighth layer 111 and portions of the seventh layer 110 exposed through the first portion 112 a of the second photoresist 112 are removed. In some embodiments, the remaining portion of the eighth layer 111 is then removed. In some embodiments, the eighth layer 111 is removed by dry etching or any other suitable process. In some embodiments, the second photoresist 112 is removed by an ashing process, a wet strip process or any other suitable process. In some embodiments, the second photoresist 112 may be chemically altered so that it no longer adheres to the remaining portion of the eighth layer 111. In some embodiments, the remaining portion of the eighth layer 111 is then removed to expose the remaining portion of the seventh layer 110.

Referring to FIG. 25, portions of the fourth layer 105 d, portions of the third layer 105 c and portions of the second layer 105 b exposed through the remaining portion of the seventh layer 110 are removed sequentially. In some embodiments, the remaining portion of the seventh layer 110 is removed by dry etching or any other suitable process.

Referring to FIG. 26, portions of the first layer 105 a exposed through the remaining portions of the second layer 105 b are removed. In some embodiments, the portions of the first layer 105 a are removed by dry etching or any other suitable process. In some embodiments, the remaining portion of the second layer 105 b is then removed after the removal of portions of the first layer 105 a.

Referring to FIG. 27, portions of the capping layer 103 exposed through the remaining portion of the first layer 105 a are removed according to step S206 in FIG. 6. In some embodiments, the portions of the capping layer 103 are removed by dry etching or any other suitable process. In some embodiments, portions of the insulating layer 102 exposed through the remaining portion of the first layer 105 a are removed according to step S207 in FIG. 6. In some embodiments, the portions of the insulating layer 102 are removed by dry etching or any other suitable process. In some embodiments, the portions of the capping layer 103 and the portions of the insulating layer 102 are removed simultaneously, sequentially or separately. In some embodiments, the portions of the capping layer 103 are removed, and then the portions of the insulating layer 102 are removed.

Referring to FIG. 28, portions of the substrate 101 exposed through the remaining portion of the insulating layer 102, the remaining portion of the capping layer 103 and the remaining portion of the first layer 105 a are removed to form a first elongated member 101 g protruding from the substrate 101 according to step S208 in FIG. 6. In some embodiments, the portions of the substrate 101 are removed by dry etching or any other suitable process. In some embodiments, the first elongated member 101 g is separated from the fins 101 f. In some embodiments, the first elongated member 101 g has a configuration similar to that of the first elongated member 101 g described above or illustrated in FIG. 1.

Referring to FIG. 29, the remaining portion of the first layer 105 a is removed by dry etching or any other suitable process. In some embodiments, the remaining portion of the first layer 105 a is a part of a hardmask stack. In some embodiments, the hardmask stack is removed according to step S209 in FIG. 6. As mentioned above, after the disposing of the second photoresist 112 over the eighth layer 111 as shown in FIG. 15, several removal steps are performed. FIG. 30 illustrates the intermediate structure after the removal steps described above. In some embodiments, the portion DD′ in FIG. 15 becomes a portion FF′ in FIG. 30, and the portion EE′ in FIG. 15 becomes a portion GG′ in FIG. 30. FIG. 31 illustrates an enlarged view of the portion FF′, and FIG. 32 illustrates an enlarged view of the portion GG′.

Referring to FIG. 30, a second elongated member 101 h is formed in a way similar to the above steps of forming the first elongated member 101 g or the fins 101 f. In some embodiments, the second elongated member 101 h is formed between the fins 101 f and the first elongated member 101 g. In some embodiments, the second elongated member 101 h, the first elongated member 101 g and the fins 101 f are formed simultaneously or sequentially. In some embodiments, the second elongated member 101 h has a configuration similar to that of the second elongated member 101 h described above or illustrated in FIG. 1.

In some embodiments, several blocks 101 i are formed in the peripheral region 101 c. In some embodiments, the blocks 101 i are formed in a way similar to the above steps of forming the first elongated member 101 g or the fins 101 f. In some embodiments, the second elongated member 101 h, the first elongated member 101 g, the fins 101 f and the blocks 101 i are formed simultaneously or sequentially. In some embodiments, the blocks 101 i have a configuration similar to that of the blocks 101 i described above or illustrated in FIG. 1.

Referring to FIG. 33, FIG. 34 showing an enlarged view of a portion HH′ in FIG. 33, and FIG. 35 showing an enlarged view of a portion Jr in FIG. 33, an isolation 104 is formed over the substrate 101 and surrounding the fins 101 f, the first elongated member 101 g, the second elongated member 101 h and the blocks 101 i according to step S210 in FIG. 6. In some embodiments, the isolation 104 is disposed between adjacent fins 101 f, between the first elongated member 101 g and the second elongated member 101 h, and between the fins 101 f and the second elongated member 101 h.

Referring to FIG. 36, FIG. 37 showing an enlarged view of a portion KK′ in FIG. 36, and FIG. 38 showing an enlarged view of a portion LL′ in FIG. 36, a planarizing process is performed to expose the capping layer 103. In some embodiments, a top surface of the capping layer 103 is exposed through the isolation 104. In some embodiments, the top surface of the capping layer 103 is substantially coplanar with a top surface of the isolation 104. Accordingly, a semiconductor structure 100 as shown in FIG. 1 is formed.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.

Claims

What is claimed is:

1. A semiconductor structure, comprising:

a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins;

an insulating layer disposed over the plurality of fins and the first elongated member;

a capping layer disposed over the insulating layer; and

an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

2. The semiconductor structure of claim 1, wherein the first elongated member encircles the plurality of fins.

3. The semiconductor structure of claim 1, wherein the first elongated member has a width in a range between 150 nm and 1000 nm.

4. The semiconductor structure of claim 1, wherein the first elongated member extends along a boundary between the peripheral region and the array area.

5. The semiconductor structure of claim 1, wherein the substrate includes a second elongated member protruding from the substrate and at least partially surrounding the plurality of fins.

6. The semiconductor structure of claim 5, wherein the second elongated member is disposed between the first elongated member and the plurality of fins.

7. The semiconductor structure of claim 5, wherein the second elongated member is at least partially disposed between two of the plurality of fins.

8. The semiconductor structure of claim 5, wherein the isolation is disposed between the first elongated member and the second elongated member.

9. The semiconductor structure of claim 5, wherein the plurality of fins, the first elongated member and the second elongated member are integrally formed.

10. The semiconductor structure of claim 1, wherein a top surface of the capping layer is substantially coplanar with a top surface of the isolation.

11. The semiconductor structure of claim 1, wherein the isolation is disposed between two of the plurality of fins.

12. The semiconductor structure of claim 1, wherein the first elongated member is a dummy pattern.

13. The semiconductor structure of claim 1, wherein the insulating layer and the isolation include oxide, and the capping layer includes nitride.

14. The semiconductor structure of claim 1, wherein the substrate includes a plurality of blocks protruding from the substrate, disposed in the peripheral region, covered by the capping layer and surrounded by the isolation.

15. The semiconductor structure of claim 14, wherein the plurality of fins, the first elongated member and the plurality of blocks are integrally formed.