US11256441B2 - Semiconductor system and method for operating semiconductor system for reducing time to perform initialization of a universal flash storage (UFS) host - Google Patents
Semiconductor system and method for operating semiconductor system for reducing time to perform initialization of a universal flash storage (UFS) host Download PDFInfo
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- US11256441B2 US11256441B2 US16/795,110 US202016795110A US11256441B2 US 11256441 B2 US11256441 B2 US 11256441B2 US 202016795110 A US202016795110 A US 202016795110A US 11256441 B2 US11256441 B2 US 11256441B2
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- G—PHYSICS
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- One or more example embodiments of the disclosure relate to a semiconductor system and a method for operating the semiconductor system.
- One or more example embodiments of the disclosure provide a semiconductor system and a method for operating the semiconductor system that are capable of reducing a time to perform initialization of a universal flash storage (UFS) host so that the connection between the UFS host and a UFS device can be quickly established when an application processor that controls the UFS host exits a suspend mode.
- UFS universal flash storage
- a semiconductor system comprising a UFS host comprising a host controller interface, a UniPro and a M-PHY; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor configured to control the UFS host.
- the UFS device is configured to maintain a power-on status when the application processor operates in a suspend mode.
- a semiconductor system comprising a universal flash storage (UFS) host, the UFS host comprising a host controller interface, a UniPro and a M-PHY; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor which controls the UFS host.
- the UFS device is configured to maintain a power-on status when the UFS host is in a power-off status.
- a method for operating a semiconductor system comprising storing, by an application processor, at least one of a setting value or status information relating to at least one of a host controller interface, a UniPro, or a M-PHY of a universal flash storage (UFS) host; entering, by the UFS device, a hibernation mode; controlling, by the application processor, the UFS host to enter a suspend mode; exiting, by the application processor, the suspend mode; restoring, by the application processor, the at least one of the setting value or the status information relating to the at least one of the host controller interface, the UniPro, or the M-PHY of the UFS host; and exiting, by the UFS device, the hibernation mode.
- UFS universal flash storage
- FIG. 1 is a diagram for explaining a semiconductor system according to an example embodiment of the disclosure
- FIG. 2 is a diagram for explaining a semiconductor system according to an example embodiment of the disclosure.
- FIG. 3 is a diagram for explaining an operation of a UFS device according to an example embodiment of the disclosure.
- FIG. 4 is a diagram for explaining a method for operating a semiconductor system according to an example embodiment of the disclosure.
- FIG. 5 is a diagram for explaining a method for operating a semiconductor system according to an example embodiment of the disclosure.
- FIG. 6 is a diagram for explaining a comparative example in which a universal flash storage (UFS) Linkstartup task is performed in comparison with a semiconductor system and a method for operating the semiconductor system according to an example embodiment of the disclosure.
- UFS universal flash storage
- FIG. 1 is a diagram for explaining a semiconductor system according to an example embodiment of the disclosure.
- FIG. 2 is a diagram for explaining the semiconductor system according to an example embodiment of the disclosure.
- a semiconductor system 1 includes an application processor 5 , a universal flash storage (UFS) host 10 , and a UFS device 20 .
- an application processor 5 a universal flash storage (UFS) host 10 , and a UFS device 20 .
- UFS universal flash storage
- the application processor 5 may control the UFS host 10 to store data in the UFS device 20 or may read data from the UFS device 20 . To this end, the application processor 5 may provide a reset signal Reset_n and a reference clock signal RefClk to the UFS device 20 .
- the UFS host 10 may store data on the UFS device 20 in response to a request of the application processor 5 , and may read data from the UFS device 20 and provide the data to the application processor 5 in response to the request of the application processor 5 .
- the UFS host 10 may be connected to the UFS device 20 through a universal flash storage (UFS) interface.
- UFS universal flash storage
- the UFS host 10 may transmit data to the UFS device 20 through data lines DIN 0 , DIN 1 .
- the UFS host 10 may receive data from the UFS device 20 through data lines DOUT 0 , DOUT 1 .
- the data lines DIN 0 , DIN 1 and the data lines DOUT 0 , DOUT 1 may be implemented by differential signal lines, respectively.
- the UFS device 20 may receive a power supply VCC separately from the UFS host 10 , and may maintain a power-on status by the power supply VCC.
- VCC power supply
- VCCQ voltage regulation
- VCCQ 2 voltage regulation
- VCCQ 2 voltage regulation
- VCCQ 2 voltage regulation
- VCCQ 2 voltage regulation
- VCCQ 2 voltage regulation
- the application processor 5 may operate in various power modes. For example, the application processor 5 may operate in a suspend mode to reduce power consumption. For example, when the user does not use a device driven by the application processor 5 for a certain period of time, the application processor 5 may reduce wasteful power consumption by switching the operation mode into the suspend mode.
- the application processor 5 when the application processor 5 enters the suspend mode, the power supply VCC of the UFS device 20 is turned off, and the UFS device 20 may lose setting values and information exchanged with the UFS host 10 .
- the setting values and information mentioned here refer to setting values and information exchanged between the UFS host 10 and the UFS device 20 each other through a Linkstartup task among initialization tasks for establishing the connection between the UFS host 10 and the UFS device 20 through a UFS interface.
- the UFS host 10 needs to exchange the setting values and information with the UFS device 20 again. Accordingly, the UFS host 10 and the UFS device 20 need to perform the Linkstartup task, and need to perform a Power Mode Change task again.
- the Linkstartup task and the Power Mode Change task are performed at a relatively low speed of about 3 Mbps to 9 Mbps.
- the UFS host 10 and the UFS device 20 are capable of exchanging data at a relatively high speed from 12 Gbps (6 Gbps per lane) to 24 Gbps (12 Gbps per lane) through the UFS interface after the Power Mode Change task is performed.
- the semiconductor system 1 may further include a buffer memory.
- the buffer memory may be used as a main memory of the UFS host 10 , or may be used as a cache memory, a temporary memory or the like for temporarily storing the data.
- the buffer memory may include a volatile memory including a dynamic random access memory (DRAM), the scope of the disclosure is not limited thereto.
- DRAM dynamic random access memory
- a semiconductor system 2 includes a UFS host 10 and a UFS device 20 .
- FIG. 2 shows the UFS host 10 and the UFS device 20 described in FIG. 1 in more detail.
- the UFS host 10 includes an application 100 , a UFS driver 110 , a UFS host controller interface 130 , a UFS host UniPro 140 , and a UFS host M-PHY 150 .
- the application 100 may control the semiconductor system 2 , based on a set of commands that is executed on the UFS host 10 and may be used in the semiconductor system 2 .
- the UFS driver 110 may drive the UFS device 20 connected to the UFS host 10 . Specifically, the UFS driver 110 may receive a command for controlling the UFS device 20 from the application 100 , process the command using the UFS host controller interface 130 , and may provide a processing result thereof to the application 100 .
- the UFS host controller interface 130 controls overall operations within the UFS host 10 .
- the UFS host controller interface 130 may transmit data stored in the buffer memory to the UFS device 20 through the UFS host UniPro 140 and the UFS host M-PHY 150 in response to a write command received from the UFS driver 110 .
- the UFS host controller interface 130 may also receive the data from the UFS device 20 through the UFS host UniPro 140 and the UFS host M-PHY 150 in response to the read command received from the UFS driver 110 .
- the UFS host UniPro 140 and the UFS host M-PHY 150 exchange data with a UFS device UniPro 250 and a UFS device M-PHY 260 of the UFS device 20 , which will be described below, through data lines DIN, DOUT.
- the UFS device 20 includes a user storage 200 , a logic unit 210 , a device level management unit 230 , a descriptor 240 , the UFS device UniPro 250 , and the UFS device M-PHY 260 .
- the user storage 200 may include a flash memory, a magnetoresistive random access memory (MRAM), a phase-change random access memory (PRAM), a ferroelectric random access memory (FeRAM) and the like, the scope of the disclosure is not limited thereto.
- MRAM magnetoresistive random access memory
- PRAM phase-change random access memory
- FeRAM ferroelectric random access memory
- the logic unit 210 , the device level management unit 230 , and the descriptor 240 control the overall operations within the UFS device 20 .
- the logic unit 210 , the device level management unit 230 , and the descriptor 240 may perform tasks of writing, reading and/or erasing data requested by the UFS host 10 on the user storage 200 .
- the UFS device 20 may further include a buffer memory.
- FIG. 3 is a diagram for explaining an operation of a UFS device according to an example embodiment of the disclosure.
- the UFS device 20 of the semiconductor system includes a UFS I/O that receives a reset signal Reset_n and a reference clock signal RefClk from the application processor 5 , a M-PHY which exchanges data with the UFS host 10 , and a NAND I/O BLOCK which provides an interface with a MLC NAND, and includes a core logic which generally controls the UFS I/O, the M-PHY, the NAND I/O BLOCK and the like.
- electric power may be provided to the above elements of the UFS device 20 through one or more power supplies VCC, VCCQ, VCCQ 2 , VDDi, VDDiQ 2 , and the like.
- the UFS device 20 maintains a power-on status, while the application processor 5 operates in the suspend mode.
- the UFS device 20 while the application processor 5 operates in the suspend mode, the UFS device 20 operates in a hibernation mode. Specifically, before the application processor 5 enters the suspend mode, the UFS device 20 may enter the hibernation mode. Before the UFS device 20 enters the hibernation mode, the application processor 5 may store at least one of a setting value or status information in the host controller interface, the UniPro and the M-PHY of the UFS host 10 .
- the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 .
- the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 enters the hibernation mode, and the application processor 5 may not provide the reference clock signal RefClk to the UFS device 20 while the UFS device 20 enters in the hibernation mode.
- the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 exits the hibernation mode.
- the application processor 5 While the application processor 5 operates in the suspend mode, the application processor 5 continues to provide the reset signal Reset_n to the UFS device 20 .
- the UFS device 20 exits the hibernation mode. Specifically, before the UFS device 20 exits the hibernation mode, the application processor 5 restores the at least one of the setting value or the status information relating to at least one of the host controller interface, the UniPro, or the M-PHY of the UFS host 10 .
- the UFS host 10 does not need to perform the UFS Linkstartup task, that is, the UFS host 10 skips the UFS Linkstartup task.
- the UFS host 10 in response to the application processor 5 exiting the suspend mode, the UFS host 10 does not need to perform the UFS Power Mode Change task, that is, the UFS host 10 skips the UFS Power Mode Change task.
- the UFS device 20 maintains a power-on status, while the UFS host 10 is in a power-off status.
- the UFS device 20 While the UFS host 10 is in the power-off status, the UFS device 20 operates in the hibernation mode. Specifically, before the UFS host 10 shifts to the power-off status, the UFS device 20 enters the hibernation mode. Before the UFS device 20 enters the hibernation mode, the application processor 5 stores the at least one of the setting value or the status information in the host controller interface, the UniPro and the M-PHY of the UFS host 10 .
- the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 .
- the application processor 5 provides the reference clock signal RefClk to the UFS device 20 before the UFS device 20 enters the hibernation mode, and the application processor 5 may not provide the reference clock signal RefClk to the UFS device 20 while the UFS device 20 operates in the hibernation mode.
- the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 exits the hibernation mode.
- the application processor 5 continues to provide the reset signal Reset_n to the UFS device 20 .
- the UFS device 20 exits the hibernation mode. Specifically, before the UFS device 20 exits the hibernation mode, the application processor 5 restores the at least one of the setting value or the status information relating to at least one of the host controller interface, the UniPro, or the M-PHY of the UFS host 10 .
- the UFS host 10 in response to a shift of the UFS host 10 to the power-on status, the UFS host 10 does not need to perform the UFS Linkstartup task.
- the UFS host 10 in response to a shift of the UFS host 10 to the power-on status, the UFS host 10 does not need to perform the UFS Power Mode Change task.
- FIG. 4 is a diagram for explaining a method for operating a semiconductor system according to an example embodiment of the disclosure.
- the method for operating the semiconductor system includes storing the at least one of the setting value or the status information relating to at least one of the host controller interface, the UniPro, or the M-PHY of the UFS host 10 (S 401 ).
- the method also includes causing the UFS device 20 to enter the hibernation mode (S 403 ).
- the method also includes causing the application processor 5 for controlling the UFS host 10 to enter a suspend mode (S 405 ).
- the method also includes causing the application processor 5 to exit the suspend mode (S 407 ).
- the method also includes initializing the UFS host 10 (S 409 ).
- the method also includes restoring the at least one of the setting value or the status information relating to at least one of the host controller interface, the UniPro, or the M-PHY of the UFS host 10 (S 411 ).
- the method also includes causing the UFS device 20 to exit the hibernation mode (S 413 ).
- the UFS device 20 may operate in the hibernation mode.
- the application processor 5 may provide a reference clock signal RefClk to the UFS device 20 while the application processor 5 operates in the suspend mode. In some embodiments, the application processor 5 provides the reference clock signal RefClk to the UFS device 20 before entering the hibernation mode, and the application processor 5 may not provide the reference clock signal RefClk to the UFS device 20 while the UFS device 20 operates in the hibernation mode. In some embodiments, the application processor 5 may provide the reference clock signal RefClk to the UFS device 20 before the UFS device 20 exits the hibernation mode.
- the application processor 5 may continue to provide the reset signal Reset_n to the UFS device 20 .
- the UFS host 10 does not perform the UFS Linkstartup task, that is, the UFS host 10 skips the UFS Linkstartup task.
- the UFS host 10 in response to the application processor 5 exiting the suspend mode, the UFS host 10 does not execute the UFS Power Mode Change task, that is, the UFS host 10 skips the UFS Power Mode Change task.
- FIG. 5 is a diagram for explaining a method for operating a semiconductor system according to an example embodiment of the disclosure.
- FIG. 6 is a diagram for explaining a comparative example in which a universal flash storage (UFS) Linkstartup task is performed in comparison with a semiconductor system and a method for operating the semiconductor system according to an example embodiment of the disclosure.
- UFS universal flash storage
- “Sequence 1” indicates a comparative case in which the UFS device does not maintain the power-on status while the application processor 5 operates in the suspend mode. “Sequence 2” indicates a case in which the UFS device remains in a power-on status while the application processor 5 operates in the suspend mode according to an example embodiment.
- FIG. 6 is a diagram specifically showing operations of performing the UFS Linkstartup task.
- the UFS Linkstartup task and the UFS Power Mode Change task need to be performed after the application processor 5 exits the suspend mode.
- the UFS Linkstartup task is a time-consuming task that requires a large number of data exchanges between the UFS host 10 and the UFS device 20 , thereby delaying establishment of connection between the UFS host 10 and the UFS device 20 .
- the suspend and the resume of the application processor 5 are performed in accordance with “Sequence 2”, in which the UFS device 20 is maintained in the power-on status while the application processor 5 operates in the suspend mode. Therefore, it is possible to reduce the time required to re-establish the connection between the UFS host 10 and the UFS device 20 , and to quickly establish the connection between the UFS host 10 and the UFS device 20 .
- At least one of the components, elements, modules or units described herein may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an example embodiment.
- at least one of these components, elements or units may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses.
- at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses.
- At least one of these components, elements or units may further include or implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like.
- a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like.
- CPU central processing unit
- Two or more of these components, elements or units may be combined into one single component, element or unit which performs all operations or functions of the combined two or more components, elements of units.
- at least part of functions of at least one of these components, elements or units may be performed by another of these components, element or units.
- a bus is not illustrated in the block diagrams, communication between the components, elements or units may be performed through the bus.
- Functional aspects of the above example embodiments may be implemented in algorithms that execute on one or more processors.
- the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.
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US20240152362A1 (en) * | 2022-11-08 | 2024-05-09 | Western Digital Technologies, Inc. | Hibernate exit time for ufs devices |
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TWI834883B (en) | 2024-03-11 |
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